CN111710716B - Fin-shaped semiconductor device, manufacturing method thereof and electronic equipment - Google Patents
Fin-shaped semiconductor device, manufacturing method thereof and electronic equipment Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a fin-shaped semiconductor device, a manufacturing method thereof and electronic equipment, which relate to the technical field of semiconductors. The fin-shaped semiconductor device includes: a substrate and a fin field effect transistor formed on the substrate; the fin field effect transistor comprises a source-drain region and a channel layer connected with the source-drain region; the fin field effect transistor further comprises an isolation layer formed between the substrate and the source drain region; wherein the isolation layer is formed by adopting selective oxidation treatment. The manufacturing method of the fin-shaped semiconductor device is used for manufacturing the fin-shaped semiconductor device provided by the technical scheme. The fin-shaped semiconductor device provided by the invention is applied to electronic equipment.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a fin-shaped semiconductor device, a manufacturing method thereof, and an electronic apparatus.
Background
FinFET (Fin Field-Effect Transistor, finFET) can improve the driving performance of the device by using channel materials with higher mobility, but the problem of source-drain leakage has been one of the bottlenecks in improving the performance of high mobility channel FinFET three-dimensional devices. Currently, an SOI (Silicon-On-Insulator) substrate or a punch-through barrier implantation process is mostly used to suppress leakage of source and drain regions. However, the SOI substrate has higher cost, the punch-through barrier layer injection process is easily influenced by factors such as injection depth, source and drain etching depth and the like, and the process control difficulty is higher.
Disclosure of Invention
The invention aims to provide a fin-shaped semiconductor device, a manufacturing method thereof and electronic equipment, and an isolation layer is formed between a source drain region and a substrate through selective oxidation treatment so as to inhibit the leakage of the source drain region.
In a first aspect, the present invention provides a fin-shaped semiconductor device comprising: a substrate and a fin field effect transistor formed on the substrate;
the fin field effect transistor comprises a source-drain region and a channel layer connected with the source-drain region;
the fin field effect transistor further comprises an isolation layer formed between the substrate and the source drain region; wherein the isolation layer is formed by adopting selective oxidation treatment.
In a second aspect, the present invention provides a method for manufacturing a fin-shaped semiconductor device, the method comprising the steps of:
providing a substrate;
forming a fin field effect transistor on a substrate; the fin field effect transistor comprises a source-drain region and a channel layer connected with the source-drain region; the fin field effect transistor further comprises an isolation layer formed between the substrate and the source drain region; wherein the isolation layer is formed by adopting selective oxidation treatment.
In a third aspect, the present invention provides an electronic device, including the fin-shaped semiconductor device provided in the above technical solution.
Compared with the prior art, the fin-shaped semiconductor device provided by the invention has the advantages that the isolation layer is formed between the substrate and the source/drain region. The isolation layer is formed by selective oxidation treatment, so the isolation layer is an oxide isolation layer. The oxide isolation layer is non-conductive, so that the oxide isolation layer can inhibit leakage of the source region and the drain region, and the electrical performance of the semiconductor device is improved. The isolation layer is obtained by partially oxidizing a film layer formed on the substrate, and can reduce the cost to a certain extent compared with an SOI substrate. Furthermore, the isolation layer can be obtained by only carrying out partial oxidation treatment on the film layer formed on the substrate, and compared with a punch-through barrier layer injection process, the isolation layer has the advantages of simple process and reduced process difficulty.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a schematic structural diagram of a fin-shaped semiconductor device according to the present invention;
FIG. 2 is a schematic view of a substrate according to the present invention;
FIG. 3 is a schematic view of a structure of a substrate with an oxidation assisting material layer and a channel material layer formed thereon;
FIG. 4 is a schematic diagram of a structure of a substrate, an oxidation assistant material layer and a channel material layer after a first patterning process according to the present invention;
FIG. 5 is a schematic diagram of a structure after shallow trench isolation is formed;
fig. 6 is a schematic structural diagram of forming a dummy gate material layer on a front channel layer according to the present invention;
FIG. 7 is a schematic diagram of a structure of a dummy gate material layer and a front channel layer after a second patterning process according to the present invention;
FIG. 8 is a schematic diagram of a structure after forming an isolation layer according to the present invention;
FIG. 9 is a schematic diagram of a structure for forming source/drain regions on an isolation layer according to the present invention;
FIG. 10 is a schematic view of a structure with dummy gates removed;
fig. 11 is a schematic structural diagram of the gate stack structure according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The problem of leakage of the source and drain regions is always one of the bottlenecks for improving the performance of the FinFET three-dimensional device. In the prior art, the following two methods are generally adopted for the source leakage and the leakage:
(1) In the manufacture of a semiconductor device, a silicon-on-insulator substrate is selected as a substrate of the semiconductor device, and structures such as a source region and a drain region in the semiconductor device are formed on a buried oxide layer of the silicon-on-insulator substrate. Because the buried oxide layer is a non-conductive insulating layer, the leakage problem of a parasitic channel and a source drain can be solved.
(2) In the process of manufacturing a semiconductor device, after a fin structure formed by a semiconductor material layer is formed, an anti-punch-through implantation treatment is performed on the fin structure to form a punch-through blocking layer at the bottom of the fin structure. The source region, the drain region, the future channel and other structures in the semiconductor device are formed on the punch-through barrier layer, and impurities with high concentration and opposite impurity types to those in the source region and the drain region are injected into the punch-through barrier layer, so that leakage current can be isolated through a PN junction with reverse bias, and parasitic channels and source-drain leakage are restrained.
Although both the above two methods can solve the problems of parasitic channel and source-drain leakage, the first solution is that the cost of the existing silicon-on-insulator substrate is high, so that the manufacturing cost of the semiconductor device is high. When the second approach is used, the anti-punch-through implant may result in an uneven impurity concentration profile in regions within the channel region during the formation of the punch-through barrier. For example: impurities in the punch-through barrier layer are affected by the subsequent high-temperature annealing to diffuse into the channel region, resulting in degradation of carrier mobility inside the channel region, so that the driving performance of the semiconductor device is degraded.
In order to solve the technical problems, the embodiment of the invention provides a fin-shaped semiconductor device, a manufacturing method thereof and electronic equipment. In the fin-shaped semiconductor device provided by the embodiment of the invention, an isolation layer is formed between the substrate and the source drain region. The existence of the isolation layer can solve the problem of electric leakage of the source region and the drain region. In addition, the isolation layer is a film layer formed on the substrate, and a silicon-on-insulator substrate with high cost is not needed, so that the manufacturing cost of the semiconductor device is reduced. Furthermore, the isolation layer can be obtained by only carrying out partial oxidation treatment on the film layer formed on the substrate, and compared with a punch-through barrier layer injection process, the isolation layer has the advantages of simple process and reduced process difficulty.
Referring to fig. 1, fig. 1 shows a schematic structural diagram of a fin-shaped semiconductor device. The fin-shaped semiconductor device includes a substrate 10 and a fin field effect transistor formed on the substrate 10. The finfet includes a source-drain region 70 and a channel layer 40 connected to the source-drain region 70. The fin field effect transistor further includes an isolation layer 30 formed between the substrate 10 and the source drain region 70. Wherein the isolation layer 30 is formed by a selective oxidation process. In order to realize the functionality of the fin-shaped semiconductor device, the fin-shaped semiconductor device further includes a gate stack structure 501 formed on the outer periphery of the channel layer 40, and a sidewall 502 formed on the outer periphery of the gate stack structure 501.
Referring to fig. 1, exemplary source drain regions 70 include a source region 701 formed on one side of a channel layer and a drain region 702 formed on the other side of the channel layer 40. The spacer 30 includes a first spacer 301 formed between the substrate 10 and the source region 701, and a second spacer 302 formed between the substrate 10 and the drain region 702. In the embodiment of the present invention, in order to avoid the leakage and parasitic capacitance caused by the junction depth change, the top of the first isolation layer 301 may be disposed flush with the top of the second isolation layer 302.
Referring to fig. 1, for example, in order to reduce the manufacturing cost of the fin-shaped semiconductor device, the substrate 10 may be a low-cost semiconductor substrate such as a silicon substrate or a silicon germanium substrate. In the case of a fin-shaped semiconductor device for isolating the active regions, shallow trench isolation (shallow trench isolation, STI) 60 is formed on the substrate 10 of the semiconductor. The shallow trench isolation 60 may be made of SiN, si 3 N 4 、SiO 2 Or an insulating material such as SiCO.
Referring to fig. 1, the isolation layer 30 is formed by a selective oxidation process to solve the leakage problem of the source/drain region 70. The isolation layer 30 is formed by selectively oxidizing the auxiliary layer to be oxidized, so that the material of the isolation layer 30 is determined by the material of the auxiliary layer to be oxidized. The material of the auxiliary layer to be oxidized is the same as that of the auxiliary layer to be oxidized 20, and after the selective oxidation treatment is performed on the preset area of the auxiliary layer to be oxidized, the area which is not oxidized forms the auxiliary layer to be oxidized 20. For example, when the oxidation assisting layer 20 is a germanium silicon oxidation assisting layer, the isolating layer 30 may be one or more of a silicon oxide isolating layer, a germanium silicon oxide isolating layer, or a germanium oxide isolating layer.
Referring to fig. 1, in order to satisfy the performance of the device, when the oxidation auxiliary layer 20 is a germanium silicon oxidation auxiliary layer, the mass percentage of germanium element in the germanium silicon oxidation auxiliary layer is 30% -80%. The channel layer 40 is illustratively a silicon channel or a germanium-silicon channel layer. When the channel layer 40 is a germanium-silicon channel layer, the mass percentage of germanium element in the germanium-silicon channel layer is greater than 0% and less than or equal to 50%.
For example, in order to avoid excessive oxidation of the channel layer in forming the isolation layer 30 during fabrication of the fin-shaped semiconductor device, a germanium-silicon oxide auxiliary layer may be provided to have a sufficient oxidation-selective ratio to the germanium-silicon channel layer. At this time, a difference between the mass percentage of the germanium element in the germanium-silicon oxidation auxiliary layer and the mass percentage of the germanium element in the germanium-silicon channel layer may be set to be greater than or equal to 30%.
Referring to fig. 1, when the oxidation auxiliary layer 20 is a germanium-silicon oxidation auxiliary layer, the germanium-silicon oxidation auxiliary layer may be selectively doped for suppressing parasitic channels, and the doping may be an in-situ doping method or an ion implantation method. The ion type of the doping is opposite to that of the source and drain regions. The concentration of the doping ions is 1×10 17 cm -3 -5×10 18 cm -3 。
For example, the doping ions may also be selected according to the type of device when doping the germanium-silicon oxide auxiliary layer. For example, when the fin semiconductor device is N-type, the doped ions may be B. For another example, when the fin semiconductor device is P-type, the doped ions may be one or both of P, as.
Referring to fig. 1, the oxidation assisting layer 20 is formed on the substrate 10, the channel layer 40 is formed on the first region 201 of the oxidation assisting layer 20, and the isolation layer 30 is formed on the second region 202 of the oxidation assisting layer 20. The specific forming mode of the isolation layer 30 is as follows: the spacer layer 30 is obtained by oxidizing a predetermined region of the auxiliary layer to be oxidized by means of selective oxidation. The selective oxidation treatment mode can be a furnace tube oxidation mode or a rapid heat treatment mode. The oxidizing atmosphere of the selective oxidation treatment is oxygen, nitrogen or an atmosphere containing ozone. The temperature and time of the different oxidation treatments may be defined differently. For example: when the oxidation treatment mode is a furnace tube oxidation mode, the temperature of the furnace tube oxidation mode is 500-850 ℃ and the time is 10-60 min. For another example, when the oxidation treatment is a rapid thermal treatment, the rapid thermal treatment is performed at a temperature of 600 to 850 ℃ for a treatment period of 1 to 10 cycles, and the treatment time for each cycle is 30 to 60 seconds.
Referring to fig. 1, for example, in order to achieve isolation of the source and drain regions 70, the isolation layer 30 needs to have a certain thickness, but the excessive thickness of the isolation layer 30 may affect the performance of the device. Based on this, the embodiment of the present invention provides the thickness range of the isolation layer 30 to be 5nm to 50nm. To further balance the isolation effect and the device performance, the thickness of the isolation layer 30 may be set in the range of 10nm to 20nm.
Referring to fig. 1, it can be understood that, in order to obtain the spacer layer 30 having the above thickness, the auxiliary layer to be oxidized needs to have a certain thickness, that is, the thickness of the auxiliary layer to be oxidized is at least greater than or equal to the thickness of the spacer layer 30. For example, the thickness of the auxiliary layer to be oxidized is 5nm-50nm, which is the same as that of the isolation layer. At this time, since the isolation layer 30 is obtained by performing the selective oxidation treatment on the predetermined region of the auxiliary layer to be oxidized, and the first region of the auxiliary layer to be oxidized is a region of the auxiliary layer to be oxidized, which is not subjected to the selective oxidation treatment, the thickness of the first region 201 of the auxiliary layer 20 may be 5nm to 50nm.
Referring to fig. 1, when the spacer layer 30 is formed and the auxiliary layer to be oxidized is oxidized, a predetermined region of the auxiliary layer to be oxidized may be partially oxidized or entirely oxidized in the thickness direction. For example, when the thickness of the isolation layer to be oxidized is large, the preset region of the auxiliary layer to be oxidized may be selectively partially oxidized in the thickness direction. At this time, the predetermined region of the auxiliary oxide layer has a certain thickness after the isolation layer 30 is formed. The thickness may be greater than 0nm and less than or equal to 45nm. The portion of the predetermined region that is not oxidized forms the second region 202 of the oxidation assisting layer 20, and at this time, the isolation layer 30 is formed on the second region 20 of the oxidation assisting layer 20. For another example, when the thickness of the spacer to be oxidized is small, in order to satisfy the isolation effect of the spacer 30, the preset region 202 of the auxiliary layer to be oxidized may be selected to be entirely oxidized in the thickness direction, and the spacer 30 is directly formed on the substrate 10.
The embodiment of the invention also provides a manufacturing method of the fin-shaped semiconductor device. Referring to fig. 2 to 11, the method for fabricating the fin-shaped semiconductor device includes the steps of:
referring to fig. 2, a substrate 10 is provided at step S1. The substrate 10 may be a low-cost semiconductor substrate such as a silicon substrate or a silicon germanium substrate.
Referring to fig. 3, an oxidation assisting material layer 21 is formed on a substrate at step S2. Specifically, the oxidation assisting material layer 21 may be formed by epitaxial method. For example, in order to suppress parasitic channel leakage, the oxidation auxiliary material layer 21 may be doped by an in-situ doping method or ion implantation method. The doped ions are selected according to the type of the fin-shaped semiconductor device. Wherein the ion concentration of the doping is 1×10 17 cm -3 -5×10 18 cm -3 。
As a possible implementation, in the case of doping the oxidation assisting material layer 21 by in-situ doping, the oxidation assisting material layer 21 and the channel material layer 41 may be formed simultaneously by epitaxy in order to simplify the manufacturing process of the semiconductor.
In the embodiment of the present invention, the oxidation auxiliary material layer 21 is a germanium-silicon oxidation auxiliary material layer, and in order to adapt to the performance of the fin-shaped semiconductor device, the mass percentage of germanium element in the germanium-silicon oxidation auxiliary material layer is greater than or equal to 30% and less than or equal to 80%.
Referring to fig. 3, a channel material layer 41 is formed on the oxidation assisting material layer 21 at step S3. The channel material layer 41 may be a silicon channel material layer or a germanium-silicon channel material layer. Illustratively, the germanium element of the germanium-silicon channel material layer is greater than 0% and less than or equal to 50% by mass. In order to satisfy the selective oxidation ratio in the subsequent formation of the isolation layer, the difference between the mass percentage of the germanium element in the germanium-silicon channel material layer and the mass percentage of the germanium element in the germanium-silicon oxidation auxiliary material layer may be set to be greater than 30%.
It will be appreciated that a further protective layer may be epitaxially deposited on the silicon germanium channel material layer in order to protect the germanium silicon channel layer. The material of the protective layer can be silicon.
And S4, patterning the substrate, the oxidation auxiliary material layer and the channel material layer. For example, referring to fig. 4 to 7, patterning the oxidation assisting material layer and the stacked material layer includes the sub-steps of:
s41, referring to fig. 4, a first patterning process is performed on the substrate 10, the oxidation auxiliary material layer 21 and the channel material layer 41, so as to obtain a fin structure, where the fin structure includes, in a bottom-up direction, a fin portion 101 formed by etching a portion of the substrate 10, a layer 22 to be assisted formed by etching a portion of the auxiliary oxide material layer 21, and a front channel layer 42 formed by etching a portion of the channel material layer 41. Wherein 102 in fig. 4 is the base of the substrate.
As a possible implementation, referring to fig. 5, after step S41, the method of manufacturing a semiconductor further includes forming shallow trench isolations 60 on both sides of the fin 101 and the auxiliary layer 22 to be oxidized of the substrate 10, where the shallow trench isolations 60 are used to isolate active regions of the fin-shaped semiconductor device.
S42, referring to fig. 6, dummy gate 50 and sidewall 502 are formed on the outer periphery of front channel layer 42. For example, the dummy gate 50 may be made of silicon in order to meet the etching selectivity of the subsequent manufacturing process.
S43, referring to fig. 7, a second patterning process is performed using the dummy gate 50 and the sidewall 502 as patterns, to obtain the channel layer 40 formed on the auxiliary layer 22 to be oxidized.
For example, the first patterning process may be to cover the channel material layer 41 with a hard mask, and etch the hard mask by using photolithography and etching processes according to a predetermined scheme to form a hard mask pattern. And then, etching the substrate, the oxidation auxiliary material layer and the channel material layer based on the hard mask pattern to form the fin-shaped structure. The second patterning process may be to etch the front channel layer with the dummy gate 50 and the sidewall 502 as masks, based on the mask pattern, to form a channel layer.
S5, referring to fig. 8, a selective oxidation treatment is performed on a predetermined region of the auxiliary layer to be oxidized 22, to obtain the isolation layer 30. The predetermined region of the auxiliary layer 22 to be oxidized is a region where the channel layer is not formed on the auxiliary layer 22 to be oxidized.
As a possible implementation manner, when the auxiliary layer 22 to be oxidized is a silicon germanium auxiliary layer and the channel layer is a silicon germanium channel layer, the difference between the mass percentage of the germanium element in the silicon germanium auxiliary layer and the mass percentage of the germanium element in the channel layer is set to be greater than a preset threshold value, so that the silicon germanium auxiliary layer to be oxidized and the silicon germanium channel layer have a larger oxidation selection ratio. Wherein, the preset threshold value can be 30%. With the above arrangement, the channel layer is not excessively oxidized when the auxiliary layer to be oxidized 22 is selectively oxidized.
Referring to fig. 8, a predetermined region of the auxiliary layer 22 to be oxidized is subjected to a selective oxidation treatment to obtain the isolation layer 30 and the auxiliary layer 20 (including the first region 201 and the second region 202). The selective oxidation treatment mode can be a furnace tube oxidation mode or a rapid heat treatment mode. The oxidizing atmosphere of the selective oxidation treatment is oxygen, nitrogen or an atmosphere containing ozone. The temperature and time of the different oxidation treatments may be defined differently. For example: when the oxidation treatment mode is a furnace tube oxidation mode, the temperature of the furnace tube oxidation mode is 500-850 ℃ and the time is 10-60 min. For another example, when the oxidation treatment is a rapid thermal treatment, the rapid thermal treatment is performed at a temperature of 600 to 850 ℃ and for a treatment period of 1 to 10 cycles, each treatment period is 30 to 60 seconds.
The specific values of the oxidation parameters (temperature and time) in the embodiment of the invention can be determined according to the germanium element in the oxidation auxiliary layer, and the selective oxidation treatment can be performed on the oxidation auxiliary layer under the set oxidation temperature and oxidation time. After the selective oxidation treatment, a thinner oxide layer is formed on the channel layer. In order to improve the performance of the device, the oxide layer can be cleaned and removed before the source drain epitaxy.
Illustratively, in order to be able to achieve isolation of the source and drain regions, the isolation layer needs to have a certain thickness, but excessive thickness of the isolation layer can affect the performance of the device. Based on the above, the thickness range of the isolation layer is set to be 5nm-50nm in the embodiment of the invention. In order to further balance the isolation effect and the device performance, the thickness of the isolation layer may be set in the range of 10nm to 20nm.
S6, referring to FIG. 9, FIG. 9 is a schematic diagram of a structure for forming source/drain regions on an isolation layer according to an embodiment of the present invention. The source and drain regions 70 are a stacked structure, and illustratively, forming the source and drain regions 70 on the spacer layer 30 includes forming a stacked structure of silicon germanium material on the spacer layer 30. The germanium-silicon material laminated structure can be three layers or five layers, and the embodiment of the invention is not limited to the three layers. The mass percentage of germanium element in the germanium-silicon material laminated structure can be the same or different. When the mass percentages of germanium elements in the germanium-silicon material stacked structure are not the same, it may be in the germanium-silicon material stacked structure in consideration of lattice matching degree and stress. The mass percentage of germanium element in each germanium-silicon material layer is gradually increased and then gradually decreased from bottom to top.
S7, referring to FIG. 10, FIG. 10 is a schematic diagram of a structure with dummy gates removed according to an embodiment of the present invention. For example, the dummy gate may be etched. The process of removing the dummy gate in the embodiment of the present invention is the same as the process of removing the sacrificial layer in the conventional method for manufacturing the fin-shaped semiconductor device, and the embodiment of the present invention is not described in detail.
S8, referring to FIG. 11, FIG. 11 is a schematic diagram of a structure after forming a gate stack structure according to an embodiment of the present invention. As an example, referring to fig. 11, a gate stack 501 is formed in a sidewall 502 at the outer periphery of the channel layer 40. Specifically, a gate dielectric layer may be sequentially formed on the outer periphery of the channel layer 40 by atomic layer deposition (Atomic layer deposition, abbreviated as ALD) or the likeAnd a metal gate layer. The gate dielectric layer may be made of HfO 2 、ZrO 2 、TiO 2 Or Al 2 O 3 A material having a relatively high dielectric constant. The metal gate may be made of TiN, taN, tiSiN or other conductive materials.
The embodiment of the invention also provides electronic equipment, which comprises the fin-shaped semiconductor device provided by the embodiment. The electronic device may be a terminal device or a communication device, but is not limited thereto. Further, the terminal device includes a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligent device, a mobile power supply, and the like. The communication device includes a base station and the like, but is not limited thereto.
The beneficial effects of the electronic device provided by the embodiment of the present invention are the same as those of the fin-shaped semiconductor device provided by the above embodiment, and are not described here again.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (13)
1. A fin-shaped semiconductor device, the fin-shaped semiconductor device comprising: a substrate and a fin field effect transistor formed on the substrate;
the fin field effect transistor comprises a source-drain region and a channel layer connected with the source-drain region; the channel layer is a germanium-silicon channel layer; the mass percentage of germanium element in the germanium-silicon channel layer is more than 0% and less than or equal to 50%;
the semiconductor device further includes an isolation layer formed only between the substrate and the source drain region; wherein the isolation layer is formed by adopting selective oxidation treatment; the interface of the channel layer and the source drain region is aligned with the inner side wall of the isolation layer;
the fin-shaped semiconductor device further includes an oxidation assisting layer formed on the substrate, the channel layer is formed on a first region of the oxidation assisting layer, and the isolation layer is formed on a second region of the oxidation assisting layer; the target object of the selective oxidation treatment is an auxiliary layer to be oxidized for manufacturing an oxidation auxiliary layer; the oxidation auxiliary layer is a germanium-silicon oxidation auxiliary layer; the mass percentage of germanium element in the germanium-silicon oxidation auxiliary layer is 30% -80%; and the difference between the mass percentage of germanium element in the germanium-silicon oxidation auxiliary layer and the mass percentage of germanium element in the germanium-silicon channel layer is more than or equal to 30%.
2. The fin-shaped semiconductor device of claim 1, wherein the source and drain regions comprise a source region formed on one side of the channel layer and a drain region formed on the other side of the channel layer;
the isolation layer includes a first isolation layer formed between the substrate and the source region, and a second isolation layer formed between the substrate and the drain region, a top of the first isolation layer being flush with a top of the second isolation layer.
3. The fin-shaped semiconductor device of claim 1, wherein the germanium-silicon oxide auxiliary layer contains a doping ion having a concentration of 1 x 10 17 cm -3 -5×10 18 cm -3 。
4. The fin-shaped semiconductor device of claim 1, wherein the first region has a thickness of 5nm-50 nm;
and/or the thickness of the second region is 0 nm-45 nm.
5. The fin-shaped semiconductor device of any one of claims 1-4, wherein the fin-shaped field effect transistor further comprises a gate stack formed around the channel layer.
6. The fin-shaped semiconductor device of any one of claims 1-4, wherein the spacer layer has a thickness of 5nm-50nm.
7. The manufacturing method of the fin-shaped semiconductor device is characterized by comprising the following steps of:
providing a substrate;
forming a fin field effect transistor and an isolation layer on the substrate; the fin field effect transistor comprises a source-drain region and a channel layer connected with the source-drain region; the isolation layer is formed only between the substrate and the source drain region; wherein the isolation layer is formed by adopting selective oxidation treatment; the channel layer is a germanium-silicon channel layer; the mass percentage of germanium element in the germanium-silicon channel layer is more than 0% and less than or equal to 50%; the interface of the channel layer and the source drain region is aligned with the inner side wall of the isolation layer;
the forming of the fin field effect transistor and the isolation layer on the substrate comprises:
forming an auxiliary material layer to be oxidized and a channel material layer on the substrate;
performing first patterning treatment on the substrate, the auxiliary material layer to be oxidized and the channel material layer to obtain a fin-shaped structure; the fin-shaped structure comprises a fin part formed by performing first patterning treatment on the substrate, an auxiliary layer to be oxidized formed by performing first patterning treatment on the auxiliary material layer to be oxidized, and a front channel layer formed by performing first patterning treatment on the channel material layer;
performing second patterning treatment on the front channel layer to obtain a channel layer;
carrying out selective oxidation treatment on a preset area of the auxiliary layer to be oxidized to obtain an isolation layer and an oxidation auxiliary layer; wherein the channel layer is formed on a first region of the oxidation assisting layer, and the isolation layer is formed on a second region of the oxidation assisting layer; the second region is exposed outside two sides of the channel layer along the length direction of the second region; the oxidation auxiliary layer is a germanium-silicon oxidation auxiliary layer; the mass percentage of germanium element in the germanium-silicon oxidation auxiliary layer is 30% -80%; the difference between the mass percentage of germanium element in the germanium-silicon oxidation auxiliary layer and the mass percentage of germanium element in the germanium-silicon channel layer is more than or equal to 30 percent
And forming a source drain region on the isolation layer.
8. The method of manufacturing a fin-shaped semiconductor device according to claim 7, wherein after the first patterning process is performed on the substrate, the auxiliary material layer to be oxidized, and the channel material layer to obtain a fin-shaped structure, the second patterning process is performed on the front channel layer to obtain a channel layer, and before the forming of the fin-shaped field effect transistor and the isolation layer on the substrate further comprises:
and forming a dummy gate and a side wall on the periphery of the front channel layer.
9. The method of manufacturing a fin-shaped semiconductor device according to claim 8, wherein after performing selective oxidation treatment on the predetermined region of the auxiliary layer to be oxidized to obtain an isolation layer and an oxidation auxiliary layer, before forming a source drain region on the isolation layer, forming a fin-shaped field effect transistor on the substrate further comprises:
and removing the oxide layer formed on the side wall of the side wall and the side wall of the channel layer.
10. The method according to any one of claims 7 to 9, wherein the selective oxidation method is characterized in that an oxidation atmosphere of the selective oxidation treatment is oxygen, nitrogen or an atmosphere containing ozone.
11. The method for manufacturing a fin-shaped semiconductor device according to any one of claims 7 to 9, wherein the selective oxidation treatment adopts a furnace tube oxidation mode, the temperature of the furnace tube oxidation mode is 500 ℃ to 850 ℃ and the time is 10min to 60min;
or, the selective oxidation treatment adopts rapid heat treatment, the temperature of the rapid heat treatment is 600-850 ℃, the rapid heat treatment comprises 1-10 treatment periods, and the treatment time of each treatment period is 30-60 s.
12. An electronic device comprising the fin-shaped semiconductor device according to any one of claims 1 to 6.
13. The electronic device of claim 12, comprising a communication device or a terminal device.
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| US9590038B1 (en) * | 2015-10-23 | 2017-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device having nanowire channel |
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