CN109326650B - Semiconductor device, method of manufacturing the same, and electronic apparatus including the same - Google Patents

Semiconductor device, method of manufacturing the same, and electronic apparatus including the same Download PDF

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CN109326650B
CN109326650B CN201811178260.2A CN201811178260A CN109326650B CN 109326650 B CN109326650 B CN 109326650B CN 201811178260 A CN201811178260 A CN 201811178260A CN 109326650 B CN109326650 B CN 109326650B
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source
semiconductor
doped
drain
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CN109326650A (en
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朱慧珑
吴振华
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US16/627,711 priority patent/US11404568B2/en
Priority to PCT/CN2018/118633 priority patent/WO2020073459A1/en
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    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

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Abstract

A semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are disclosed. According to an embodiment, a semiconductor device may include: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer stacked on the substrate in sequence and adjacent to each other, a gate stack being formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, and conduction band energy levels and/or valence band energy levels on both sides of the interface structure are different.

Description

Semiconductor device, method of manufacturing the same, and electronic apparatus including the same
Technical Field
The present application relates to the field of semiconductors, and in particular, to a vertical type semiconductor device, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.
Background
Horizontal type semiconductor devices, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), are widely used in various electronic devices. In the horizontal MOSFET, the source, gate, and drain of the transistor are arranged in a direction substantially parallel to the top surface of the substrate, but this arrangement pattern makes it difficult to further reduce the device area in the horizontal direction, which affects the integration of the electronic device and increases the difficulty in further reducing the manufacturing cost.
To solve the above problems, vertical type devices have been used. In the vertical MOSFET, the source, gate, and drain of the transistor are arranged in a direction substantially perpendicular to the top surface of the substrate, and thus the vertical device is more easily scaled down. But for vertical devices, on the one hand, if a polycrystalline channel material is used, the channel resistance will be greatly increased, making it difficult to stack multiple vertical devices, as this would result in too high a resistance. On the other hand, if a single-crystal channel material is used, there are problems that the gate length and the relative position of the gate and the source/drain are difficult to control. The structural design, material usage, and manufacturing accuracy of a semiconductor device directly affect its on and off current, thereby affecting its performance (e.g., power consumption of the semiconductor device).
Disclosure of Invention
In view of the above, an object of the present application is to provide a vertical type semiconductor device capable of controlling power consumption and a leakage current of the semiconductor device, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.
According to a first aspect of the present application, there is provided a semiconductor device comprising: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer stacked on a substrate in sequence and adjacent to each other, a gate stack being formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, and a conduction band energy level and/or a valence band energy level of both sides of the interface structure are different.
According to a second aspect of the present application, there is provided a method of manufacturing a semiconductor device, forming a first source/drain layer on a substrate; forming a channel layer on the first source/drain layer; forming a second source/drain layer on the channel layer; defining an active region of the semiconductor device in the first source/drain layer, the channel layer, and the second source/drain layer; and forming a gate stack around a periphery of the channel layer; wherein, the forming of the first source/drain layer and the forming of the second source/drain layer further comprise forming at least one interface structure in at least one of the first source/drain layer and the second source/drain layer, and the conduction band energy level and/or the valence band energy level on two sides of the interface structure are different.
According to a third aspect of the present application, there is provided an electronic apparatus including an integrated circuit formed of the above semiconductor device.
According to the embodiment of the application, at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer of the semiconductor device, so that the conduction band energy levels on two sides of the interface structure are different and/or the valence band energy levels are different, or the difference between the conduction band energy levels (or the valence band energy levels) of the semiconductor layers on two sides of the semiconductor interface is larger than or equal to the set threshold value, thereby effectively reducing the leakage current of the semiconductor device and improving the performance of the semiconductor device. Further, a gate stack formed by epitaxial growth is provided in a semiconductor device, the gate stack surrounding the periphery of the channel layer and embedded in a first recess on the channel layer, and at least a portion of a bottom surface or a top surface of the gate stack being substantially coplanar with a portion of a top surface of the first source/drain layer and a bottom surface of the second source/drain layer, respectively, in contact with the channel layer, thereby enabling good control of gate length and achieving self-alignment of the gate stack with the source/drain layers, optimizing switching performance of the device. In addition, since the second recess recessed inward is also formed on the outer peripheries of the first and second source/drain layers, when the gate stack is embedded in the first recess, it is simultaneously isolated from the first and second source/drain layers by the isolation dielectric filled in the second recess, thereby reducing or even avoiding overlap with the source/drain region, which helps to reduce parasitic capacitance between the gate and the source/drain.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings, in which:
fig. 1 to 3 show schematic structural views of a semiconductor device according to an embodiment of the present application;
fig. 4 to 12 show schematic views of a flow of manufacturing a semiconductor device according to an embodiment of the present application.
Throughout the drawings, the same or similar reference numerals denote the same or similar components.
Detailed Description
Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present application. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present application.
Various structural schematics according to embodiments of the present application are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of this application, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Fig. 1 illustrates a schematic structural view of a semiconductor device according to an embodiment of the present application, and as shown in fig. 1, a vertical type semiconductor device according to an embodiment of the present application may include a first source/drain layer 1011-1, a channel layer 1003, and a second source/drain layer 1011-2 stacked in sequence and adjacent to each other on a substrate 1001. Source/drain regions of the device may be formed in the first and second source/drain layers 1011-1 and 1011-2, and a channel region of the device may be formed in the channel layer 1003. A conductive path may be formed through the channel region between the source/drain regions at the respective ends of the channel region. The gate stack may be formed around the outer circumference of the channel layer 1003. Thus, the gate length may be determined by the thickness of the channel layer 1003 itself, rather than relying on a time-consuming etch as in the prior art. Further, the gate length can be controlled by controlling the thickness of the channel layer 1003. In the latter embodiment, it can be seen that in the present application, the channel layer 1003 may be formed by a growth process such as epitaxial growth, so that the thickness of the channel layer may be well controlled, and thus, the gate length of the formed device may be well controlled.
According to an embodiment of the present application, at least one interface structure is formed in at least one of the first source/drain layer 1011-1 and the second source/drain layer 1011-2, and a conduction band energy level and/or a valence band energy level are different at both sides of the interface structure. As shown in fig. 1, a schematic view of an interface structure formed in each of the first and second source/drain layers 1011-1 and 1011-2, respectively, and formed in a direction parallel to the top surface of the substrate 1001 is shown. In the first source/drain layer 1011-1, a first semiconductor layer 1031-1 'and a second semiconductor layer 1032-1' are included in a direction from bottom to top perpendicular to the top surface of the substrate 1001, and in the second source/drain layer 1011-2, a fourth semiconductor layer 1034-1 'and a third semiconductor layer 1033-1' are included in a direction from bottom to top perpendicular to the top surface of the substrate 1001. An interface structure is formed at an interface between the first semiconductor layer 1031-1 'and the second semiconductor layer 1032-1', and at an interface between the third semiconductor layer 1033-1 'and the fourth semiconductor layer 1034-1', and conduction band energy levels and/or valence band energy levels at both sides of the interface structure are different, that is, carriers at both sides of the interface structure have different potential energies, and such an energy band structure can reduce or avoid a large leakage current generated when a conventional MOSFET crosses a potential barrier due to thermionic emission, and improve device performance, such as improving a subthreshold swing and reducing power consumption.
Further, a schematic view of forming one (or more) interface structure only in the second source/drain layer 1011-2 is shown in fig. 2. As shown in fig. 2, an interface structure is formed only at an interface between the third semiconductor layer 1033-1 'and the fourth semiconductor layer 1034-1' in the second source/drain layer 1011-2, conduction band energy levels and/or valence band energy levels at both sides of the interface structure are different, and carriers at both sides of the interface structure have different potential energies, so that a built-in electric field is formed at both sides of the interface structure, which is advantageous for reducing off-current of the semiconductor device. In other embodiments, one or more interface structures may be formed only in the first source/drain layer 1011-1.
In a specific embodiment, for a conventional nMOSFET, the pn junction structure is npn, whereas the pn junction structure of the vertical transistor according to the present application is pnp (pn junction is present in only one source/drain layer) or pnp (pn junctions are present in both upper and lower source/drain layers). Preferably, for a vertical transistor of a pnp-n structure, the pn junction located in the source/drain region is p + n (i.e., a pn junction formed by p + doping and n doping); for a vertical transistor of pnp structure, the pn junctions located in the source/drain regions are the first and fourth pn junctions, which are p + n and np + junctions, respectively. The structure can reduce or avoid leakage current generated by hot electron emission of the traditional nMOSFET, and further reduce the power consumption of the device.
It should be noted that, in other embodiments of the present application, the first semiconductor layer 1031-1 'and the second semiconductor layer 1032-1' stacked alternately are not limited to one layer. That is, in the first source/drain layer 1011-1, at least one first semiconductor layer (e.g., 1031-1 ', 1031-2', 1031-3 '… …) and at least one second semiconductor layer (e.g., 1032-1', 1032-2 ', 1032-3' … …) may be alternately stacked. An interface structure is formed at an interface where each of the first semiconductor layers (e.g., 1031-1 ', 1031-2', 1031-3 '… …) and the second semiconductor layers (e.g., 1032-1', 1032-2 ', 1032-3' … …) are in corresponding contact, and the conduction band energy levels and/or the valence band energy levels are different at both sides of the interface structure.
For example, as shown in FIG. 3, four semiconductor layers are alternately stacked in a first source/drain layer 1011-1 and a second source/drain layer 1011-2, respectively. Taking the first source/drain layer 1011-1 as an example, the first semiconductor layer 1031-1 ', the second semiconductor layer 1032-1', the first semiconductor layer 1031-2 'and the second semiconductor layer 1032-2' are sequentially included in a direction from bottom to top perpendicular to the top surface of the substrate 1001. The first semiconductor layer and the second semiconductor layer are alternately stacked, and the above-described interface structure may be formed at an interface of the first semiconductor layer 1031-1 'and the second semiconductor layer 1032-1', and at an interface of the first semiconductor layer 1031-2 'and the second semiconductor layer 1032-2', that is, two interface structures are formed inside the first source/drain layer 1011-1. In this way, built-in electric fields can be formed at the two interface structures, respectively. Therefore, the leakage current of the device can be controlled by finely adjusting the built-in electric field, and the performance of the device is improved. In a specific embodiment, the stacked semiconductor layers may be formed by growing layers of Si, SiGe or III-V semiconductors, and the thickness of each semiconductor layer may be controlled within a range of 1nm to 20nm, which not only satisfies the performance requirements of the device, but also enables stacking of the device in the vertical direction. When each semiconductor layer is formed, the conduction band energy level or the valence band energy level of each semiconductor layer satisfies a certain relationship, so that electrons in conduction bands on two sides of the interface structure have different potential energies or holes in the valence bands have different potential energies.
Specifically, according to an embodiment of the present application, as shown in fig. 1, on both sides of the interface structure of the first semiconductor layer 1031-1 'and the second semiconductor layer 1032-1' in the first source/drain layer 1011-1 and the interface structure of the third semiconductor layer 1033-1 'and the fourth semiconductor layer 1034-1' in the second source/drain layer 1011-2, the conduction band or valence band energy level of the first semiconductor layer 1031-1 '(or the third semiconductor layer 1033-1') is different from the conduction band or valence band energy level of the second semiconductor layer 1032-1 '(or the fourth semiconductor layer 1034-1'), and the difference between the conduction band or valence band energy levels is greater than or equal to a set threshold, for example, greater than 0.1 eV. The band structure can reduce or avoid large leakage current generated by crossing a potential barrier due to thermal electron emission of a traditional MOSFET, and improve the performance of a device, such as improving the subthreshold swing and the like.
For example, in the first embodiment, the first semiconductor layer is AlxGa1-xN，0.1<x<0.5, the second semiconductor layer is GaN; and/or the third semiconductor layer is AlxGa1-xN，0.1<x<0.5, the fourth semiconductor layer is GaN. In a second embodiment, the first semiconductor layer is InxGa1-xAs，0.3<x<0.7 the second semiconductor layer is InyAl1-yAs，0.3<y<0.7; and/or the third semiconductor layer is InxGa1-xAs，0.3<x<0.7 the fourth semiconductor layer is InyAl1-yAs，0.3<y<0.7. In a third specific embodiment, the first semiconductor layer is InP and the second semiconductor layer is InzAl1-zAs，0.3<z<0.7; and/or the third semiconductor layer is InP and the fourth semiconductor layer is InzAl1-zAs，0.3<z<0.7. In a fourth specific embodiment, the first semiconductor layer is SiaGe1-aThe second semiconductor layer is SibGe1-bWherein a is not equal to b; and/or the third semiconductor layer is SiaGe1-aThe fourth semiconductor layer is SibGe1-bWhere a ≠ b.
Further, one or more interface structures may be formed only in the first source/drain layer 1011-1 or the second source/drain layer 1011-2, and in other embodiments of the present application, the alternately stacked first semiconductor layer 1031-1 ', second semiconductor layer 1032-1', or third semiconductor layer 1033-1 ', and fourth semiconductor layer 1034-1' are not limited to one layer, and the present embodiment may be implemented as long as the conduction band energy level or valence band energy level of the semiconductor layers satisfies a relationship such that the conduction band energy level and/or valence band energy level of both sides of the interface structure are different. Reference may be made to fig. 2 and fig. 3 and the description of the foregoing embodiments, which are not repeated herein.
According to another embodiment of the application, the interface structure may be a pn junction structure. Specifically, at least one pn junction structure is formed in at least one of the first source/drain layer 1011-1 and the second source/drain layer 1011-2. A different doping layer is formed in each of the first and second source/drain layers 1011-1 and 1011-2 by differently doping the respective semiconductor layers, and a pn junction structure is formed at an interface of the different doping layers. The first source/drain layer 1011-1 and the second source/drain layer 1011-2 may be formed by epitaxial growth or a Molecular Beam Epitaxy (MBE) process. Wherein, the epitaxial growth process is preferably a low-temperature epitaxial growth process.
Referring again to fig. 1, a pn junction structure formed in a direction parallel to the top surface of the substrate 1001 is formed on an interface where the first doped layer 1031-1 and the second doped layer 1032-1 are in contact and on an interface where the third doped layer 1033-1 and the fourth doped layer 1034-1 are in contact, respectively.
According to an embodiment of the present application, the first and second doped layers 1031-1 and 1032-1 are oppositely doped. For example, for an n-type MOSFET device, the first doped layer 1031-1 is a positive polarity doped layer (negative polarity doped layer for a p-type MOSFET device) and the second doped layer 1032-1 is a negative polarity doped layer (positive polarity doped layer for a p-type MOSFET device). Further, the first doped layer 1031-1 may be a p + doped layer (n + doped layer for a p-type MOSFET device) and the second doped layer 1032-1 may be an n doped layer (p doped layer for a p-type MOSFET device). The first and second doped layers 1031-1 and 1032-1 may be in-situ doped layers formed by an in-situ doping process. In other specific embodiments, the doped layer may also be formed by an ion implantation process or a vapor phase drive-in diffusion process. Similarly, for an n-type MOSFET device, the doped layer in the second source/drain layer 1011-2 is formed symmetrically with the doped layer in the first source/drain layer 1011-1 with respect to the channel layer 1003.
According to an embodiment of the present application, third doped layer 1033-1 and fourth doped layer 1034-1 are oppositely doped. For example, for an n-type MOSFET device, third doped layer 1033-1 is a positive polarity doped layer (negative polarity doped layer for a p-type MOSFET device) and fourth doped layer 1034-1 is a negative polarity doped layer (positive polarity doped layer for a p-type MOSFET device). Further, third doped layer 1033-1 can be a p + doped layer (n + doped layer for a p-type MOSFET device) and fourth doped layer 1034-1 can be an n doped layer (p doped layer for a p-type MOSFET device). Third doped layer 1033-1 and fourth doped layer 1034-1 may be in-situ doped layers formed by an in-situ doping process. In other specific embodiments, the doped layer may also be formed by an ion implantation process or a vapor phase drive-in diffusion process.
It should be noted that the MOSFET having the mirror-image first source/drain layer 1011-1 and the mirror-image second source/drain layer 1011-2 is a symmetric semiconductor device, but in other embodiments of the present application, an asymmetric semiconductor device may be formed by doping each first doping layer and each second doping layer stacked at different positions in the first source/drain layer with different semiconductor materials. For example, when the first source/drain layer 1011-1 includes two first doping layers and two second doping layers, the two first doping layers may be doped with different materials, respectively, and the two second doping layers may be doped with different materials, respectively. The embodiments of the present application can be implemented as long as the requirements of forming a pn junction structure between adjacent first and second doped layers can be satisfied, and the present application is not limited thereto.
According to the semiconductor device of the embodiment of the present application, since the pn junction structures are formed in the first source/drain layer 1011-1 and the second source/drain layer 1011-2, respectively, the additional pn junction structure can adjust the electric field inside the semiconductor device when an operating voltage is applied to the semiconductor device, thereby improving the performance of the semiconductor device. The electric field formed inside can reduce the leakage current of the device, reduce the influence of the sub-threshold swing amplitude on the device and increase the ratio of the on current to the off current of the semiconductor device.
In addition, it should be further noted that, in other embodiments of the present application, the first doped layer 1031-1 and the second doped layer 1032-1 stacked alternately are not limited to one layer. The interleaved stack of third and fourth doped layers 1033-1 and 1034-1 is not limited to one layer. For example, in the first source/drain layer 1011-1, at least one first doped layer (e.g., 1031-1, 1031-2, 1031-3 … …) and at least one second doped layer (e.g., 1032-1, 1032-2, 1032-3 … …) may be alternately stacked. A plurality of pn junction structures are respectively formed on the interfaces of the corresponding contacts of each of the first doped layers (e.g., 1031-1, 1031-2, 1031-3 … …) and the second doped layers (e.g., 1032-1, 1032-2, 1032-3 … …).
According to an embodiment of the present application, an active region of a device may be defined in the stacked first source/drain layer 1011-1, channel layer 1003, and second source/drain layer 1011-2. For example, they may be selectively etched into a desired shape in turn. In general, the active region may be cylindrical, and its cross-section may be circular or rectangular. The radius of the circle may preferably be 5nm to 100nm in the case of a circle in its cross section, and may be 3nm to 100nm in width (in a direction perpendicular to the paper surface) and 3nm to 10 μm in length (in a direction parallel to the top surface of the substrate 1001) in the case of a rectangle in its cross section. Such a structure not only provides sufficient device current, but also allows for better control of short channel effects.
As can also be seen from fig. 1, only the upper portion of the first source/drain layer 1011-1 is etched, and the lower portion of the first source/drain layer 1011-1 may extend beyond the outer periphery of the upper portion thereof, which may facilitate connection of source/drain regions formed in the first source/drain layer in a subsequent process. Then, a gate stack may be formed around the outer circumference of the channel layer 1003. The gate stack includes a gate dielectric layer 1015, Vt tuning metal (also typically a metal layer sandwiched between the gate dielectric layer and the gate conductor layer), and a gate conductor layer 1017. The outer circumference of the channel layer 1003 may be recessed inward with respect to the outer circumference of the pillar-shaped active region, forming a first recess. In this way, the formed gate stack can be embedded in the first recess, and self-alignment can be performed by using the first recess during the formation of the gate stack, thereby ensuring the processing accuracy to a certain extent.
Further, at least a portion of the bottom surface of the gate stack is formed substantially coplanar with at least a portion of the top surface of a second doped layer (in fig. 1, the doped layer is 1032-1, in fig. 3, the doped layer is 1032-2) or a second semiconductor layer (in fig. 1, the semiconductor layer is 1032-1 ', in fig. 3, the semiconductor layer is 1032-2') in contact with the channel layer 1003, and/or at least a portion of a top surface of the gate stack and at least a portion of a bottom surface of a fourth doped layer (in fig. 1, the doped layer is 1034-1, in fig. 3, the doped layer is 1034-2) or a fourth semiconductor layer (in fig. 1, the semiconductor layer is 1034-1 ', and in fig. 3, the semiconductor layer is 1034-2') in contact with the channel layer 1003 are substantially coplanar. The structure can increase the on-state current of the device, improve the short channel effect of the device and reduce the process fluctuation in the device manufacturing.
According to an embodiment of the present application, the first source/drain layer 1011-1 and the second source/drain layer 1011-2 are recessed inwardly with respect to the outer circumference of the pillar-shaped active region, forming a second recess. The second recess is filled with an isolation medium. The isolation dielectric may, for example, comprise SiN, Si3N4、SiO2And SiCO and the like. As can be seen in fig. 1, the filled isolation dielectric is located at the portion of the gate stack embedded in the first recess, thereby being able to isolate the overlap between the gate stack and the first and second source/drain layers 1011-1 and 1011-2, helping to reduce the parasitic capacitance between the gate and the source/drain to improve device performance.
According to an embodiment of the present application, the channel layer 1003 may be composed of a single crystalline semiconductor material, and the channel layer 1003 may include a semiconductor material different from the first and second source/drain layers 1011-1 and 1011-2. Specifically, the semiconductor material of the channel layer 1003 is different from the semiconductor material of at least one second doped layer or the semiconductor material of at least one second semiconductor layer, and/or the semiconductor material of the channel layer 1003 is different from the semiconductor material of at least one fourth doped layer or the semiconductor material of at least one fourth semiconductor layer. In this way, it is advantageous to perform a process, such as selective etching, on the channel layer 1003 to form the first recess and the second recess, respectively. The channel layer 1003 may be formed by an epitaxial growth process or a Molecular Beam Epitaxy (MBE) process. Wherein, the epitaxial growth process is preferably a low-temperature epitaxial growth process.
As can also be seen in fig. 1, the semiconductor device further includes vias respectively exposing the gate stack, the first source/drain layer 1011-1 and the second source/drain layer 1011-2, in which a contact 1023-3 for connecting the gate stack, a contact 1023-1 for connecting the first source/drain layer 1011-1 and a contact 1023-2 for connecting the second source/drain layer 1011-2 are respectively formed. In addition, on the top surface of the lower region of the first source/drain layer 1011-1 beyond the outer circumference of the upper portion thereof, an isolation layer 1013 is also formed. The top surface of the isolation layer 1013 is near the top surface of the first source/drain layer 1011-1 inside the pillar-shaped active region or between the top surface and the bottom surface of the channel layer 1003, and the isolation layer 1013 may implement self-alignment of the gate stack during the process together with the first recess, which will be described in detail later. An interlayer dielectric layer 1021 is also formed on top of the MOSFET structure for device isolation and protection.
The present application may be presented in a variety of forms, some examples of which are described below.
Fig. 4 to 12 show a flow chart of manufacturing a semiconductor device according to an embodiment of the present application, in which an n-type MOSFET device that is symmetrical and forms one pn junction structure in a first source/drain layer and a second source/drain layer, respectively, is taken as an example for explanation.
As shown in fig. 4, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, a bulk Si substrate is described as an example for convenience of explanation.
On the substrate 1001, a first source/drain layer 1011-1, a channel layer 1003, and a second source/drain layer 1011-2 may be sequentially formed. In thatIn a specific embodiment, the above layers may be sequentially formed by epitaxial growth. Includes, first, forming a first source/drain layer 1011-1 on a substrate 1001. Taking the first source/drain layer 1011-1 including the first doped layer 1031-1 and the second doped layer 1032-1 as an example, it is required that the first doped layer 1031-1 and the second doped layer 1032-1 stacked alternately are sequentially formed on the substrate 1001 by epitaxial growth. The first doped layer 1031-1 may be an in-situ doped Si layer. For example, for an n-type MOSFET device, the preferred dopant material is B with a dopant concentration of about 1E19cm-3～1E21cm-3The thickness of the first doped layer 1031-1 is about 10nm to about 100 nm. The second doped layer 1032-1 may be an in-situ doped Si layer. For example, for an n-type MOSFET device, the preferred dopant material is P or As with a dopant concentration of about 1E18cm-3～1E21cm-3The thickness of the second doped layer 1032-1 is approximately 1nm-15 nm. Then, a channel layer 1003 is epitaxially grown on the first source/drain layer 1011-1 (i.e., on the second doped layer 1032-1), and the channel layer 1003 may be a SiGe layer having a thickness of about 10nm to 100nm, which is used to define the gate length. A second source/drain layer 1011-2 is next formed on the channel layer 1003. Taking the second source/drain layer 1011-2 comprising the third doped layer 1033-1 and the fourth doped layer 1034-1 as an example, the fourth doped layer 1034-1 and the third doped layer 1033-1 stacked alternately are sequentially formed on the channel layer 1003 by epitaxial growth. The third doped layer 1033-1 may be an in-situ doped Si layer. For example, for an n-type MOSFET device, the preferred dopant material is B with a dopant concentration of about 1E19cm-3～1E21cm-3The thickness of the third doped layer 1033-1 is about 10nm to about 100 nm. The fourth doped layer 1034-1 may also be an in-situ doped Si layer. For example, for an n-type MOSFET device, the preferred dopant material is P or As with a dopant concentration of about 1E18cm-3～1E21cm-3The thickness of the fourth doped layer 1034-1 is about 1nm to about 15 nm. The present invention is not limited to this, and the kind of the doping material, the doping concentration, and the thickness of the doping layer may be changed.
In the embodiments of the present application, it is preferably formed using an epitaxial growth process or a molecular beam epitaxy process. The epitaxial growth process preferably adopts a low-temperature epitaxial growth process, and the process temperature is less than 800 ℃, so that the diffusion of large dopants can be avoided. The stacked semiconductor layers are formed by an epitaxial growth process, and the thickness of the semiconductor layers can be well controlled. And since the gate length of the semiconductor device is determined by the thickness of the channel layer 1003, the gate length can be more accurately controlled.
In embodiments of the present application, in addition to the in-situ doping method for forming the doped layer, other doping processes, such as an ion implantation process or a gas phase drive-in diffusion process, may be used. When the doped layers are formed, a semiconductor material layer (e.g., Si in the first doped layer 1031-1, the second doped layer 1032-1, the third doped layer 1033-1, and the fourth doped layer 1034-1) is formed by deposition, and then the in-situ doping, the ion implantation process, or the vapor phase drive-in diffusion process is applied to dope other materials.
The channel layer 1003 may be formed by an epitaxial growth process over the first source/drain layer 1011-1 (i.e., the second doped layer 1032-1). In the embodiment of the present application, the channel layer 1003 may use a single crystal semiconductor material, which is advantageous for reducing the resistance of the device. And the single crystal semiconductor material of the channel layer 1003 may have the same crystal structure as the semiconductor material of the first and second source/drain layers 1011-1 and 1011-2. For example, in a particular embodiment, the channel layer 1003 may be in-situ doped SiGe.
It should be noted that, in order to ensure the subsequent processes (for example, forming the first recess and the second recess), the materials between the channel layer 1003, the first source/drain layer 1011-1, the second source/drain layer 1011-2, and the substrate 1001 should be ensured to have etching selectivity. Additionally, in some other embodiments, an oxide is also deposited on third doped layer 1033-1 to form hard mask 1041, and hard mask 1041 may be used to define the shape of first source/drain layer 1011-1 and second source/drain layer 1011-2 isolation when forming/etching first source/drain layer 1011-1 and second source/drain layer 1011-2 isolation.
Next, the active region of the device may be defined. Specifically, as shown in fig. 5a and 5b (where fig. 5a is a cross-sectional view, fig. 5b is a top view, and line AA' shows a position where the cross-section is taken out), a photoresist (not shown) may be formed on the stack of the substrate 1001, the channel layer 1003, the first source/drain layer 1011-1 (including the first and second doped layers 1031-1 and 1032-1), the second source/drain layer 1011-2 (including the third and fourth doped layers 1033-1 and 1034-1), and the hard mask 1041 shown in fig. 4, the photoresist is patterned into a desired shape by photolithography (exposure and development), and the hard mask 1041, the third doping layer 1033-1, the fourth doping layer 1034-1, the channel layer 1003, the second doping layer 1032-1, and the first doping layer 1031-1 are selectively etched (e.g., Reactive Ion Etching (RIE)) in this order using the patterned photoresist as a mask. The etch proceeds into the first doped layer 1031-1 but not at the bottom surface of the first doped layer 1031-1, i.e., not to the top surface of the substrate 1001. The etched upper portions of the hard mask 1041, the third doped layer 1033-1, the fourth doped layer 1034-1, the channel layer 1003, the second doped layer 1032-1 and the first doped layer 1031-1 form a column shape. The RIE may, for example, be performed in a direction generally perpendicular to the substrate surface such that the pillar is also generally perpendicular to the substrate surface. Thereafter, the photoresist may be removed.
As can be seen from the top view of fig. 5b, in this embodiment the cross-section of the active region is substantially circular in shape, i.e. the outer periphery of the active region is substantially cylindrical, the radius of the circular cross-section may preferably be between 10nm and 100 nm. In other embodiments, when the cross-section of the active region is rectangular, it may be preferable that the length of the rectangle (in fig. 5a, in a direction parallel to the top surface of the substrate 1001) is 10nm to 10 μm in order to provide sufficient device current, and the width of the rectangle is 10nm to 100nm (in fig. 5a, in a direction perpendicular to the paper) in order to better control short channel effects. Of course, the shape of the active region is not limited thereto, but may be formed in other shapes according to the design layout. For example, the cross-section of the active region may be elliptical, square, etc.
Then, as shown in fig. 6, a first recess is formed in the channel layer 1003, that is, the outer periphery of the channel layer 1003 is recessed with respect to the outer periphery of the pillar-shaped active region (or the outer periphery of the hard mask 1041) which has been formed (in this example, recessed in a lateral direction substantially parallel to the substrate surface). This may be accomplished, for example, by further selectively etching channel layer 1003 relative to substrate 1001, first source/drain layer 1011-1, second source/drain layer 1011-2, and hard mask 1041.
In a specific embodiment, a modifier-based selective etching method is used. Specifically, the laminate structure formed in the foregoing process is first put into its entirety in a surface modifier, which may include ozone (O)3) Potassium permanganate (KMnO)4) Potassium dichromate (K)2Cr2O7) Nitric acid (HNO)3) Sulfuric acid (H)2SO4) Hydrogen peroxide (H)2O2) One or a combination of several of them, an oxygen-containing gas or an oxygen-containing plasma. A modified layer in the form of an oxide (e.g., SiGeO formed on a SiGe surface) is formed on the surface of the substrate 1001, the channel layer 1003, the first source/drain layer 1011-1 (including the first doped layer 1031-1 and the second doped layer 1032-1), the second source/drain layer 1011-2 (including the third doped layer 1033-1 and the fourth doped layer 1034-1), and the hard mask 1041 by a reaction between the modifier and the semiconductor material. Generally, the surface of the semiconductor on which the modified layer is formed is also cleaned after the modified layer is formed. Then, the modifying layer is removed by using an etchant and the surface of the semiconductor after the modifying layer is removed is cleaned. The etchant used may include hydrofluoric acid, buffered hydrofluoric acid, BOE, hydrofluoric acid vapor, halogen hydride, or vapor thereof. The cleaning agent used may include water, high purity deionized water, ethanol, acetone, etc. And then checking whether the etching depth reaches a preset depth, and if the etching depth does not reach the preset depth, repeating the process steps of forming the modified layer by using the modifier and etching the modified layer until the etching requirement is met. The method can accurately control the etching thickness (less than or equal to 0.5nm) in semiconductor processing, and can improve the etching rate.
Next, as shown in fig. 7, a material layer, referred to as a sacrificial layer 1007 (also referred to as a sacrificial gate), is filled in the first recess. This sacrificial layer is used primarily to avoid subsequent processing affecting the channel layer 1003 or leaving unnecessary material in the first recess that could affect the formation of subsequent gate stacks. In a specific embodiment, the first recess may be filled with nitride, which is formed by depositing nitride on the structure shown in fig. 6, and then etching back the deposited nitride, such as RIE, in a direction substantially perpendicular to the direction of the top surface of the substrate 1001. The filled nitride mainly occupies a space of a gate stack to be formed in a subsequent process, and an outer circumferential surface of the sacrificial layer 1007 is substantially coplanar with an outer circumferential surface of the pillar-shaped active region.
Next, second recesses are formed at an upper portion of the first source/drain layer 1011-1 (i.e., a portion of the first source/drain layer 1011-1 included in the pillar-shaped active region) and the second source/drain layer 1011-2. That is, the upper portion of the first source/drain layer 1011-1 and the outer periphery of the second source/drain layer 1011-2 are recessed (in this example, recessed in a lateral direction substantially parallel to the substrate surface) with respect to the outer periphery of the pillar-shaped active region that has been formed (or the outer periphery of the hard mask 1041, or the outer periphery of the sacrificial layer 1007 that has been formed). This may be accomplished, for example, by further selectively etching the upper portion of the first source/drain layer 1011-1 and the second source/drain layer 1011-2 relative to the substrate 1001, sacrificial layer 1007, and hard mask 1041.
In a specific embodiment, a modifier-based selective etch process is still employed. The implementation steps can be performed by referring to the process steps adopted for forming the first recess, and are not described herein again. After the second recess is formed, an isolation dielectric is filled in the second recess. In a specific embodiment, the isolation dielectric may be SiN, Si3N4、SiO2And SiCO and the like. Due to the presence of the isolation dielectric, when the gate stack is embedded in the first recess, the first source/drain layer and the second source/drain layer can be simultaneously isolated by the isolation dielectric filled in the second recess, and thus overlap with the source/drain region can be reduced or even avoided, which helps to reduce parasitic capacitance between the gate and the source/drain. The outer peripheral surface of the isolation medium after being filled with the isolation medium is substantially coplanar with the outer peripheral surface of the sacrificial layer 1007, as shown in fig. 8.
Next, an isolation layer may be formed around the active region to achieve electrical isolation. For example, as shown in fig. 9, an oxide may be deposited on the top surface of the portion of the first source/drain layer 1011-1 beyond the pillar-shaped active region and etched back to form an isolation layer 1013. The deposited oxide may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP) or sputtering prior to etch back. In an embodiment of the present application, the top surface of the spacer layer 1013 (note that the hard mask 1041 is etched away together when etching back the oxidation) may be formed near the top surface of the upper portion of the first source/drain layer 1011-1 or between the top surface and the bottom surface of the channel layer 1003.
The sacrificial layer 1007 may be left when forming the isolation layer to avoid that the material of the isolation layer enters the first recess in which the gate stack is to be accommodated. Thereafter, the sacrificial layer 1007 may be removed to release the space in the first recess. For example, the sacrificial layer 1007 (nitride) may be selectively etched with respect to the spacer layer 1013 (oxide) and the first source/drain layer 1011-1 (in-situ doped Si), the isolation dielectric (oxide or nitride of Si) and the channel layer 1003 (SiGe).
Then, as shown in fig. 10, a gate stack may be formed in the first recess. Specifically, a gate dielectric layer 1015 and a gate conductor layer 1017 may be sequentially deposited on the structure shown in fig. 9 (with the sacrificial layer 1007 removed), and the gate dielectric layer 1015 may include, for example, an interfacial layer and a high-K gate dielectric such as SiO2And HfO2The gate conductor layer 1017 may, for example, comprise a metal gate conductor. In addition, a work function adjusting layer may be further formed between the gate dielectric layer 1015 and the gate conductor layer 1017.
The deposited gate conductor layer 1017 (and optionally the gate dielectric layer 1015) is then etched back such that at least a portion of the bottom surface of the gate stack (e.g., the bottom surface of the portion outside the first recess) and at least a portion of the top surface of the first source/drain layer 1011-1 in contact with the channel layer 1003 are substantially coplanar. Referring to fig. 10, the bottom surface of the gate dielectric 1015 of the gate stack outside the first recess and the top surface of the second doped layer 1032-1 of the first source/drain layer 1011-1 are substantially coplanar. And/or such that at least a portion of the top surface of the gate stack (e.g., the top surface of the portion outside the first recess) and at least a portion of the bottom surface of the second source/drain layer 1011-2 in contact with the channel layer 1003 are substantially coplanar. Referring to fig. 10, the top surface of the gate conductor layer 1017 of the gate stack outside the first recess and the bottom surface of the fourth doped layer 1034-1 of the second source/drain layer 1011-2 are substantially coplanar.
In this way, the gate stack may be embedded in the first recess, overlapping the entire height of the channel layer 1003. At the position opposite to the gate stack embedded in the first recess, the isolation medium filled in the second recess is adopted, so that the overlapping between the gate stack and the source and drain regions can be avoided, and the parasitic capacitance between the gate and the source/drain regions can be reduced. In addition, since self-alignment is achieved by the first recess in forming the gate stack, the processing accuracy may be improved.
Next, the shape of the gate stack may be adjusted to facilitate subsequent interconnect fabrication. For example, as shown in fig. 11, a photoresist 1019 may be formed on the structure shown in fig. 10. The photoresist 1019 is patterned, for example by photolithography, to cover a portion of the gate stack exposed outside the first recess (in this example, the left half of the figure) and to expose another portion of the gate stack exposed outside the first recess (in this example, the right half of the figure).
Then, the gate conductor layer 1017 may be selectively etched, such as RIE, using the photoresist 1019 as a mask. Thus, the portion of the gate conductor layer 1017 blocked by the photoresist 1019 is retained except for the portion remaining within the first recess. Electrical connection to the gate stack may then be made through this portion. After that, the photoresist 1019 is removed as shown in fig. 12.
Next, referring back to fig. 1, an interlayer dielectric layer 1021 may be formed on the structure shown in fig. 12. For example, an oxide may be deposited and planarized such as CMP to form the interlayer dielectric layer 1021. In the interlayer dielectric layer 1021, contacts 1023-1 and 1023-2 to the first source/drain layer 1011-1 (i.e., source/drain region) and the second source/drain layer 1011-2 (i.e., source/drain region) regions, respectively, and a contact 1023-3 to the gate conductor layer 1017 may be formed. These contacts may be formed by etching vias in the interlayer dielectric layer 1021 and the isolation layer 1013 and filling them with a conductive material such as a metal.
Since the gate conductor layer 1017 extends beyond the outer periphery of the active region, its contact 1023-3 can be easily formed. In addition, since the lower portion of the first source/drain layer 1011-1 extends beyond the outer circumference of the pillar-shaped active region, that is, the gate conductor layer does not exist at least over a portion of the first source/drain layer 1011-1, its contact portion 1023-1 can be easily formed.
The semiconductor device according to the embodiment of the present application can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (e.g., other forms of transistors, etc.), an Integrated Circuit (IC) can be formed, and an electronic apparatus can be constructed therefrom. Accordingly, the present application also provides an electronic device including the above semiconductor device. The electronic device may also include components such as a display screen that cooperates with the integrated circuit and a wireless transceiver that cooperates with the integrated circuit. Such electronic devices are for example smart phones, computers, tablets (PCs), wearable smart devices, mobile power supplies etc.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present application are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present application. The scope of the application is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present application, and such alternatives and modifications are intended to be within the scope of the present application.

Claims (44)

1. A semiconductor device, comprising:
a substrate;
a first source/drain layer, a channel layer, and a second source/drain layer stacked on a substrate in sequence and adjacent to each other, a gate stack being formed around an outer circumference of the channel layer;
wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, and conduction band energy levels and/or valence band energy levels on both sides of the interface structure are different;
wherein the at least one interface structure is formed in a direction parallel to the top surface of the substrate;
wherein the first source/drain layer includes at least one first semiconductor layer and at least one second semiconductor layer alternately stacked in a direction from bottom to top perpendicular to a top surface of the substrate, the interface structure being formed between the first semiconductor layer and the second semiconductor layer;
wherein a conduction band energy level or a valence band energy level of the first semiconductor layer is different from a conduction band energy level or a valence band energy level of the second semiconductor layer and a difference between the conduction band energy level or the valence band energy level is greater than or equal to a set threshold;
wherein the at least one interface structure is a pn junction.
2. The semiconductor device of claim 1, wherein the second source/drain layer comprises at least one fourth semiconductor layer and at least one third semiconductor layer alternately stacked in a bottom-up direction perpendicular to the top surface of the substrate, the interface structure being formed between the fourth semiconductor layer and the third semiconductor layer.
3. The semiconductor device of claim 2,
the conduction band energy level or the valence band energy level of the third semiconductor layer is different from the conduction band energy level or the valence band energy level of the fourth semiconductor layer, and the difference between the conduction band energy level and the valence band energy level is greater than or equal to a set threshold value.
4. The semiconductor device of any one of claims 1-3,
the first semiconductor layer is AlxGa1-xN、InxGa1-xAs, InP or SiaGe1-aX is more than 0.1 and less than 0.7, and the second semiconductor layer is GaN or InyAl1-yAs、InyAl1-yAs or SibGe1-bY is more than 0.3 and less than 0.7, wherein a is not equal to b; and/or
The third semiconductor layer is AlxGa1-xN、InxGa1-xAs, InP or SiaGe1-aX is more than 0.1 and less than 0.7, and the fourth semiconductor layer is GaN or InyAl1-yAs、InyAl1-yAs or SibGe1-bY is more than 0.3 and less than 0.7, wherein a is not equal to b.
5. The semiconductor device of claim 1, wherein the first source/drain layer comprises at least one first doped layer and at least one second doped layer alternately stacked in a bottom-up direction perpendicular to the top surface of the substrate, the pn junction being formed between the first doped layer and the second doped layer.
6. The semiconductor device of claim 5, wherein the second source/drain layer comprises at least one fourth doped layer and at least one third doped layer alternately stacked in a bottom-up direction perpendicular to the top surface of the substrate, the pn junction being formed between the fourth doped layer and the third doped layer.
7. The semiconductor device of claim 1, wherein the second source/drain layer comprises at least one fourth doped layer and at least one third doped layer alternately stacked in a bottom-up direction perpendicular to the top surface of the substrate, the pn junction being formed between the fourth doped layer and the third doped layer.
8. The semiconductor device according to any of claims 1-3, 5-7, wherein the semiconductor material of the channel layer is different from the semiconductor material of at least one second doped layer or at least one second semiconductor layer, and/or the semiconductor material of the channel layer is different from the semiconductor material of at least one fourth doped layer or at least one fourth semiconductor layer.
9. The semiconductor device of claim 4, wherein the semiconductor material of the channel layer is different from the semiconductor material of the at least one second doped layer or the at least one second semiconductor layer, and/or the semiconductor material of the channel layer is different from the semiconductor material of the at least one fourth doped layer or the at least one fourth semiconductor layer.
10. The semiconductor device of claim 8,
at least a portion of a bottom surface of the gate stack and at least a portion of a top surface of a second doped layer or a second semiconductor layer in contact with the channel layer are substantially coplanar; and/or
At least a portion of a top surface of the gate stack and at least a portion of a bottom surface of a fourth doped layer or a fourth semiconductor layer in contact with the channel layer are substantially coplanar.
11. The semiconductor device of claim 9,
at least a portion of a bottom surface of the gate stack and at least a portion of a top surface of a second doped layer or a second semiconductor layer in contact with the channel layer are substantially coplanar; and/or
At least a portion of a top surface of the gate stack and at least a portion of a bottom surface of a fourth doped layer or a fourth semiconductor layer in contact with the channel layer are substantially coplanar.
12. The semiconductor device according to any one of claims 5 to 7 and 9 to 11, wherein the first doped layer and/or the third doped layer is a positive polarity doped layer or a negative polarity doped layer, and the second doped layer and/or the fourth doped layer is a negative polarity doped layer or a positive polarity doped layer.
13. The semiconductor device according to claim 8, wherein the first doped layer and/or the third doped layer is a positive polarity doped layer or a negative polarity doped layer, and the second doped layer and/or the fourth doped layer is a negative polarity doped layer or a positive polarity doped layer.
14. The semiconductor device of claim 12,
the first doped layer is a p + doped layer or an n + doped layer, and the second doped layer is an n doped layer or a p doped layer; and/or
The third doped layer is a p + doped layer or an n + doped layer, and the fourth doped layer is an n doped layer or a p doped layer.
15. The semiconductor device of claim 13,
the first doped layer is a p + doped layer or an n + doped layer, and the second doped layer is an n doped layer or a p doped layer; and/or
The third doped layer is a p + doped layer or an n + doped layer, and the fourth doped layer is an n doped layer or a p doped layer.
16. The semiconductor device of any one of claims 5-7, 9-11, 13-15,
the first doping layer and the second doping layer are both in-situ doped semiconductor layers; and/or
The third doped layer and the fourth doped layer are both in-situ doped semiconductor layers.
17. The semiconductor device of claim 8,
the first doping layer and the second doping layer are both in-situ doped semiconductor layers; and/or
The third doped layer and the fourth doped layer are both in-situ doped semiconductor layers.
18. The semiconductor device of claim 12,
the first doping layer and the second doping layer are both in-situ doped semiconductor layers; and/or
The third doped layer and the fourth doped layer are both in-situ doped semiconductor layers.
19. The semiconductor device of claim 1, wherein the channel layer comprises a channel layer single crystal semiconductor material.
20. The semiconductor device of claim 19, wherein the channel layer single crystal semiconductor material has the same crystal structure as the semiconductor material of the first and second source/drain layers.
21. The semiconductor device of claim 20 wherein the channel layer is SiGe or in-situ doped SiGe.
22. The semiconductor device of claim 1, wherein the first source/drain layer, the channel layer, and the second source/drain layer are formed by an epitaxial growth process.
23. The semiconductor device of claim 1, wherein the doping of the first source/drain layer, the channel layer, and the second source/drain layer is formed by in-situ doping, an ion implantation process, or a gas phase drive-in diffusion process.
24. A method of manufacturing a semiconductor device, comprising:
forming a first source/drain layer on a substrate;
forming a channel layer on the first source/drain layer;
forming a second source/drain layer on the channel layer;
defining an active region of the semiconductor device in the first source/drain layer, the channel layer, and the second source/drain layer; and
forming a gate stack around a periphery of the channel layer;
wherein, in the process of forming the first source/drain layer and the second source/drain layer, at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, and the conduction band energy level and/or the valence band energy level of two sides of the interface structure are different;
wherein forming a first source/drain layer on a substrate comprises:
growing and sequentially forming at least one first semiconductor layer and at least one second semiconductor layer which are overlapped in a staggered mode on the substrate;
wherein the interface structure is formed between the first semiconductor layer and the second semiconductor layer, a conduction band energy level or a valence band energy level of the first semiconductor layer is different from a conduction band energy level or a valence band energy level of the second semiconductor layer, and a difference between the conduction band energy level or the valence band energy level is greater than or equal to a set threshold value;
wherein the interface structure is a pn junction.
25. The method of claim 24, wherein forming a second source/drain layer on the channel layer comprises:
growing and sequentially forming at least one fourth semiconductor layer and at least one third semiconductor layer which are overlapped in a staggered manner on the channel layer;
wherein the interface structure is formed between the third semiconductor layer and the fourth semiconductor layer, a conduction band energy level or a valence band energy level of the third semiconductor layer is different from a conduction band energy level or a valence band energy level of the fourth semiconductor layer, and a difference between the conduction band energy level or the valence band energy level is greater than or equal to a set threshold value.
26. The method of claim 24 or 25, wherein each semiconductor layer is formed using epitaxial growth.
27. The method of claim 24, wherein forming a first source/drain layer on a substrate comprises:
sequentially forming at least one first doping layer and at least one second doping layer which are overlapped in a staggered mode on the substrate through epitaxial growth;
the interface structure is formed between the first doping layer and the second doping layer, the first doping layer is a positive polarity doping layer or a negative polarity doping layer, and the second doping layer is a negative polarity doping layer or a positive polarity doping layer.
28. The method of claim 27, wherein forming a second source/drain layer on the channel layer comprises:
sequentially forming at least one fourth doping layer and at least one third doping layer which are overlapped in a staggered mode on the channel layer by utilizing epitaxial growth;
the interface structure is formed between the third doping layer and the fourth doping layer, the third doping layer is a positive polarity doping layer or a negative polarity doping layer, and the fourth doping layer is a negative polarity doping layer or a positive polarity doping layer.
29. The method of claim 24, wherein forming a second source/drain layer on the channel layer comprises:
sequentially forming at least one fourth doping layer and at least one third doping layer which are overlapped in a staggered mode on the channel layer by utilizing epitaxial growth;
the interface structure is formed between the third doping layer and the fourth doping layer, the third doping layer is a positive polarity doping layer or a negative polarity doping layer, and the fourth doping layer is a negative polarity doping layer or a positive polarity doping layer.
30. The method of any one of claims 27-29,
carrying out in-situ doping on each first doping layer and each second doping layer superposed at different positions in the first source/drain layer by using the same or different semiconductor materials; and/or
And carrying out in-situ doping on each third doping layer and each fourth doping layer superposed at different positions in the second source/drain layer by using the same or different semiconductor materials.
31. The method of any of claims 24, 25, 27-29, wherein defining an active region of the semiconductor device comprises:
and sequentially etching the second source/drain layer, the channel layer and the upper part of the first source/drain layer to form a columnar active region, and enabling the lower part of the first source/drain layer to extend beyond the periphery of the columnar active region.
32. The method of claim 26, wherein defining an active region of the semiconductor device comprises:
and sequentially etching the second source/drain layer, the channel layer and the upper part of the first source/drain layer to form a columnar active region, and enabling the lower part of the first source/drain layer to extend beyond the periphery of the columnar active region.
33. The method of claim 30, wherein defining an active region of the semiconductor device comprises:
and sequentially etching the second source/drain layer, the channel layer and the upper part of the first source/drain layer to form a columnar active region, and enabling the lower part of the first source/drain layer to extend beyond the periphery of the columnar active region.
34. The method of claim 31, wherein defining an active region of the semiconductor device comprises:
forming a first recess inward of the channel layer relative to an outer periphery of the pillar-shaped active region.
35. The method of claim 32, wherein defining an active region of the semiconductor device comprises:
forming a first recess inward of the channel layer relative to an outer periphery of the pillar-shaped active region.
36. The method of claim 33, wherein defining an active region of the semiconductor device comprises:
forming a first recess inward of the channel layer relative to an outer periphery of the pillar-shaped active region.
37. The method of any of claims 34-36, wherein defining an active region of the semiconductor device comprises:
forming a modified layer on outer surfaces of the first source/drain layer, the channel layer, and the second source/drain layer at least once using a modifier; and
etching the modified layer at least once so that the channel layer forms a first recess inwards relative to the outer periphery of the columnar active region;
a sacrificial layer is formed in the first recess, an outer peripheral surface of the sacrificial layer being substantially coplanar with an outer peripheral surface of the columnar active region.
38. The method of claim 37, wherein defining an active region of the semiconductor device comprises:
forming a second recess into the first and second source/drain layers with respect to an outer periphery of the pillar-shaped active region.
39. The method of claim 38, wherein defining an active region of the semiconductor device comprises:
forming a modified layer on outer surfaces of the first source/drain layer, the channel layer, and the second source/drain layer at least once using a modifier; and
etching the modification layer at least once, so that a second recess is formed inwards relative to the outer periphery of the columnar active region by the first source/drain layer and the second source/drain layer;
and filling an isolation medium in the second recess, wherein the peripheral surface of the isolation medium is approximately coplanar with the peripheral surface of the sacrificial layer.
40. The method of claim 39, wherein forming a gate stack around an outer periphery of the channel layer comprises:
removing the sacrificial layer;
depositing a gate dielectric layer and a gate conductor layer in sequence;
etching back the gate dielectric layer and the gate conductor layer such that at least a portion of a bottom surface of the gate stack and at least a portion of a top surface of the first source/drain layer in contact with the channel layer are substantially coplanar; and/or at least a portion of a top surface of the gate stack and at least a portion of a bottom surface of the second source/drain layer in contact with the channel layer are substantially coplanar.
41. The method of claim 24, wherein forming a channel layer on the first source/drain layer comprises:
and epitaxially growing the channel layer on the first source/drain layer.
42. The method of claim 41, further comprising:
forming an isolation layer around the pillar-shaped active region on a top surface of a portion of the first source/drain layer beyond the pillar-shaped active region, wherein the top surface of the isolation layer is near a top surface of an upper portion of the first source/drain layer or between a top surface and a bottom surface of the channel layer.
43. An electronic device comprising an integrated circuit formed by the semiconductor device according to any one of claims 1 to 23.
44. The electronic device of claim 43, wherein the electronic device comprises a smartphone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source.
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