WO2018059109A1

WO2018059109A1 - Semiconductor device, manufacturing method thereof, and electronic apparatus comprising same

Info

Publication number: WO2018059109A1
Application number: PCT/CN2017/095178
Authority: WO
Inventors: 朱慧珑; 王桂磊; 亨利·H·阿达姆松; 张严波; 朱正勇
Original assignee: 中国科学院微电子研究所
Priority date: 2016-09-30
Filing date: 2017-07-31
Publication date: 2018-04-05

Abstract

A semiconductor device, manufacturing method thereof, and electronic apparatus comprising same. The semiconductor device comprises: a substrate (1001); a first source/drain layer (1005), a trench layer (1009), and a second source/drain layer (1013) sequentially stacked on the substrate (1001), wherein the trench layer (1009) comprises a semiconductor material enabling an increase of an on-state current and/or a decrease of an off-state current compared with the Si material; and a gate stack formed around a periphery of the trench layer (1009).

Description

Semiconductor device, method of manufacturing the same, and electronic device including the same

Reference to related application

This application claims Chinese Patent Application No. 201610872541.2 entitled "Semiconductor Device and Its Manufacturing Method and Electronic Device Comprising the Device", filed on September 30, 2016, and entitled "Semiconductor Device and The priority of the Chinese Patent Application No. 201710530250.X, which is incorporated herein by reference.

Technical field

The present disclosure relates to the field of semiconductors, and in particular to a vertical type semiconductor device having an enhanced on-state current and/or a reduced off-state current, a method of fabricating the same, and an electronic device including the same.

Background technique

In a horizontal type device such as a metal oxide semiconductor field effect transistor (MOSFET), the source, the gate and the drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device is not easily further reduced. Unlike this, in a vertical type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the surface of the substrate. Therefore, vertical devices are easier to shrink than horizontal devices.

Summary of the invention

In view of this, an object of the present disclosure is at least in part to provide a vertical type semiconductor device having an enhanced on-state current and/or a reduced off-state current, a method of fabricating the same, and an electronic device including the same.

According to an aspect of the present disclosure, there is provided a semiconductor device comprising: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate, wherein the channel layer A semiconductor material having an increased on-state current and/or a reduced off-state current compared to the Si material; and a gate stack formed around the outer circumference of the channel layer.

According to another aspect of the present disclosure, there is provided a method of fabricating a semiconductor device comprising: epitaxially growing a first source/drain layer on a substrate; epitaxial growth on the first source/drain layer is increased compared to Si material a large on-state current and/or a channel layer that reduces the off-state current; epitaxially growing a second source/drain layer on the channel layer; An active region of the semiconductor device is defined in the first source/drain layer, the channel layer, and the second source/drain layer; and a gate stack is formed around the outer circumference of the channel layer.

According to another aspect of the present disclosure, an electronic device including an integrated circuit formed of the above semiconductor device is provided.

According to an embodiment of the present disclosure, the channel layer may include a semiconductor material having an increased on-state current and/or a reduced off-state current compared to the Si material. For example, for a p-type device, the channel layer may include a semiconductor material such as a Group IV or III-V semiconductor material such as Ge, SiGe, SiGeSn, GeSn, which is advantageous for increasing the on-state current and/or reducing the off-state current. InSb, InGaSb; for n-type devices, the channel layer may include a semiconductor material such as a Group IV or III-V compound semiconductor material, SiGe, Ge, GaAs, which is advantageous for increasing the on-state current and/or reducing the off-state current. InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, GaN, InSb, InGaSb.

In addition, a gate stack is formed around the outer circumference of the channel layer and a channel is formed in the channel layer, so that the gate length is determined by the thickness of the channel layer. The channel layer can be formed, for example, by epitaxial growth, so that its thickness can be well controlled. Therefore, the gate length can be well controlled. The outer circumference of the channel layer may be recessed inwardly with respect to the outer circumferences of the first and second source/drain layers, so that the gate stack may be embedded in the recess, reducing or even avoiding overlap with the source/drain regions, contributing to Reduce the parasitic capacitance between the gate and the source/drain. In addition, the channel layer may be a single crystal semiconductor material, which may have a high on-state current and/or a small off-state current, thereby improving device performance.

DRAWINGS

The above and other objects, features and advantages of the present disclosure will become more apparent from

1 to 10(b) are diagrams showing a flow of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure;

FIG. 11 shows a schematic cross-sectional view of a semiconductor device in accordance with another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numerals indicate the same or similar components.

detailed description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. But it should be understood that these descriptions are only The scope of the present disclosure is not intended to be limiting. In addition, descriptions of well-known structures and techniques are omitted in the following description in order to avoid unnecessarily obscuring the concept of the present disclosure.

Various structural schematics in accordance with embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, and some details are exaggerated for clarity of illustration and some details may be omitted. The various regions, the shapes of the layers, and the relative sizes and positional relationships therebetween are merely exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and may be It is desirable to additionally design regions/layers having different shapes, sizes, and relative positions.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element. In addition, if a layer/element is "on" another layer/element, the layer/element may be "under" the other layer/element when the orientation is reversed.

A vertical type semiconductor device according to an embodiment of the present disclosure may include a first source/drain layer, a channel layer, and a second source/drain layer which are sequentially stacked on a substrate. Source/drain regions of the device may be formed in the first source/drain layer and the second source/drain layer, and a channel region of the device may be formed in the channel layer. The channel layer may comprise a semiconductor material that increases the on-state current and/or reduces the off-state current compared to the Si material. For example, for an n-type device, the channel layer may employ a semiconductor material that facilitates improved electron mobility, such as a Group IV or III-V compound semiconductor such as SiGe, Ge, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa. InAlGa, InSb, InGaSb or GaN; for p-type devices, the channel layer may employ a semiconductor material that facilitates improved hole mobility, such as Group IV or III-V semiconductor materials such as Ge, SiGe, SiGeSn, InSb, InGaSb Or GeSn.

According to an embodiment of the present disclosure, such a semiconductor device may be a conventional field effect transistor (FET). In the case of a FET, the first source/drain layer and the second source/drain layer (or source/drain regions on both sides of the channel layer) may have the same conductivity type (eg, n-type or p-type) doping miscellaneous. A conductive path may be formed through the channel region between the source/drain regions at both ends of the channel region. Alternatively, such a semiconductor device may be a tunneling FET. In the case of tunneling FETs, the first source/drain layer and the second source/drain layer (or source/drain regions on both sides of the channel layer) may have different conductivity types (eg, n-type and p, respectively) Type) doping. In this case, charged particles such as electrons can tunnel from the source region through the channel region into the drain region, thereby forming a conduction path between the source region and the drain region. Despite the conduction mechanism in conventional FETs and tunneling FETs They are not the same, but they all exhibit electrical properties that can be controlled by the gate to control the conduction between the source/drain regions. Therefore, for the conventional FET and the tunneling FET, the terms "source/drain layer (source/drain region)" and "channel layer (channel region)" are collectively described, although there is no general meaning in the tunneling FET. "Channel" on the top.

The gate stack may be formed around the outer circumference of the channel layer. Thus, the gate length can be determined by the thickness of the channel layer itself, rather than relying on time consuming etching as in the conventional art. The channel layer can be formed, for example, by epitaxial growth, so that its thickness can be well controlled. Therefore, the gate length can be well controlled. The outer circumference of the channel layer may be recessed inwardly with respect to the outer circumferences of the first and second source/drain layers. In this way, the formed gate stack can be embedded in the recess of the channel layer with respect to the first and second source/drain layers, reducing or even avoiding overlap with the source/drain regions, helping to reduce the gate and source/ Parasitic capacitance between drains.

The channel layer may be composed of a single crystal semiconductor material to improve device performance. Of course, the first and second source/drain layers may also be composed of a single crystal semiconductor material. In this case, the single crystal semiconductor material of the channel layer and the single crystal semiconductor material of the source/drain layer may be a eutectic. The electron or hole mobility of the channel layer single crystal semiconductor material may be greater than the electron or hole mobility of the first and second source/drain layers. In addition, the forbidden band width of the first and second source/drain layers may be greater than the forbidden band width of the channel layer single crystal semiconductor material.

According to an embodiment of the present disclosure, the channel layer single crystal semiconductor material and the first and second source/drain layers may have the same crystal structure. In this case, the lattice constant of the first and second source/drain layers without strain may be greater than the lattice constant of the channel layer single crystal semiconductor material without strain. Thus, the carrier mobility of the channel layer single crystal semiconductor material may be greater than the carrier mobility in the absence of strain, or the effective mass of the lighter carriers of the channel layer single crystal semiconductor material may be less than The effective mass of the lighter carriers in the absence of strain, or the concentration of the lighter carriers of the channel layer single crystal semiconductor material may be greater than the concentration of the lighter carriers in the absence of strain. . Alternatively, the lattice constant of the first and second source/drain layers without strain may be smaller than the lattice constant of the channel layer single crystal semiconductor material without strain. Thus, the electron mobility of the channel layer single crystal semiconductor material is greater than that of the electron mobility in the absence of strain, or the effective mass of the electron of the channel layer single crystal semiconductor material is smaller than that of the electron without strain. Effective quality.

According to an embodiment of the present disclosure, between the first source/drain layer and the channel layer and/or between the channel layer and the second source/drain layer (in the case of tunneling FETs, particularly A leakage confinement layer or an on-state current enhancement layer is provided between the two layers constituting the tunnel junction. The band gap of the leakage limiting layer may be larger than the band gap above it A band gap of at least one of the layer adjacent thereto and the layer adjacent thereto. The open current enhancement layer may have a band gap smaller than a band gap of at least one of the layer adjacent thereto and the layer adjacent thereto. Due to this difference in bandgap, it is possible to suppress leakage or enhance the on-state current.

According to an embodiment of the present disclosure, doping for the source/drain regions may partially enter the channel layer adjacent to the source/drain regions close to the end of the first source/drain layer and the second source/drain layer or the leak confinement layer The on-state current enhancement layer (if present). Thereby, a doping profile is formed in the channel layer near the end of the first source/drain layer and the second source/drain layer or the leakage confinement layer, which helps to reduce the source/drain regions and the channel when the device is turned on. Resistance between the regions to improve device performance.

According to an embodiment of the present disclosure, the first and second source/drain layers may include a semiconductor material different from the channel layer (but may belong to the same material system, for example, for an n-type device, a source/drain layer and a channel layer) Different III-V compound semiconductor materials or Group IV semiconductor materials may be included; for p-type devices, the source/drain layers and channel layers may include different Group IV semiconductor materials or III-V compound semiconductor materials). Thus, it is advantageous to perform processing such as selective etching and/or switching current optimization on the channel layer to be recessed relative to the first and second source/drain layers. Additionally, the first source/drain layer and the second source/drain layer may comprise the same semiconductor material.

Each of the semiconductor layers may be an epitaxial layer on the substrate. For example, the first source/drain layer may be a semiconductor layer epitaxially grown on a substrate, the channel layer may be a semiconductor layer epitaxially grown on the first source/drain layer, and the second source/drain layer may be in the channel A semiconductor layer epitaxially grown on the layer.

Such a semiconductor device can be manufactured, for example, as follows. Specifically, the first source/drain layer may be epitaxially grown on the substrate. Next, a channel layer may be epitaxially grown on the first source/drain layer, and a non-silicon semiconductor material that increases the on-state current and/or reduces the off-state current compared to the Si material may be utilized in growing the channel layer. And the second source/drain layer may be epitaxially grown on the channel layer. At the time of epitaxial growth, the thickness of the grown channel layer can be controlled. Due to epitaxial growth, respectively, at least one pair of adjacent layers may have a clear crystal interface. Alternatively, each layer may be separately doped so that at least one pair of adjacent layers may have a doping concentration interface.

A leakage confinement layer and/or an on-state current enhancement layer may also be epitaxially grown between the first source/drain layer and the channel layer and/or between the channel layer and the second source/drain layer to suppress leakage and / or enhance the on-state current.

For the stacked first source/drain layers, channel layers and second source/drain layers (and the leakage limiting layer or the on-state current enhancement layer, if present), an active region can be defined therein. For example, you can rely on them The sub-selective etch is the desired shape. Generally, the active region may be columnar (eg, cylindrical). In order to facilitate connection of the source/drain regions formed in the first source/drain layer in a subsequent process, the etching of the first source/drain layer may be directed only to the upper portion of the first source/drain layer, thereby the first source/drain layer The lower part can extend beyond the outer circumference of its upper portion. Then, a gate stack can be formed around the outer circumference of the channel layer.

In addition, the outer circumference of the channel layer may be recessed inwardly with respect to the outer circumferences of the first and second source/drain layers to define a space for accommodating the gate stack. For example, this can be achieved by selective etching. In this case, the gate stack can be embedded in the recess.

Source/drain regions may be formed in the first and second source/drain layers. For example, this can be achieved by doping the first and second source/drain layers. For example, ion implantation, plasma doping, or in-situ doping while growing the first and second source/drain layers may be performed. Doping of the first and second source/drain layers may enter the layer adjacent thereto.

The present disclosure can be presented in various forms, some of which are described below.

1 to 10(b) illustrate a flow chart for fabricating a semiconductor device in accordance with an embodiment of the present disclosure.

As shown in FIG. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a III-V compound semiconductor substrate, or a Group IV semiconductor liner. Bottom (for example, SiGe, Ge, SiGeSn, GeSn, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, InSb, InGaSb or GaN). In the following description, a bulk Si substrate will be described as an example for convenience of explanation.

In this example, for a device to be formed on substrate 1001, its performance is improved by semiconductor material selection (eg, non-silicon material). In order to improve the quality of other semiconductor material layers that are subsequently grown, a buffer layer 1003 may be formed on the substrate 1001, for example, by epitaxial growth. For example, the buffer layer 1003 may include Si _1-b Ge _b (eg, b is between about 0.1 and 1) and has a thickness of, for example, about 200 nm to several micrometers. At least the top of the buffer layer 1003 can be relaxed so that high quality layers of other semiconductor materials can subsequently be grown thereon.

At the top of the buffer layer, a well region 1003w can be formed. If a p-type device is to be formed, the well region 1003w may be an n-type well; if an n-type device is to be formed, the well region 1003w may be a p-type well. The well region 1003w may be formed, for example, by implanting a corresponding conductivity type (p-type or n-type) dopant into the buffer layer 1003, and the doping concentration may be about 1E17-2E18 cm ^-3 . There are various ways to set such a well region in the art, and details are not described herein again.

On the buffer layer 1003, the first source/drain layer 1005, the first leak restricting layer 1007, the channel layer 1009, the second leak restricting layer 1011, and the second source/drain layer 1013 may be sequentially formed by, for example, epitaxial growth. These are all layers of semiconductor material.

The channel layer 1009 may include a semiconductor material capable of increasing an on-state current and/or decreasing an off-state current, for example, for a p-type device, may be a material capable of improving carrier mobility. Here, the so-called "improvement" is generally relative to conventional Si materials (in the absence of strain or stress). For example, channel layer 1009 can comprise a Group IV semiconductor material, such as Ge or Si _1-y Ge _y (eg, y is between about 0.1 and 1). The Ge-based material can enhance the mobility of electrons or holes with respect to the Si material, and thus is suitable for both the n-type device and the p-type device. The thickness of the channel layer 1009 can determine the gate length, for example, from about 10 to 100 nm. When the channel layer 1009 is epitaxially grown, it may be doped in situ to adjust the threshold voltage (V _t ) of the device. For example, for an n-type device, the channel layer 1009 can be p-type doped (eg, B or In); for a p-type device, the channel layer 1009 can be n-doped (eg, P or As), The doping concentration may be about 1E17-2E18 cm ^-3 . Of course, the channel layer 1009 may also be not intentionally doped.

The first source/drain layer 1005 and the second source/drain layer 1013 may include a semiconductor material different from the channel layer. Here, the term "different" means not only that the constituent components are different, but also that the constituent components are the same but the component contents are different. This difference is primarily to provide etch selectivity in the following processing. For example, the first source/drain layer 1005 can include Si _1-x Ge _x (eg, x is between 0 and 1, but x is different from y; the greater the difference between x and y, the etching options provided The more pronounced, the second source/drain layer 1013 may comprise Si _1-z Ge _z (eg z is between 0 and 1, but z is different from y; the greater the difference between z and y, the provided The etch selectivity is more obvious). The materials of the first source/drain layer 1005 and the second source/drain layer 1013 may be substantially the same, that is, x may be approximately equal to or equal to z. The thickness of the first source/drain layer 1005 and the second source/drain layer 1013 may be about 20-50 nm. When the first source/drain layer 1005 and the second source/drain layer 1013 are epitaxially grown, they may be doped in situ. For example, for an n-type device, the first source/drain layer 1005 and the second source/drain layer 1013 may be doped with n-type (eg, As or P); for a p-type device, the first source/drain layer may be applied 1005 and the second source/drain layer 1013 are p-type doped (for example, B or BF ₂ ), and the doping concentration may be about 1E17-1E20 cm ^-3 .

The

leakage confinement layers

1007 and 1011 may include semiconductor materials different from the channel layer and the source/drain layers. Again, this difference is primarily to provide etch selectivity in the following processing. For example, the leakage limiting layer 1007 may include Si _1-LR1 Ge _LR1 (eg, LR1 is between 0 and 1, but LR1 is different from x, y, z; the greater the difference between LR1 and x, y, z, The more etch selectivity provided, the leakage limiting layer 1011 may comprise Si _1-LR2 Ge _LR2 (eg, LR2 is between 0 and 1, but LR2 is different from x, y, z; LR2 and x, y, z) The greater the difference between them, the more etch selectivity is provided). The materials of the

leakage confinement layers

1007 and 1011 may be substantially the same, that is, LR1 may be approximately equal to or equal to LR2. The thickness of the

leakage confinement layers

1007 and 1011 may be about 1-10 nm.

Here, the

leakage restricting layers

1007 and 1011 are provided to suppress leakage. To this end, the band gaps of the

leakage limiting layers

1007 and 1011 may be larger than the band gap of at least one of the layers adjacent thereto and the layer adjacent thereto. For example, for the leakage confinement layer 1007, the band gap may be greater than the band gap of at least one of the first source/drain layer 1005 and the channel layer 1009, for which LR1 may be greater than x, greater than y, or greater than both x and y. Likewise, for the leakage confinement layer 1011, the band gap may be greater than the band gap of at least one of the channel layer 1009 and the second source/drain layer 1013, for which LR2 may be greater than y, greater than z, or greater than both y and z. .

In addition, when the

leak confinement layers

1007 and 1011 are grown, they may be doped in situ. For example, for an n-type device, the

leakage confinement layers

1007 and 1011 may be doped with n-type (eg, As or P); for a p-type device, the

leakage confinement layers

1007 and 1011 may be p-doped (eg, B) Or BF ₂ ), the doping concentration may be about 1E18-1E21 cm ^-3 .

Of course, the

leakage limiting layers

1007 and 1011 can also be omitted. In this case, the first source/drain layer, the channel layer, and the second source/drain layer may be sequentially stacked and adjacent to each other.

Next, the active area of the device can be defined. For example, this can be done as follows. Specifically, as shown in FIGS. 2(a) and 2(b) (Fig. 2(a) is a cross-sectional view, and Fig. 2(b) is a plan view, in which the line AA' shows the intercepted position of the cross section), A photoresist is formed on the stack of the first source/drain layer 1005, the first leak confinement layer 1007, the channel layer 1009, the second leak confinement layer 1011, and the second source/drain layer 1013 shown in FIG. 1 (not shown) The photo-resist is patterned into a desired shape (in this example, substantially circular, or other shapes such as a rectangle) by photolithography (exposure and development), and the patterned photoresist is used as a mask. Selective etching of the second source/drain layer 1013, the second leak confinement layer 1011, the channel layer 1009, the first leak confinement layer 1007, and the first source/drain layer 1005, such as reactive ion etching (RIE) . The etching may proceed into the first source/drain layer 1005, but not to the bottom surface of the first source/drain layer 1005. Thus, each of the semiconductor layers after etching is columnar or wall-shaped (in this example, cylindrical). RIE can be, for example, roughly draped The direction is straight to the surface of the substrate such that the column is also substantially perpendicular to the surface of the substrate. After that, the photoresist can be removed.

Then, as shown in FIG. 3, the outer circumference of the channel layer 1009 may be made relative to the first source/drain layer 1005 and the second source/drain layer 1013 (and the first leak restricting layer 1007 and the second leak restricting layer 1011). The peripheral recess (in this example, recessed in a lateral direction substantially parallel to the surface of the substrate). For example, this can be achieved by further selectively etching the channel layer 1009 with respect to the first source/drain layer 1005 and the second source/drain layer 1013 (and the first leakage confinement layer 1007 and the second leakage confinement layer 1011). . As described above, this selective etching can be achieved due to the difference between y and x, z (and LR1, LR2, b). The selective etching can be performed by using an atomic layer etch (ALE) or a digital etch (Digital Etch) method for precise and controllable etching.

Thus, the active region of the semiconductor device, ie, the etched first source/drain layer 1005, the channel layer 1009, and the second source/drain layer 1013 (and the first leakage confinement layer 1007 and the second leakage limit) are defined. Layer 1011). In this example, the active area is substantially cylindrical. In the active region, the outer circumference of the first source/drain layer 1005 and the outer circumference of the second source/drain layer 1013 are substantially aligned, and the outer circumference of the channel layer 1009 is relatively concave.

Of course, the shape of the active region is not limited thereto, but other shapes may be formed according to the design layout. For example, in a top view, the active area may be elliptical, square, rectangular, or the like.

In the recess formed by the channel layer 1009 with respect to the outer circumferences of the first source/drain layer 1005 and the second source/drain layer 1013, a gate stack will be subsequently formed. In order to prevent subsequent processing from affecting the channel layer 1009 or leaving unnecessary material in the recess to affect the formation of the subsequent gate stack, a layer of material may be filled in the recess to occupy the space of the gate stack (thus, This layer of material can be referred to as a "sacrificial gate"). For example, this can be performed by depositing a nitride on the structure shown in FIG. 3 and then etching back the deposited nitride such as RIE. The RIE can be performed in a direction substantially perpendicular to the surface of the substrate, and the nitride can be left only in the recess to form the sacrificial gate 1015, as shown in FIG. In this case, the sacrificial gate 1015 can substantially fill the recess.

The

leakage confinement layers

1007 and 1011 can be relatively recessed in a similar process according to a similar process. The selective etching can be performed by the ALE method for precise and controllable etching, and the dielectric spacers 1017 are filled in the recesses. As shown in Figure 5. The dielectric spacers 1017 can include low k dielectrics such as oxides, nitrides, or oxynitrides. Here, the dielectric spacer 1017 may include a material different from the sacrificial gate 1015. For example, nitrogen oxides are not subsequently removed along with the sacrificial gate.

If necessary, particularly in the case where the

leakage confinement layers

1007 and 1011 are not doped (in situ), an annealing treatment may be performed to drive the dopants in the source/

drain layers

1005, 1013 into the leak. The

layers

1007 and 1011 are confined to reduce the resistance between the source/drain regions and the channel, thereby improving device performance. This annealing treatment can also activate the dopants in the source/

drain layers

1005, 1013.

In addition, it is also possible to perform silicidation on the surface of the source/drain layer to reduce the contact resistance. For example, a metal such as Co, Ti or NiPt or the like may be deposited on the structure shown in FIG. 5, and then annealed at a temperature of about 200 to 600 ° C to cause the metal to react with SiGe to form a silicide (for example, A SiNiPt) layer was obtained in the case of NiPt. Thereafter, the unreacted remaining metal can be removed.

An isolation layer can be formed around the active region to achieve electrical isolation. For example, as shown in FIG. 6, an oxide may be deposited on the structure shown in FIG. 5 and etched back to form an isolation layer 1019. The deposited oxide may be subjected to a planarization treatment such as chemical mechanical polishing (CMP) or sputtering before etch back. Here, the top surface of the isolation layer 1019 may be close to the interface between the channel layer 1009 and the first leakage confinement layer 1007.

When the isolation layer is formed, the sacrificial gate 1015 may be left to prevent the material of the isolation layer from entering the above-described recess to accommodate the gate stack. Thereafter, the sacrificial gate 1015 can be removed to release the space in the recess. For example, it may be relative to the isolation layer 1019 (oxide), the dielectric spacer 1017 (oxygen oxide), and the second source/drain layer 1013 (Si _1-z Ge _z ) and the channel layer 1009 (Si _1-y Ge _y ), selectively etching the sacrificial gate 1015 (nitride).

Then, as shown in FIG. 7, a gate stack can be formed in the recess. Specifically, the gate dielectric layer 1021 and the gate conductor layer 1023 may be sequentially deposited on the structure shown in FIG. 6 (the sacrificial gate 1015 is removed), and the deposited gate conductor layer 1023 (and optionally the gate dielectric layer 1021) may be deposited. The etch back is performed such that the top surface of the portion other than the recess is not higher than and preferably lower than the top surface of the channel layer 1009. For example, the gate dielectric layer 1021 can include a high-k gate dielectric such as HfO ₂ ; the gate conductor layer 1023 can include a metal gate conductor. In addition, between the gate dielectric layer 1021 and the gate conductor layer 1023, a function adjustment layer can also be formed. An interface layer such as an oxide may also be formed before the gate dielectric layer 1021 is formed.

In this way, the gate stack can be embedded in the recess to overlap the entire height of the channel layer 1009.

In addition, the top surface of the isolation layer 1019 may not be lower than the interface between the channel layer 1009 and the first leakage confinement layer 1007, preferably between the top surface and the bottom surface of the channel layer 1009 to reduce or avoid gate stacking. Possible overlap with source/drain to reduce parasitic capacitance between gate and source/drain.

Next, the shape of the gate stack can be adjusted to facilitate subsequent interconnect fabrication. For example, as shown in FIGS. 8(a) and 8(b) (Fig. 8(a) is a cross-sectional view, and Fig. 8(b) is a plan view, in which the line AA' shows the intercepted position of the cross section), it can be shown in the figure. A photoresist 1025 is formed on the structure shown in FIG. The photoresist 1025 is patterned, for example by photolithography, to cover a portion of the gate stack that is exposed outside the recess (in this example, the left half of the figure), and exposes another portion of the gate stack that is exposed outside of the recess (at In this example, the right half of the figure).

Then, as shown in Figures 9(a) and 9(b) (Fig. 9(a) is a cross-sectional view, and Fig. 9(b) is a plan view, in which the AA' line shows the intercepted position of the cross section), photolithography is possible. The paste 1025 is a mask, and the gate conductor layer 1023 is selectively etched such as RIE. Thus, the portion of the gate conductor layer 1023 that is hidden by the photoresist 1025 is retained except for the portion remaining inside the recess. As shown, the gate conductor layer 1023 extends in a strip shape from the recess beyond the periphery of the active region and may have an increased area end (eg, used as a contact pad). The electrical connection to the gate stack can then be achieved by this portion.

According to another embodiment, the gate dielectric layer 1021 may be further selectively etched such as RIE (not shown). Thereafter, the photoresist 1021 can be removed.

Then, as shown in FIGS. 10(a) and 10(b) (Fig. 10(a) is a cross-sectional view, and Fig. 10(b) is a plan view, in which the line AA' shows the intercepted position of the cross section), in the figure An interlayer dielectric layer 1027 is formed on the structures shown in 9(a) and 9(b). For example, an oxide can be deposited and planarized, such as CMP, to form interlayer dielectric layer 1027. In the interlayer dielectric layer 1027, a contact portion 1029-1 to the first source/drain layer 1005, a contact portion 1029-2 to the second source/drain layer 1013, and a contact portion 1029 to the gate conductor layer 1023 may be formed. 3. These contacts may be formed by etching holes in the interlayer dielectric layer 1027 and the isolation layer 1019 and filling a conductive material such as a metal therein.

According to another embodiment, the dielectric spacers 1017 may be removed prior to depositing the interlayer dielectric layer 1027 to form gas sidewalls. For example, before depositing the interlayer dielectric layer 1027, the gate dielectric layer 1021, the isolation layer 1019, and the dielectric spacer 1017 may be sequentially removed, and then the interlayer dielectric layer 1027 may be deposited, leaving unfilled on both sides of the

leakage limiting layers

1007 and 1011. The gap forms an air gap side wall.

Since the gate conductor layer 1023 extends beyond the outer periphery of the active region, its contact portion 1029-3 can be easily formed. In addition, since the lower portion of the first source/drain layer 1005 extends beyond the upper active layer and at least a portion thereof does not have the gate conductor layer, its contact portion 1029-1 can be easily formed.

As shown in FIGS. 10(a) and 10(b), the semiconductor device according to this embodiment includes a first source/drain layer 1005, a channel layer 1009, and a second source/drain layer 1013 stacked in the vertical direction. Source/drain regions are formed in the first source/drain layer 1005 and the second source/drain layer 1013. The channel layer 1009 is laterally recessed, and a gate stack (1021/1023) is formed around the outer circumference of the channel layer 1009 and embedded in the recess. Channel layer 1009 can include a material that can increase the on-state current and/or reduce the off-state current. Further,

leakage restricting layers

1007 and 1011 are formed between the first source/drain layer 1005 and the channel layer 1009 and between the channel layer 1009 and the second source/drain layer 1013.

It should be noted here that the recess of the channel layer with respect to the source/drain layer may not be present in the final device. For example, the source/drain layers may become thinner due to the silicidation process described above.

In the above embodiments, the channel layer uses a Group IV Ge-based material, which is particularly advantageous for a p-type device. For example, GeSn/Ge/GeSn, Ge/SiGe/Ge, SiGeSn/SiGeSn/SiGeSn may be formed (the composition of Ge, Sn in the source/drain layer may be larger than the composition of Ge, Sn in the channel layer), GeSn/SiGeSn/ GeSn and other stacking. In this case, there may be an enhanced strain in the channel layer.

According to another embodiment of the present disclosure, the channel layer may use a III-V compound semiconductor material, which may also increase the on-state current and/or decrease the off-state current. The channel layer of the III-V compound semiconductor material is particularly suitable for n-type devices. The channel layer III-V compound semiconductor material may include one of GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, GaN, InSb, InGaSb, or the like, or a combination thereof. The channel layer semiconductor material may also include SiGe, Ge, or the like.

The first source/drain layer 1005 and the second source/drain layer 1013 may also include a group III-V compound semiconductor material such as GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, GaN, InSb, InGaSb, or the like. The ratio of the group III element and the group V element in the source/drain layer may be different from the ratio of the group III element and the group V element in the channel layer. Alternatively, the first source/drain layer 1005 and the second source/drain layer 1013 source/drain layers may also include a Group IV semiconductor material such as SiGe, Ge, SiGeSn, GeSn, InSb, InGaSb, or the like.

For example, channel layer 1009 can comprise InGaAs having a thickness of between about 20 and 100 nm. The first source/drain layer 1005 and the second source/drain layer 1013 may include a semiconductor material different from the channel layer, such as a different III-V compound semiconductor material such as InP, having a thickness of about 20-40 nm. They can be doped as described above.

Likewise, the

leakage limiting layers

1007 and 1011 can also be formed. The leakage confinement layer 1007 may comprise a Group IV semiconductor material such as Si _1-LR1 Ge _LR1 (for example, LR1 between 0 and 1) or a III-V compound semiconductor material, and the leakage confinement layer 1011 may comprise a Group IV semiconductor material as described above. Si _1-LR2 Ge _LR2 (for example, LR2 is between 0 and 1) or a III-V compound semiconductor material. The value of LR1, LR2 or the composition and/or component content of the III-V compound semiconductor material may be selected such that the band gaps of the

leakage confinement layers

1007 and 1011 are larger than the layer adjacent thereto and adjacent thereto Band gap of at least one of the layers. For example, the leakage confinement layer 1007 may include one of SiGe, Ge, SiGeSn, GeSn, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, GaN, InSb, InGaSb, or a combination thereof.

In order to accommodate such a semiconductor stack, the buffer layer 1003 includes Si _1-b Ge _b (eg, b is between about 0.5 and 1).

In the above embodiment, the first source/drain layer 1005 and the second source/drain layer 1013 are doped with the same conductivity type (for example, p-type doping or n-type doping), so that a conventional FET (pFET) can be formed. Or nFET). According to another embodiment of the present disclosure, the first source/drain layer 1005 and the second source/drain layer 1013 may be doped with different conductivity types (eg, one of n-type doping, and the other of which is p-type doped ) to form a tunneling FET. Channel layer 1009 may be unintentionally doped (ie, an intrinsic layer) or may be lightly doped. This doping can be obtained by in-situ doping when growing these semiconductor layers.

In the case of a tunneling FET, two leakage confinement layers may not be provided, but only a leakage confinement layer may be provided at the tunneling junction. Figure 11 shows the device obtained in this case. As shown in FIG. 11, a leak restricting layer 1011 is provided between the channel layer 1009 and the second source/drain layer 1013, and the leak restricting layer 1007 is omitted. Of course, if tunneling occurs between the first source/drain layer and the channel layer 1009, the leak restricting layer 1007 may be disposed between the first source/drain layer and the channel layer 1009, and the leak restricting layer 1011 may be omitted.

In the above embodiment, a leak restricting layer having a band gap larger than that of the lower layer or the upper layer is used. According to another embodiment of the present disclosure, particularly in the case of a tunneling FET, instead of the leakage confinement layer, an on-state current enhancement layer may be used. In this case, the band gap of the on-state current enhancement layer may be smaller than the band gap of at least one of the layer adjacent thereto and the layer adjacent thereto. To this end LR1 may be less than x, less than y, or less than both x and y; LR2 may be less than y, less than z, or less than both y and z.

A semiconductor device according to an embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and thereby an electronic device can be constructed. Accordingly, the present disclosure also provides an inclusion An electronic device of the above semiconductor device. The electronic device can also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Such electronic devices are, for example, smart phones, computers, tablets (PCs), artificial intelligence, wearable devices, mobile power supplies, and the like.

According to an embodiment of the present disclosure, a method of fabricating a chip system (SoC) is also provided. The method can include the above method of fabricating a semiconductor device. In particular, a variety of devices can be integrated on a chip, at least some of which are fabricated in accordance with the methods of the present disclosure.

In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it will be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination.

The embodiments of the present disclosure have been described above. However, the examples are for illustrative purposes only and are not intended to limit the scope of the disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the present disclosure.

Claims

A semiconductor device comprising:

Substrate

a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate, wherein the channel layer includes an increased on-state current and/or a reduced off state compared to the Si material Current semiconductor material;

A gate stack formed around the outer circumference of the channel layer.
The semiconductor device according to claim 1, wherein

For a p-type device, the channel layer comprises a Group IV material system or a III-V compound semiconductor material;

For n-type devices, the channel layer comprises a Group IV material system or a III-V compound semiconductor material.
The semiconductor device according to claim 1 or 2, wherein

For a p-type device, the first source/drain layer and the second source/drain layer comprise SiGe, Ge, SiGeSn, InSb, InGaSb or GeSn, and the channel layer comprises SiGe, Ge, SiGeSn, InSb, InGaSb or GeSn;

For an n-type device, the first source/drain layer and the second source/drain layer comprise SiGe, Ge, SiGeSn, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa or GaN, and the channel layer comprises SiGe, Ge GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, InSb, InGaSb or GaN, the source/drain material and the channel material are doped and the III-V element compound element ratio is different.
The semiconductor device according to claim 1, wherein the first source/drain layer and the second source/drain layer have doping of the same conductivity type, whereby the semiconductor device constitutes a vertical type field effect transistor.
The semiconductor device according to claim 1, wherein the first source/drain layer and the second source/drain layer have doping of different conductivity types, so that the semiconductor device constitutes a vertical tunneling field effect transistor.
The semiconductor device according to claim 4 or 5, further comprising: a leakage confinement layer and/or opening provided between the first source/drain layer and the channel layer and between the channel layer and the second source/drain layer State current enhancement layer.
The semiconductor device according to claim 5, wherein one of the first source/drain layer and the second source/drain layer forms a tunneling junction with the channel layer, and the semiconductor device further includes a source/drain layer and a trench A leakage limiting layer and/or an on-state current enhancement layer between the layers.
The semiconductor device according to claim 6 or 7, wherein

The leakage confinement layer has a band gap larger than the layer adjacent thereto and the layer adjacent thereto One of the less band gaps,

The open current enhancement layer has a band gap that is less than a band gap of at least one of the layer adjacent thereto and the layer adjacent thereto.
The semiconductor device according to claim 6 or 7, further comprising: a dielectric spacer provided at both ends of the leakage confinement layer or the on-state current enhancement layer.
The semiconductor device of claim 9 wherein the dielectric spacer comprises a low-k dielectric or gas.
The semiconductor device according to claim 10, wherein the low-k dielectric comprises an oxide, a nitride or an oxynitride.
The semiconductor device according to claim 6 or 7, wherein the leakage confinement layer or the on-state current enhancement layer comprises SiGe, Ge, SiGeSn, GeSn, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, GaN, One of InSb, InGaSb, or a combination thereof.
The semiconductor device according to claim 1, wherein the channel layer comprises a channel layer single crystal semiconductor material.
The semiconductor device according to claim 13, wherein the channel layer single crystal semiconductor material has the same crystal structure as the first and second source/drain layers.
The semiconductor device according to claim 1, wherein the first source/drain layer is a semiconductor layer epitaxially grown on a substrate, and the channel layer is a semiconductor layer epitaxially grown on the first source/drain layer, the second source The drain layer is a semiconductor layer epitaxially grown on the channel layer.
The semiconductor device according to claim 1, wherein an outer circumference of the channel layer is recessed inward with respect to an outer circumference of the first and second source/drain layers, and a gate stack is embedded in an outer circumference of the channel layer with respect to the first and the The recess formed in the outer periphery of the two source/drain layers is self-aligned to the channel layer.
The semiconductor device according to claim 6 or 7, wherein at least one pair of adjacent layers in the first source/drain layer, the channel layer, the second source/drain layer, and the leakage confinement layer or the on-state current enhancement layer There is a crystal interface and/or a doping concentration interface.
The semiconductor device according to claim 1, wherein a crystal interface and/or a doping concentration interface is provided between at least one pair of adjacent layers of the first source drain layer, the channel layer, and the second source/drain layer.
A method of fabricating a semiconductor device, comprising:

Epitaxially growing a first source/drain layer on the substrate;

Epitaxially growing a channel layer having an increased on-state current and/or a reduced off-state current compared to the Si material on the first source/drain layer;

Epitaxially growing a second source/drain layer on the channel layer;

Defining an active region of the semiconductor device in the first source/drain layer, the channel layer, and the second source/drain layer;

A gate stack is formed around the outer circumference of the channel layer.
The method of claim 19, further comprising:

A leakage confinement layer and/or an on-state current enhancement layer is epitaxially grown between the first source/drain layer and the channel layer and/or between the channel layer and the second source/drain layer.
The method of claim 19 or 20, wherein defining the active region further comprises:

The outer circumference of the channel layer is recessed inward with respect to the outer circumferences of the first and second source/drain layers.
The method of claim 21 wherein defining the active region comprises:

Selective etching of the second source/drain layer, the channel layer, and the first source/drain layer in turn;

The channel layer is further selectively etched such that the channel layer is recessed with respect to the outer circumferences of the first and second source/drain layers.
The method according to claim 22, wherein the defined active region has a columnar shape, and the upper portion of the etched first source/drain layer has a columnar shape and the lower portion extends beyond the outer periphery of the columnar upper portion.
The method of claim 20 further comprising:

Selectively etching the leakage confinement layer or the on-state current enhancement layer to make it relatively concave;

In the relative recess of the leakage limiting layer or the on-state current enhancement layer, a dielectric spacer is formed.
The method according to claim 22 or 24, wherein the selective etching is atomic layer etching or digital etching.
The method of claim 24 wherein said forming a dielectric sidewall comprises forming a low-k dielectric sidewall and/or a gas sidewall.
The method of claim 21 further comprising:

The first source/drain layer and the second source/drain layer are doped to form source/drain regions in the first source/drain layer and the second source/drain layer.
The method of claim 27, wherein doping the first source/drain layer and the second source/drain layer comprises: doping the first source/drain layer and the second source/drain layer with the same conductivity type Miscellaneous or different Electrical type doping.
The method of claim 27 or 28, wherein performing doping comprises:

In situ doping is carried out while growing.
The method of claim 21 further comprising:

Forming a sacrificial gate in a recess formed in an outer circumference of the channel layer with respect to an outer circumference of the first and second source/drain layers;

An isolation layer is formed around the active region on the substrate, wherein a top surface of the isolation layer is adjacent an interface between the channel layer and a layer adjacent thereto therebelow.
The method of claim 30 wherein forming the gate stack comprises:

Forming a gate dielectric layer and a gate conductor layer sequentially on the isolation layer;

The gate conductor layer is etched back such that a top surface of the portion of the gate conductor layer outside the recess is lower than a top surface of the channel layer.
An electronic device comprising an integrated circuit formed by the semiconductor device according to any one of claims 1 to 18.
32. The electronic device of claim 32, further comprising: a display that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit.
The electronic device of claim 32, comprising a smart phone, a computer, a tablet, an artificial intelligence, a wearable device, or a mobile power source.