CN108198815B

CN108198815B - Semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Info

Publication number: CN108198815B
Application number: CN201711452736.2A
Authority: CN
Inventors: 朱慧珑
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2017-12-27
Filing date: 2017-12-27
Publication date: 2020-12-22
Anticipated expiration: 2037-12-27
Also published as: CN108198815A

Abstract

A semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are disclosed. According to an embodiment, a semiconductor device includes: a substrate; the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction; a gate stack formed around a periphery of the channel region; a first contact to the second source/drain region over the second source/drain region, wherein a first contact perimeter is substantially aligned with a second source/drain region perimeter.

Description

Semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a vertical type semiconductor device, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.

Background

In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a source, a gate, and a drain are arranged in a direction substantially parallel to a surface of a substrate. Due to this arrangement, the area occupied by the horizontal type device is reduced, and the area occupied by the source, the drain, and the gate is generally required to be reduced, so that the device performance is deteriorated (for example, power consumption and resistance increase), and thus the area of the horizontal type device is not easily reduced further. Unlike this, in the vertical type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, the area occupied by the vertical device is more easily reduced than the horizontal device.

Disclosure of Invention

In view of the above, it is an object of the present disclosure, at least in part, to provide a vertical type semiconductor device having improved performance, a method of manufacturing the same, and an electronic apparatus including such a semiconductor device.

According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate; the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction; a gate stack formed around a periphery of the channel region; a first contact to the second source/drain region over the second source/drain region, wherein a first contact perimeter is substantially aligned with a second source/drain region perimeter.

According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate; the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction; a gate stack formed around a periphery of the channel region; a spacer formed over the gate stack and on a sidewall of the active region; self-aligned metal contacts are formed over the gate stacks and on the sidewall of the isolation walls.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: a source region material layer is arranged on the substrate; providing a hard mask layer on the active area material layer, the hard mask layer including a first portion for defining an active area; patterning the active region material layer with the hard mask layer as a mask to define a vertical active region; forming an interlayer dielectric layer on the substrate, and carrying out planarization treatment on the interlayer dielectric layer to expose the hard mask layer; selectively etching the hard mask layer to remove the hard mask layer, thereby leaving a first trench in the inter-level dielectric layer corresponding to the vertical active region; and filling the first groove with a conductive material to form a first contact part.

According to another aspect of the present disclosure, there is provided an electronic apparatus including an integrated circuit formed of the above semiconductor device.

According to the embodiments of the present disclosure, the first contact outer circumference is substantially aligned with the second source/drain region outer circumference, thereby increasing the integration density of the device and reducing the mask steps, thereby reducing the manufacturing cost, and furthermore, the integration density is increased and the difficulty of forming the contact is reduced due to the formation of the self-aligned contact and the contact pillar. Thereby, a metal contact having a high aspect ratio can be formed (avoiding the process difficulty of etching a contact hole using, for example, a plasma etching method and refilling the contact hole with a material such as a metal), and the risk of photolithography misalignment is reduced due to the reduction of the photolithography step, thereby further increasing the integration density. In addition, since double patterning is not employed, manufacturing cost is reduced.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

fig. 1 to 14 show schematic diagrams of a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 15 to 21 show schematic diagrams of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure;

fig. 22 to 29 are schematic views showing a flow of manufacturing a semiconductor device according to still another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numerals denote the same or similar components.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

A vertical type semiconductor device according to an embodiment of the present disclosure may include a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on a substrate. The layers may be adjacent to each other, although other semiconductor layers may be present in between, such as a leakage suppressing layer and/or an on-current enhancing layer (a semiconductor layer with a larger or smaller bandgap than the adjacent layers). Source/drain regions of the device may be formed in the first source/drain layer and the second source/drain layer, and a channel region of the device may be formed in the channel layer. Such a semiconductor device may be a conventional Field Effect Transistor (FET) according to embodiments of the present disclosure. In the case of a FET, the first and second source/drain layers (or source/drain regions on either side of the channel layer) may have doping of the same conductivity type (e.g., n-type or p-type). A conductive path may be formed through the channel region between the source/drain regions at both ends of the channel region. Alternatively, such a semiconductor device may be a tunneling FET. In the case of a tunneling FET, the first and second source/drain layers (or, stated, the source/drain regions on either side of the channel layer) may have different conductivity type dopings (e.g., n-type and p-type, respectively). In this case, charged particles, such as electrons, may tunnel from the source region through the channel region and into the drain region, thereby forming a conductive path between the source and drain regions. Although the conduction mechanisms in conventional FETs and tunneling FETs are not the same, they both exhibit electrical properties that allow control of conduction between source/drain regions via the gate. Thus, for conventional FETs and punch-through FETs, the terms "source/drain layer (source/drain region)" and "channel layer (channel region)" are used collectively to describe the FET, even though there is no "channel" in the usual sense in a tunnel FET.

The gate stack may be formed around an outer periphery of the channel layer. Thus, the gate length may be determined by the thickness of the channel layer itself, rather than relying on time-consuming etching as in conventional techniques. The channel layer may be formed by, for example, epitaxial growth, so that its thickness can be well controlled. Therefore, the gate length can be well controlled. An outer periphery of the channel layer may be recessed inward with respect to outer peripheries of the first and second source/drain layers. In this way, the formed gate stack may be embedded in a recess of the channel layer relative to the first and second source/drain layers. Preferably, a range of the gate stack in a stacking direction (vertical direction, for example, substantially perpendicular to a substrate surface) of the first source/drain layer, the channel layer, and the second source/drain layer is within a range of the recess in the direction. Thus, overlap with the source/drain regions can be reduced or even avoided, helping to reduce parasitic capacitance between the gate and the source/drain regions.

The channel layer may be composed of a single-crystal semiconductor material such as single-crystal silicon or silicon germanium (SiGe) to improve device performance. Of course, the first and second source/drain layers may be made of a single crystal semiconductor material. In this case, the single crystal semiconductor material of the channel layer and the single crystal semiconductor material of the source/drain layer may be eutectic. The channel layer single crystal semiconductor material may have electron or hole mobility greater than that of the first and second source/drain layers. In addition, the band gap widths of the first and second source/drain layers may be larger than the band gap width of the single crystal semiconductor material of the channel layer.

According to an embodiment of the present disclosure, the channel layer single crystal semiconductor material and the first and second source/drain layers may have the same crystal structure. In this case, the lattice constant of the first and second source/drain layers in the absence of strain may be greater than the lattice constant of the channel layer single crystal semiconductor material in the absence of strain. Thus, the channel layer single crystal semiconductor material may have a carrier mobility greater than its carrier mobility in the absence of strain, or the channel layer single crystal semiconductor material may have an effective mass of carriers less than its effective mass of carriers in the absence of strain, or the channel layer single crystal semiconductor material may have a concentration of lighter carriers greater than its concentration of lighter carriers in the absence of strain. Alternatively, the lattice constant of the first and second source/drain layers in the absence of strain may be less than the lattice constant of the channel layer single crystal semiconductor material in the absence of strain. Thus, when the < 110 > direction of the channel layer single crystal semiconductor material is parallel to the current density vector between the source and drain, the electron mobility of the channel layer single crystal semiconductor material is greater than its electron mobility in the absence of strain, or the effective mass of electrons of the channel layer single crystal semiconductor material is less than its effective mass of electrons in the absence of strain.

According to an embodiment of the present disclosure, the doping for the source/drain region may partially enter the channel layer near the ends of the first and second source/drain layers. Therefore, doping distribution is formed at the end parts, close to the first source/drain layer and the second source/drain layer, of the channel layer, and therefore resistance between the source/drain region and the channel region when the device is turned on is reduced, and performance of the device is improved.

According to an embodiment of the present disclosure, the channel layer may include a semiconductor material different from the first and second source/drain layers. In this way, it is advantageous to process, e.g., selectively etch, the channel layer to be recessed with respect to the first and second source/drain layers. In addition, the first source/drain layer and the second source/drain layer may include the same semiconductor material.

For example, the first source/drain layer may be the semiconductor substrate itself. In this case, the channel layer may be a semiconductor layer epitaxially grown on the substrate, and the second source/drain layer may be a semiconductor layer epitaxially grown on the channel layer. Alternatively, the first source/drain layer may be a semiconductor layer epitaxially grown on the substrate. In this case, the channel layer may be a semiconductor layer epitaxially grown on the first source/drain layer, and the second source/drain layer may be a semiconductor layer epitaxially grown on the channel layer.

Stress liners may also be provided on the surfaces of the first and second source/drain layers according to embodiments of the present disclosure. For an n-type device, the stress liner may be under compressive stress to create tensile stress in the channel layer; for a p-type device, the stress liner may be under tensile stress to create compressive stress in the channel layer. Therefore, the device performance can be further improved.

According to an embodiment of the present disclosure, an outer circumference of the first contact substantially coincides with an outer circumference of the second source/drain region; or the semiconductor device may further include a metal semiconductor compound layer formed on a surface of the second source/drain region, and an outer periphery of the first contact portion substantially coincides with an outer periphery of the metal semiconductor compound layer formed on the surface of the second source/drain region.

According to an embodiment of the present disclosure, the first source/drain region comprises a lateral extension portion that may extend beyond a portion of the active region above it, the device further comprising: a second contact to the first source/drain region over the laterally extending portion of the first source/drain region, the second contact may include a first portion and a second portion stacked one on top of the other on the substrate and vertically aligned with each other, and the first portion may include a low-resistance semiconductor material and/or a metal semiconductor compound. The second portion of the second contact may include the same material as the first contact and substantially the same thickness in a vertical direction as the first contact, and the first portion of the second contact may include a semiconductor material and/or a metal-semiconductor compound material. The first portion of the second contact comprises a semiconductor material of which the element is at least partially the same as part of the semiconductor element in the first source/drain region or the channel region or the second source/drain region.

According to an embodiment of the present disclosure, the first contact and/or the second contact contain metal Cu, Co, W, Ru, combinations thereof, and the like.

According to an embodiment of the present disclosure, the second contact may further include a metal layer surrounding the outer circumference of the first and second portions, the metal layer may contain metal Cu, Co, W, Ru, or a combination of any of them.

According to an embodiment of the present disclosure, the device may further comprise a third contact to the gate conductor layer in the gate stack. Wherein the third contact portion and the gate conductor layer may be integral; or the third contact portion comprises the same material as the first contact portion.

According to an embodiment of the present disclosure, the present application also discloses a semiconductor device, including: a substrate; the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction; a gate stack formed around a periphery of the channel region; a spacer formed over the gate stack and on a sidewall of the active region; self-aligned metal contacts are formed over the gate stacks and on the sidewall of the isolation walls.

According to an embodiment of the present disclosure, the device may further include a third contact formed over the self-aligned metal contact that is substantially self-aligned to the self-aligned metal contact; a diffusion barrier layer conformally formed on the sidewalls of the isolation walls and over the gate stack; a conformally formed metal contact layer may be included over the diffusion barrier layer; the sidewalls of the metal contact layer may include a conformally formed thin dielectric layer. In addition, the device may further include a self-aligned metal contact formed from the diffusion barrier layer and the metal contact layer; a third contact formed on the self-aligned metal contact that is substantially self-aligned to the self-aligned metal contact. The self-aligned metal contact and/or the third contact may comprise metal Cu, Co, W, Ru, combinations thereof, and the like.

Such a semiconductor device can be manufactured, for example, as follows. Specifically, a stack of a first source/drain layer, a channel layer, and a second source/drain layer may be provided on a substrate. As described above, the first source/drain layer may be provided by the substrate itself or by epitaxial growth on the substrate. Next, a channel layer may be epitaxially grown on the first source/drain layer, and a second source/drain layer may be epitaxially grown on the channel layer. In the epitaxial growth, the thickness of the grown channel layer may be controlled. Due to the separate epitaxial growth, at least some adjacent layers may have a sharp crystalline interface between them. In addition, each layer may be doped differently, respectively, so that at least some adjacent layers may have a doping concentration interface therebetween.

For the first source/drain layer, the channel layer, and the second source/drain layer that are stacked, an active region may be defined therein. For example, they may be selectively etched into a desired shape in turn. In general, the active region may have a columnar shape (e.g., a cylindrical shape). In order to facilitate connection of source/drain regions formed in the first source/drain layer in a subsequent process, the first source/drain layer may be etched only for an upper portion of the first source/drain layer so that a lower portion of the first source/drain layer may extend beyond a periphery of the upper portion thereof. A gate stack may then be formed around the periphery of the channel layer.

In addition, the outer circumference of the channel layer may be recessed inward with respect to the outer circumferences of the first and second source/drain layers so as to define a space accommodating the gate stack. This can be achieved, for example, by selective etching. In this case, the gate stack may be embedded in the recess.

Source/drain regions may be formed in the first and second source/drain layers. This may be achieved, for example, by doping the first and second source/drain layers. For example, ion implantation, plasma doping, or in-situ doping may be performed while the first and second source/drain layers are grown. According to an advantageous embodiment, a sacrificial gate may be formed in a recess formed in the outer periphery of the channel layer with respect to the outer periphery of the first and second source/drain layers, and then a dopant source layer may be formed on the surfaces of the first and second source/drain layers, and dopants in the dopant source layer may be introduced into the active region through the first and second source/drain layers by, for example, annealing. The sacrificial gate may prevent dopants in the dopant source layer from directly entering the channel layer. However, there may be a portion of the dopant entering the channel layer through the first and second source/drain layers near the ends of the first and second source/drain layers.

The present disclosure may be presented in various forms, some examples of which are described below.

Fig. 1 through 14 show a flow chart for manufacturing a semiconductor device according to an embodiment of the present disclosure.

As shown in fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, a bulk Si substrate is described as an example for convenience of explanation.

On the substrate 1001, a channel layer 1003, another semiconductor layer 1005, and a hard mask layer 1031 may be formed in order by, for example, epitaxial growth. For example, channel layer 1003 may include a semiconductor material such as SiGe (the atomic percent of Ge may be about 10-40%) that is different from substrate 1001, semiconductor layer 1005, and has a thickness of about 10-100 nm; semiconductor layer 1005 may comprise the same semiconductor material as substrate 1001, such as Si, to a thickness of about 20-50 nm. The hard mask layer 1031 may comprise a nitride, such as silicon nitride, having a thickness of about 30-100 nm. Of course, the present disclosure is not limited thereto. For example, the channel layer 1003 may include the same constituent components as the substrate 1001 or the semiconductor layer 1005, but with different compositional content of the semiconductor material (e.g., both SiGe, but with different atomic percentages of Ge), so long as the channel layer 1003 has etch selectivity with respect to the overlying substrate 1001 and the overlying semiconductor layer 1005.

Next, the active region of the device may be defined. This may be done, for example, as follows. Specifically, as shown in fig. 2(a) and 2(b) (fig. 2(a) is a sectional view, fig. 2(b) is a top view, in which an AA' line shows a position where a section is taken out), a photoresist (not shown) may be formed on the stack of the substrate 1001, the channel layer 1003, the semiconductor layer 1005, and the hard mask layer 1031 shown in fig. 1, the photoresist may be patterned into two desired shapes (in this example, a substantially circular shape, and other shapes such as a rectangular shape may also be employed) by photolithography (exposure and development), and the hard mask layer 1031, the semiconductor layer 1005, the channel layer 1003, and the substrate 1001 may be selectively etched such as Reactive Ion Etching (RIE) in this order using the patterned photoresist as a mask. The etch proceeds into the substrate 1001, but not to the bottom surface of the substrate 1001. Then, two pillars (in this example, cylindrical shape) are formed on the hard mask layer 1031, the semiconductor layer 1005, the channel layer 1003, and the upper portion of the substrate 1001 after etching. Correspondingly, the hard mask layer 1031, the semiconductor layer 1005 and the channel layer 1003 are respectively formed as two portions of a first hard mask layer 1031-1, a second hard mask layer 1031-2, a first semiconductor layer 1005-1, a second semiconductor layer 1005-2, a first channel layer 1003-1 and a second channel layer 1003-2. Since the patterning of the active area material layer is stopped before proceeding to the bottom surface of the active area material layer, the active area material layer is then patterned into a first stack (i.e., left-side pillar) corresponding to the first hard mask layer 1031-1, which serves as an active area, and a second stack (i.e., right-side pillar) corresponding to the second hard mask layer 1031-2, and the first stack and the second stack are connected together at the bottom. The RIE may, for example, be performed in a direction substantially perpendicular to the substrate surface such that the first stack and the second stack are also substantially perpendicular to the substrate surface. Thereafter, the photoresist may be removed.

A first isolation layer, such as a shallow trench isolation layer 1033, may be formed around the first stack (active region) and the second stack to achieve electrical isolation. For example, as shown in fig. 2(a), a trench may be structurally patterned, an oxide deposited and etched back to the location of the upper surface of the bottom of substrate 1001 to form a first isolation layer 1033. The deposited oxide may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP) or sputtering prior to etch back. Here, a top surface of the first isolation layer 1033 may be near an interface between the channel layer 1003 and the substrate 1001.

Then, as shown in fig. 3, the outer periphery of the first channel layer 1003-1 may be recessed with respect to the outer periphery of the substrate 1001 and the first semiconductor layer 1005-1 (in this example, recessed in a lateral direction substantially parallel to the substrate surface). This may be accomplished, for example, by further selectively etching the channel layer 1003-1 relative to the substrate 1001 and the first semiconductor layer 1005-1. For example, Atomic Layer etching (Atomic Layer Etch) or Digital etching (Digital Etch) may be used for the selective etching. For example, the surfaces of another portion of the substrate 1001, the first hard mask layer 1031-1, the first channel layer 1003-1, and the first semiconductor layer 1005-1 are oxidized, for example, by first covering an oxynitride layer over the right-side pillars (comprised of the second hard mask layer 1031-2, the second semiconductor layer 1005-2, and a portion of the substrate 1001), for example, by deposition, and then removing their respective surface oxide layers, for example, by heat treatment. In the case where the first channel layer 1003-1 is SiGe and the substrate 1001 and the first semiconductor layer 1005-1 are Si, the oxidation rate of SiGe is higher than that of Si, and the oxide on SiGe is more easily removed. The oxidation-removal oxide step may be repeated to achieve the desired recess. This way the degree of recessing can be better controlled than with selective etching.

Thus, the active region of the semiconductor device is defined (the etched substrate 1001, and in particular the upper portion thereof, the first channel layer 1003-1 and the first semiconductor layer 1005-1, as shown by the left column in fig. 3). In this example, the active region is substantially cylindrical. In the active region, the upper portion of the substrate 1001 and the outer circumference of the first semiconductor layer 1005-1 are substantially aligned, and the outer circumference of the first channel layer 1003-1 is relatively recessed. The recessed upper and lower sidewalls are defined by the interfaces between the first channel layer 1003-1 and the first semiconductor layer 1005-1 and the first channel layer 1003-1 and the substrate 1001, respectively.

Of course, the shape of the active region is not limited thereto, but may be formed in other shapes according to devious layouts. For example, in a top view, the active region may be oval, square, rectangular, etc.

In a recess formed in the first channel layer 1003-1 with respect to the upper portion of the substrate 1001 and the outer circumference of the first semiconductor layer 1005-1, a gate stack will be subsequently formed. To avoid subsequent processing affecting the channel layer 1003 or leaving unnecessary material in the recess to affect the formation of subsequent gate stacks, a layer of material may be filled in the recess to occupy space in the gate stack (and thus may be referred to as a "sacrificial gate"). This may be done, for example, by depositing oxynitride on the structure shown in fig. 3, and then etching back the deposited oxynitride, such as RIE. The RIE may be performed in a direction substantially perpendicular to the substrate surface to remove excess oxynitride while removing the oxynitride formed on the right side pillar from the previous process so that the oxynitride may only remain in the recess to form the sacrificial gate 1007, as shown in fig. 4. In this case, the sacrificial gate 1007 may substantially fill the recess.

Next, source/drain regions may be formed in the substrate 1001 and the first semiconductor layer 1005-1. This may be formed by doping the substrate 1001 and the first semiconductor layer 1005-1. This may be done, for example, as follows.

Specifically, as shown in fig. 5, a dopant source layer 1009 may be formed on the structure shown in fig. 4. For example, the dopant source layer 1009 may include an oxide such as silicon oxide, in which a dopant is contained. For n-type devices, an n-type dopant may be included; for a p-type device, a p-type dopant may be included. Here, the dopant source layer 1009 may be a thin film and thus may be deposited substantially conformally on the surface of the structure shown in fig. 4 by, for example, Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

Next, as shown in fig. 6, dopants contained in the dopant source layer 1009 may be driven into the active region and into the left pillar as the second stack by, for example, annealing, thereby forming a doped region therein, as shown by the shaded portion. More specifically, one of the source/drain regions 1011-1 may be formed in the substrate 1001 and the other source/drain region 1011-2 may be formed in the first semiconductor layer 1005-1. In addition, the dopant also enters a portion of the substrate 1001, the second channel layer 1003-2, and the second semiconductor layer 1005-2, which constitute the second stack. And as can be seen in fig. 6, the dopant source layer 1009 includes a portion that extends along a horizontal surface of the substrate 1001 such that doped regions formed in the substrate 1001 extend beyond the outer perimeter of the pillars. The first stack and the second stack, which are pillars, are conductively connected together at the bottom by the horizontally extending portion of the doped substrate 1001, after which the dopant source layer 1009 may be removed.

In addition, although the sacrificial gate 1007 is present, a dopant may enter the first channel layer 1003-1 through the substrate 1001 and the first semiconductor layer 1005-1, thereby forming a certain doping profile at both upper and lower ends of the first channel layer 1003-1, as shown by the oval dotted line in the figure. The doping distribution can reduce the resistance between the source region and the drain region when the device is conducted, so that the performance of the device is improved.

In the above example, the source/drain regions are formed by driving (drive in) dopants from the dopant source layer into the active region, but the present disclosure is not limited thereto. For example, the source/drain regions can be formed by ion implantation, plasma doping (e.g., conformal doping along the surface of the structure in fig. 4), and the like. Alternatively, in the process described above in connection with fig. 1, a well region may be formed in the substrate 1001, then the channel layer 1003 may be grown thereon, and then the semiconductor layer 1005 may be doped in situ on the channel layer 1003. The channel layer 1003 may also be doped in-situ as it is grown to adjust the threshold voltage (V) of the device_t)。

In addition, in order to reduce contact resistance, the source/drain layer and the second stack may be subjected to silicidation. As shown in FIG. 7(a), for example, a layer of NiPt (or Co or Ti) may be deposited on the structure shown in FIG. 6, e.g., with a Pt content of about 2-10% and a thickness of about 2-10nm, and annealed at a temperature of about 200-900 deg.C to react the NiPt with Si (in the source/drain layer) or SiGe (1003-2) to form a metal semiconductor compound such as SiNiPt or SiGeNiPt. After that, the unreacted remaining NiPt may be removed.

It is noted that since the second stack (i.e., the right pillars) does not serve as an active region but merely serves as a conductive path, in another embodiment, as shown in fig. 7(b), NiPt deposited on the second stack (i.e., the right pillars) may be sufficiently reacted with Si and SiGe, and in the case where the right pillars are finer, a portion of the substrate and the semiconductor material in the second semiconductor layer 1005-2, such as doped silicon and silicon germanium in the second channel layer 1006-2, may be sufficiently reacted with NiPt (or Co or Ti) deposited on the right pillars to completely generate a metal-semiconductor compound (which includes a metal silicide and/or a metal silicide-germanide), thereby forming a unitary metal-semiconductor compound. After that, the unreacted remaining NiPt may be removed.

A second isolation layer may be formed over the substrate and the shallow trench isolation layer, specifically, as shown in fig. 8, an oxide is deposited over the substrate 1001 and the shallow trench isolation layer 1033 and etched back to the position of the interface between the channel layers 1003-1 and 1003-2 and the substrate 1001 (i.e., the interface between the SiGe layer and the Si layer) to form a second isolation layer 1013. The deposited oxide may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP) or sputtering prior to etch back.

A gate dielectric layer and a gate conductor layer may be formed in the recess. Specifically, as shown in fig. 9, the sacrificial gate 1007 may be removed from the structure shown in fig. 8, a gate dielectric layer 1015 and a gate conductor layer 1017 may be sequentially deposited, and the deposited gate conductor layer 1017 may be etched back to be flush with the top surfaces of the hard mask layers 1031-1 and 1031-2. For example, the gate dielectric layer 1015 may include a high-K gate dielectric such as HfO₂(ii) a The gate conductor layer 1017 may comprise a metal gate conductor. In addition, between the gate dielectric layer 1015 and the gate conductor layer 1017, a work function adjusting layer may be further formed, and the function adjusting layer may include a threshold voltage Vt adjusting metal. An interfacial layer, such as an oxide, may also be formed prior to forming the gate dielectric layer 1015.

In this way, the gate dielectric layer 1015 and the gate conductor layer 1017 may be embedded into the recess, and the top surfaces of the gate dielectric layer 1015 and the gate conductor layer 1017 are flush with the top surfaces of the hard mask layers 1031-1, 1031-2.

The gate conductor layer may be patterned to form a gate stack, and specifically, as shown in fig. 10, a photoresist may be coated on the structure shown in fig. 9, the photoresist may be patterned to form a photoresist layer 1039, and then the gate conductor layer 1017 may be selectively etched, such as RIE, with the photoresist 1039 as a mask. Thus, the gate conductor layer 1017 is etched to a level not higher than and preferably lower than the top surface of the channel layers 1003-1 and 1003-2, except for the portion left within the recess and the portion shielded by the photoresist 1019.

Then, as shown in fig. 11, the photoresist layer 1039 is removed, the photoresist is coated again, and the photoresist is patterned to form a photoresist layer 1019, and then selective etching such as RIE is performed again on the remaining gate conductor layer 1017 with the photoresist layer 1019 as a mask. Thus, the gate conductor layer 1017 is etched away except for the portion remaining within the recess and the portion blocked by the photoresist 1039. Thus, the gate conductor layer is formed only around the first stack, which is an active region, and there is no gate conductor layer around the second stack. At this time, the gate conductor layer 1017 and the gate dielectric layer 1015 form a gate stack. The gate stack may serve as a gate contact.

Then, as shown in fig. 12, an interlayer dielectric layer 1021 may be formed on the structure shown in fig. 11. Specifically, for example, an oxide may be deposited and planarized such as CMP to form an interlayer dielectric layer 1021, and the interlayer dielectric layer 1021 is planarized to be flush with the top surfaces of the hard mask layers 1031-1, 1031-2.

Then, in fig. 13, the hard mask layers 1031-1, 1031-2 may be selectively etched to form first and second recesses T1, T2 in the interlayer dielectric layer 1021. Then, as shown in fig. 14, a contact metal may be deposited on top and planarized, e.g., CMP, to the top surface of the interlayer dielectric layer 1021, thereby forming self-aligned first and second metal contacts 1023-1 and 1023-2 in the first and second grooves T1 and T2, where each of the first and second metal contacts 1023-1 and 1023-2 may comprise the metals Cu, Co, W, Ru, combinations thereof, and the like.

As shown in fig. 14, the first metal contact 1023-1 is aligned with a source/drain region (which is formed by the first semiconductor layer 1005-1) above the first channel layer 1003-1, specifically, the outer circumference of the first metal contact 1023-1 is substantially aligned with the outer circumference of the first semiconductor layer 1005-1, and further, the outer circumference of the first metal contact 1023-1 is substantially coincident with the outer circumference of the first semiconductor layer 1005-1. Also, the first metal contact 1023-1 may serve as a contact of the source/drain region (which is formed by the first semiconductor layer 1005-1). The second metal contact 1023-2 and the conductive second stack are vertically aligned with each other and may together serve as a contact to a source/drain region (formed from a portion of the substrate 1001) below the first channel layer 1003-1. As previously mentioned, the conductive second stack may comprise a low resistance semiconductor material, in particular, may comprise a doped semiconductor material such as doped silicon and doped germanium and/or a metal semiconductor compound material. The metal-semiconductor compound material includes a metal silicide material and/or a metal silicide-germanide material. Obviously, according to the aforementioned embodiments, the conductive second stack may also be entirely of a metal semiconductor compound material. And second metal contact 1023-2 may comprise the same material as first metal contact 1023-1.

Thus, fig. 14 illustrates a vertical semiconductor device in accordance with an embodiment of the present invention in which conductive contacts with high aspect ratios are formed using self-aligned metal contacts and conductive stacked pillars, thereby increasing integration density and reducing the difficulty of forming contacts (avoiding the process difficulty of, for example, etching contact holes using plasma etching and refilling the contact holes with a material such as metal). The mask steps are also reduced, thereby reducing manufacturing costs.

Fig. 15 to 21 show schematic views of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Since the first half of the flow of manufacturing a semiconductor device according to another embodiment of the present disclosure is the same as the first half of the flow of manufacturing a semiconductor device of the foregoing embodiment (see the relevant description parts of fig. 1 to 9 in particular), for the sake of brevity, no further description is given here.

As shown in fig. 15, on the structure of fig. 9, the gate conductor layer 1017 is subjected to etching such as RIE, so that the gate conductor layer 1017 is etched not higher than and preferably lower than the top surface of the channel layers 1003-1, 1003-2. Oxide spacers are then formed on sidewalls of the first stack and the second stack.

As shown in fig. 16, a diffusion barrier layer and a contact metal layer may be sequentially formed over the structure shown in fig. 15. Specifically, a diffusion barrier layer 1043 is first conformally deposited over the structure shown in fig. 15, the diffusion barrier layer 1043 may comprise a metal comprising TiN, TaN, or Ti, etc., with a thickness of 1 to 10 nm. A contact metal layer 1045 is then conformally deposited over the diffusion barrier layer 1043, the contact metal layer 1045 may comprise the metals Cu, Co, W, Ru, combinations thereof, and the like, and the contact metal layer 1045 has a thickness of 5-20 nm.

Next, the contact metal layer, such as RIE, may be selectively etched, the diffusion barrier layer may be etched, the oxide spacers may be etched, and the gate conductor layer, such as RIE, may be selectively etched in sequence. This may be done, for example, as follows. Specifically, as shown in fig. 17, 18(a) and 18(b) (fig. 18(a) is a sectional view, fig. 18(b) is a top view, in which an AA 'line shows a position where the section is taken out), a photoresist may be formed on the contact metal layer 1045, and the photoresist 1019' may be patterned by photolithography to expose a portion where a contact hole is to be formed. Then, with the patterned photoresist 1203 as a mask, selective etching such as RIE is sequentially performed on the contact metal layer 1045, the diffusion barrier layer 1043 is selectively etched, the oxide barrier is selectively etched, and the gate conductor layer 1017 is selectively etched such as RIE. Here, the etching may stop on the gate dielectric layer 1015 and the hard mask layers 1031-1, 1031-2 on the upper surface of the substrate 1001. Here, the gate conductor layer 1017 is etched away except for a portion remaining within the recess and a portion blocked by the photoresist 1019'. The contact metal layer 1045, the diffusion barrier layer 1043, and the remaining portions of the oxide partition walls except for the portions blocked by the photoresist 1019' are etched away. Another embodiment is to perform a selective etching, such as RIE, on the contact metal layer 1045, stop on the diffusion barrier layer 1043, perform a selective etching (such as RIE, selectively leave the metal isolation wall formed by the contact metal layer 1045) on the diffusion barrier layer 1043 and the gate conductor layer 1017, and then perform an etching with the photoresist 1019' shielding, and only the metal isolation wall portion where the upper metal contact is to be formed is remained. The metal side wall comprises metals Cu, Co, W, Ru and the like.

Then, as shown in fig. 19, an interlayer dielectric layer 1021 may be formed on the structure shown in fig. 11. Specifically, for example, the photoresist shown in fig. 11 may be removed, then the thin dielectric layer 1047 conformally deposited, and portions of the thin dielectric layer 1047 above the top surfaces of the hard mask layers 1031-1, 1031-2 selectively etched away. The thin dielectric layer 1047 may serve as a protective and/or diffusion barrier and may comprise a nitride material with a thickness of 2 to 20 nm. An oxide is then deposited and planarized, such as CMP, to form an inter-level dielectric layer 1021, and the inter-level dielectric layer 1021 is planarized to be flush with the top surfaces of the hard mask layers 1031-1, 1031-2. The interlayer dielectric layer 1021 is 40 to 200nm thick.

Then, as shown in fig. 20, a first groove T1, a second groove T2, and a third groove T3 may be formed on the structure shown in fig. 19. Specifically, the hard mask layers 1031-1, 1031-2 and the thin dielectric layer 1047 formed of a nitride material and the contact metal layer 1045 and the diffusion barrier layer 1043 made of a metal material may be selectively etched to the same depth as RIE to form the first, second, and third recesses T1, T2, and T3 in the interlayer dielectric layer 1021

Then, as shown in fig. 21, a contact metal may be deposited over and planarized, e.g., CMP, to the top surface of the inter-layer dielectric layer 1021, thereby forming self-aligned first 1023-1, second 1023-2, and third 1023-3 metal contacts in the first and second grooves T1 and T2, each of the first 1023-1, second 1023-2, and third 1023-3 metal contacts may comprise Cu, Co, W, Ru, combinations thereof, and the like.

The first metal contact 1023-1 may serve as a contact for the source/drain region (which is formed by the first semiconductor layer 1005-1). The second metal contacts 1023-2 and the conductive second stack are vertically aligned with each other and may together serve as contacts to source/drain regions (formed from a portion of the substrate 1001) below the first channel layer 1003-1. The third metal portion 1023-3 may function as a gate contact portion together with the contact metal layer 1045, the diffusion barrier layer 1043, and the gate conductor layer 1017 located thereunder. First metal contact 1023-1, second metal contact 1023-2, and third metal contact 1023-3 may be formed using the same material.

Thus, fig. 21 shows a vertical type semiconductor device according to another embodiment of the present invention. It differs from the previous embodiment in that the gate contact is formed using the third metal contact 1023-3, rather than using only the gate conductor layer 1017.

In a further embodiment, in order to increase the conductivity, i.e. to reduce the contact resistance of each contact, a process step of forming a conductive metal is added to the aforementioned process. Specifically, fig. 22 to 29 are schematic diagrams showing a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Since the first half of the flow of manufacturing a semiconductor device according to another embodiment of the present disclosure is the same as the first half of the flow of manufacturing a semiconductor device of the foregoing embodiment (see the relevant description part of fig. 1 to 7(a) or 7(b), in particular), for the sake of brevity, no further description is repeated here.

As shown in fig. 22, a metal layer material comprising W, Co or Ru is deposited on the structure shown in fig. 7 (a). A barrier/STI oxide etch stop layer (not shown) is then deposited as desired. The metal layer material is patterned using photoresist 1042 and the metal not covered by photoresist 1042 is etched away, thereby forming a patterned metal layer 1041. Metal layer 1041 serves as a metal line or a metal contact.

In fig. 23, similarly to the step shown in fig. 8, the photoresist is removed, an oxide is deposited over the substrate 1001 and the shallow trench isolation layer 1033, and is etched back to the position of the interface between the channel layers 1003-1 and 1003-2 and the substrate 1001 (i.e., the interface between the SiGe layer and the Si layer) to form a second isolation layer 1013. The deposited oxide may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP) or sputtering prior to etch back.

In fig. 24(a), similarly to the step shown in fig. 9, a gate dielectric layer and a gate conductor layer may be formed in the recess. Specifically, as shown in fig. 24(a), the sacrificial gate 1007 may be removed on the structure shown in fig. 23, a gate dielectric layer 1015 and a gate conductor layer 1017 may be sequentially deposited, and the deposited gate conductor layer 1017 may be etched back to be flush with the top surfaces of the hard mask layers 1031-1 and 1031-2. At the same time remove the metalThe portion of layer 1041 above the hard mask layer 1031-2. For example, the gate dielectric layer 1015 may include a high-K gate dielectric such as HfO₂(ii) a The gate conductor layer 1017 may comprise a metal gate conductor. In addition, between the gate dielectric layer 1015 and the gate conductor layer 1017, a work function adjusting layer may be further formed, and the function adjusting layer may include a threshold voltage Vt adjusting metal. An interfacial layer, such as an oxide, may also be formed prior to forming the gate dielectric layer 1015.

In fig. 24(b), on the basis of the structure shown in fig. 24(a), further etching is performed to recess the nitride and metal layer 1041, and then nitride is deposited to form a nitride cap layer 1031-2 (in conformity with the hard mask layer 1031-2 material, which may also be referred to as a hard mask layer 1031-2), whereby electrical isolation is better achieved.

In fig. 25, similar to the steps shown in fig. 10, the gate conductor layer may be patterned to form a gate stack, and specifically, as shown in fig. 25, a photoresist may be coated on the structure shown in fig. 24(b), the photoresist may be patterned to form a photoresist layer 1039, and then the gate conductor layer 1017 may be selectively etched, such as RIE, with the photoresist 1039 as a mask. Thus, the remaining portion of the gate conductor layer 1017, except for the portion remaining within the recess and the portion shielded by the photoresist 1019, is etched to no higher than and preferably lower than the top surface of the channel layers 1003-1, 1003-2.

Then, as shown in fig. 26, the photoresist layer 1039 is removed, the photoresist is coated again, and the photoresist is patterned to form a photoresist layer 1019, and then selective etching such as RIE is performed again on the remaining gate conductor layer 1017 with the photoresist layer 1019 as a mask. Thus, the gate conductor layer 1017 is etched away except for the portion remaining within the recess and the portion blocked by the photoresist 1039. Thus, the gate conductor layer is formed only around the first stack, which is an active region, and there is no gate conductor layer around the second stack. At this time, the gate conductor layer 1017 and the gate dielectric layer 1015 form a gate stack. The gate stack may serve as a gate contact.

Then, as shown in fig. 27, an interlayer dielectric layer 1021 may be formed on the structure shown in fig. 26. Specifically, for example, an oxide may be deposited and planarized such as CMP to form an interlayer dielectric layer 1021, and the interlayer dielectric layer 1021 is planarized to be flush with the top surfaces of the hard mask layers 1031-1, 1031-2.

Then, in fig. 28, the hard mask layers 1031-1, 1031-2 may be selectively etched to form first and second recesses T1, T2 in the interlayer dielectric layer 1021. Then, as shown in fig. 29, a contact metal may be deposited over and planarized, e.g., CMP, to the top surface of the interlayer dielectric layer 1021, thereby forming self-aligned first and second metal contacts 1023-1 and 1023-2 in the first and second grooves T1 and T2. Due to the pre-formed metal layer 1041 in the second groove, better conductive contact of the second contact portion is facilitated, and conductivity is increased.

The semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices as well as other devices (e.g., other forms of transistors, etc.), an Integrated Circuit (IC) may be formed, and an electronic apparatus constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device. The electronic device may also include components such as a display screen that cooperates with the integrated circuit and a wireless transceiver that cooperates with the integrated circuit. Such as smart phones, computers, tablet computers (PCs), artificial intelligence, wearable devices, mobile power supplies, and the like.

According to an embodiment of the present disclosure, there is also provided a method of manufacturing a system on chip (SoC). The method may include the above-described method of manufacturing a semiconductor device. In particular, a variety of devices may be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the above-described method. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a substrate;

the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction;

a gate stack formed around a periphery of the channel region;

a first contact to the second source/drain region over the second source/drain region, wherein a first contact periphery is aligned with a second source/drain region periphery;

wherein the first contact is self-aligned to the second source/drain region;

wherein the first source/drain region includes a laterally extending portion that extends beyond a portion of the active region above it,

the semiconductor device further includes: a second contact to the first source/drain region over the laterally extending portion of the first source/drain region,

wherein the second contact portion includes a first portion and a second portion which are sequentially stacked on the substrate and are aligned with each other in a vertical direction,

wherein the first portion comprises a low resistance semiconductor material and/or a metal semiconductor compound.

2. The semiconductor device of claim 1,

the outer periphery of the first contact part is overlapped with the outer periphery of the second source/drain region; or

The semiconductor device further includes a metal semiconductor compound layer formed on a surface of the second source/drain region, wherein an outer periphery of the first contact portion coincides with an outer periphery of the metal semiconductor compound layer formed on the surface of the second source/drain region.

3. The semiconductor device of claim 1, wherein the first contact and/or the second contact comprise a metal Cu, Co, W, Ru, and combinations thereof.

4. The semiconductor device of claim 1,

the second portion of the second contact includes the same material as the first contact and has the same thickness in the vertical direction as the first contact, and the first portion of the second contact includes a semiconductor material and/or a metal-semiconductor compound material.

5. The semiconductor device of claim 4,

the first portion of the second contact comprises at least partially the same element in the semiconductor material as a portion of the semiconductor element in the first or second source/drain region.

6. The semiconductor device of claim 1, the second contact further comprising a metal layer surrounding a periphery of the first portion and the second portion.

7. The semiconductor device of claim 6, wherein the metal layer surrounding the outer perimeter of the first and second portions of the second contact comprises a metal Cu, Co, W, Ru, or a combination of any of the foregoing.

8. The semiconductor device of claim 1, further comprising:

a third contact to a gate conductor layer in the gate stack.

9. The semiconductor device of claim 8,

the third contact is integral with the gate conductor layer; or

The third contact portion includes the same material as the first contact portion.

10. A semiconductor device, comprising:

a substrate;

a gate stack formed around a periphery of the channel region;

a spacer formed over the gate stack and on a sidewall of the active region;

self-aligned metal contacts are formed over the gate stacks and on the sidewall of the isolation walls.

11. The semiconductor device of claim 10, further comprising a third contact formed over the self-aligned metal contact that is self-aligned to the self-aligned metal contact.

12. The semiconductor device of claim 11, further comprising a diffusion barrier layer conformally formed over the gate stack and on sidewalls of the isolation walls;

a metal contact layer formed conformally over the diffusion barrier layer;

a thin dielectric layer conformally formed on the sidewalls of the metal contact layer;

a self-aligned metal contact formed from the diffusion barrier layer and the metal contact layer;

a third contact formed on the self-aligned metal contact and self-aligned to the self-aligned metal contact.

13. The semiconductor device of claim 10 or 11, wherein the self-aligned metal contact and/or the third contact comprise the metals Cu, Co, W, Ru, and combinations of any of them.

14. A method of manufacturing a semiconductor device, comprising:

a source region material layer is arranged on the substrate;

providing a hard mask layer on the active area material layer, the hard mask layer including a first portion for defining an active area;

patterning the active region material layer with the hard mask layer as a mask to define a vertical active region;

forming an interlayer dielectric layer on the substrate, and carrying out planarization treatment on the interlayer dielectric layer to expose the hard mask layer;

selectively etching the hard mask layer to remove the hard mask layer, thereby leaving a first trench in the inter-level dielectric layer corresponding to the vertical active region;

filling the first groove with conductive material, and forming a first contact part by self-alignment

Wherein the hard mask layer further comprises a second portion separate from the first portion,

while patterning the active area material layer, the patterning of the active area material layer is stopped before proceeding to the bottom surface of the active area material layer, whereupon the active area material layer is patterned into a first stack corresponding to a first portion of the hard mask layer, which serves as an active area, and a second stack corresponding to a second portion of the hard mask layer, and the first stack and the second stack are connected together at the bottom,

after selectively etching the hard mask layer, a second trench corresponding to the second stack is left in the interlayer dielectric layer,

when the first groove is filled with the conductive material, the conductive material is also filled into the second groove, thereby forming the second contact portion.

15. The method of claim 14, further comprising:

forming a barrier layer at the periphery of a portion of the first stack where a channel region is to be formed;

forming a dopant source layer on a surface of the first stack and the second stack;

dopants in the dopant source layer are driven into the lower and upper end portions of the first stack to form first and second source/drain regions, respectively, and into the entire second stack.

16. The method of claim 15, further comprising:

a metal-semiconductor compound layer is formed on a surface of the first stack and the second stack in the presence of the barrier layer.

17. The method of claim 15, wherein,

the active region material layer comprises a first source/drain layer, a channel layer and a second source/drain layer which are sequentially stacked,

forming the barrier layer includes:

selectively etching the channel layer such that an outer periphery of the channel layer is recessed with respect to outer peripheries of the first and second source/drain layers;

the barrier layer is formed in a recess formed in an outer periphery of the channel layer with respect to outer peripheries of the first and second source/drain layers.

18. The method of any of claims 14 to 16, further comprising:

forming an isolation layer on a substrate, the isolation layer exposing a portion of the active region that serves as a channel region;

a gate stack is formed on the isolation layer around an outer periphery of a portion of the active region that serves as a channel region.

19. The method of claim 17, further comprising:

20. The method of claim 19, wherein forming a gate stack comprises:

removing the barrier layer;

sequentially forming a gate dielectric layer and a gate conductor layer on the isolation layer;

planarizing the gate conductor layer to expose the hard mask layer;

covering a portion of the gate conductor layer with a first masking layer separate from the first stack;

etching back the gate conductor layer in the presence of the first masking layer such that a top surface of the etched-back portion of the gate conductor layer is lower than a top surface of the channel layer;

covering a portion of the gate conductor layer with a second masking layer overlapping the first stack, wherein the second masking layer completely covers the portion of the gate conductor layer covered by the first masking layer;

the gate conductor layer is etched back in the presence of the second masking layer, wherein the etching back is performed to a bottom surface of the gate conductor layer.

21. The method of claim 19, wherein forming a gate stack comprises:

removing the barrier layer;

etching back the gate conductor layer so that the top surface of the portion of the gate conductor layer outside the recess is lower than the top surface of the channel layer;

forming dielectric side walls on the side walls of the first stack and the second stack;

forming a conductive material layer;

covering a portion of the layer of conductive material with a masking layer that overlaps the first stack;

the layer of conductive material and the gate conductor layer are etched back in the presence of the masking layer, wherein the etching back is performed to a bottom surface of the gate conductor layer.

22. The method of claim 21, wherein,

upon selective etching of the hard mask layer, the layer of conductive material is also removed, leaving a third trench in the inter-level dielectric layer,

when the first groove is filled with the conductive material, the conductive material is also filled in the third groove, thereby forming a third contact portion.

23. An electronic device comprising an integrated circuit formed by the semiconductor device according to any one of claims 1 to 13.

24. The electronic device of claim 23, further comprising: a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.

25. The electronic device of claim 24, comprising a smartphone, a computer, a tablet, an artificial intelligence, a wearable device, or a mobile power source.