CN111710716A - Fin-shaped semiconductor device, manufacturing method thereof and electronic equipment - Google Patents
Fin-shaped semiconductor device, manufacturing method thereof and electronic equipment Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a fin-shaped semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The fin-shaped semiconductor device includes: the field effect transistor structure comprises a substrate and a fin type field effect transistor formed on the substrate; the fin field effect transistor comprises a source drain region and a channel layer connected with the source drain region; the fin field effect transistor further comprises an isolation layer formed between the substrate and the source drain region; wherein the isolation layer is formed by selective oxidation treatment. The manufacturing method of the fin-shaped semiconductor device is used for manufacturing the fin-shaped semiconductor device provided by the technical scheme. The fin-shaped semiconductor device provided by the invention is applied to electronic equipment.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fin-shaped semiconductor device, a manufacturing method of the fin-shaped semiconductor device and electronic equipment.
Background
A Fin Field-Effect Transistor (FinFET) can improve the driving performance of a device by using a channel material with higher mobility, but the problem of leakage of a source/drain region is always one of the bottlenecks in improving the performance of a high-mobility channel FinFET three-dimensional device. Currently, most of them use SOI (Silicon-On-Insulator, Silicon On Insulator) substrate or punch-through barrier layer implantation process to suppress leakage in the source and drain regions. However, the cost of the SOI substrate is high, the punch-through barrier layer injection process is easily influenced by factors such as injection depth, source and drain etching depth and the like, and the process control difficulty is high.
Disclosure of Invention
The invention aims to provide a fin-shaped semiconductor device, a manufacturing method thereof and electronic equipment.
In a first aspect, the present invention provides a fin-shaped semiconductor device comprising: the field effect transistor comprises a substrate and a fin type field effect transistor formed on the substrate;
the fin field effect transistor comprises a source drain region and a channel layer connected with the source drain region;
the fin field effect transistor further comprises an isolation layer formed between the substrate and the source drain region; wherein the isolation layer is formed by selective oxidation treatment.
In a second aspect, the present invention provides a method for manufacturing a fin-shaped semiconductor device, including the steps of:
providing a substrate;
forming a fin field effect transistor on a substrate; the fin field effect transistor comprises a source drain region and a channel layer connected with the source drain region; the fin field effect transistor further comprises an isolation layer formed between the substrate and the source drain region; wherein the isolation layer is formed by selective oxidation treatment.
In a third aspect, the present invention provides an electronic device including the fin-shaped semiconductor device provided in the above technical solution.
Compared with the prior art, the fin-shaped semiconductor device provided by the invention has the advantages that the isolation layer is formed between the substrate and the source drain region. The isolation layer is formed by selective oxidation treatment, so the isolation layer is an oxide isolation layer. The oxide isolation layer is non-conductive, so the oxide isolation layer can inhibit leakage of electricity in the source and drain regions, and the electrical performance of the semiconductor device is improved. The isolation layer is obtained by partially oxidizing a film layer formed on a substrate, and can reduce the cost to a certain extent as compared with an SOI substrate. Moreover, the isolation layer can be obtained only by carrying out partial oxidation treatment on the film layer formed on the substrate, and compared with a punch-through barrier layer injection process, the process is simple, and the process difficulty is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a fin-shaped semiconductor device according to the present invention;
FIG. 2 is a schematic structural diagram of a substrate according to the present invention;
FIG. 3 is a schematic diagram illustrating a structure of the present invention after forming an oxidation assistant material layer and a channel material layer on a substrate;
FIG. 4 is a schematic diagram illustrating a structure of a substrate, a layer of oxidation assist material, and a layer of channel material after a first patterning process;
FIG. 5 is a schematic diagram of a structure after shallow trench isolation is formed according to the present invention;
FIG. 6 is a schematic structural diagram of a dummy gate material layer formed on a front channel layer according to the present invention;
fig. 7 is a schematic structural diagram of a dummy gate material layer and a front channel layer after a second patterning process is performed thereon according to the present invention;
FIG. 8 is a schematic structural diagram of a spacer layer formed according to the present invention;
FIG. 9 is a schematic structural diagram of a source/drain region formed on an isolation layer according to the present invention;
FIG. 10 is a schematic view of a structure of the present invention with dummy gates removed;
fig. 11 is a schematic structural diagram of a gate stack structure formed according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The problem of leakage of the source and drain regions has been one of the bottlenecks in improving the performance of the FinFET three-dimensional device. In the prior art, the source-drain leakage problem generally adopts the following two modes:
(1) when the semiconductor device is manufactured, the silicon-on-insulator substrate is selected as the substrate of the semiconductor device, and at the moment, structures such as a source region, a drain region and the like in the semiconductor device are formed on a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is a non-conductive insulating layer, so that the problem of electric leakage of a parasitic channel and a source drain can be solved.
(2) In the process of manufacturing the semiconductor device, after the fin-shaped structure formed by the semiconductor material layer is formed, the fin-shaped structure is subjected to punch-through preventing injection treatment so as to form a punch-through blocking layer at the bottom of the fin-shaped structure. The source region, the drain region, a future channel and other structures in the semiconductor device are formed on the punch-through blocking layer, and because impurities with high concentration and the types opposite to those of the impurities in the source region and the drain region are injected into the punch-through blocking layer, leakage current can be isolated through a PN junction with reverse bias, so that parasitic channel and source-drain leakage are inhibited.
Although both of the above two methods can solve the problem of parasitic channel and source-drain leakage, the first solution has a high manufacturing cost of the semiconductor device due to the high cost of the conventional silicon-on-insulator substrate. When the second method is adopted, the punch-through prevention implantation may cause the impurity concentration distribution of each region in the channel region to be uneven in the process of forming the punch-through blocking layer. For example: impurities in the punch-through barrier layer are affected by subsequent high-temperature annealing and diffuse into the channel region, so that the mobility of carriers in the channel region is degraded, and the driving performance of the semiconductor device is reduced.
In order to solve the above technical problems, embodiments of the present invention provide a fin-shaped semiconductor device, a method for manufacturing the same, and an electronic device. In the fin-shaped semiconductor device provided by the embodiment of the invention, an isolation layer is formed between the substrate and the source and drain regions. The existence of the isolation layer can solve the problem of electric leakage of the source and drain regions. In addition, the isolation layer is a film layer formed on the substrate, and a silicon-on-insulator substrate with higher cost is not needed, so that the manufacturing cost of the semiconductor device is reduced. Moreover, the isolation layer can be obtained only by carrying out partial oxidation treatment on the film layer formed on the substrate, and compared with a punch-through barrier layer injection process, the process is simple, and the process difficulty is reduced.
Referring to fig. 1, fig. 1 shows a schematic structural diagram of a fin-shaped semiconductor device according to an embodiment of the present invention. The fin-shaped semiconductor device includes a substrate 10 and a fin field effect transistor formed on the substrate 10. The finfet includes source and drain regions 70 and a channel layer 40 connected to the source and drain regions 70. The finfet further includes an isolation layer 30 formed between the substrate 10 and the source and drain regions 70. The isolation layer 30 is formed by selective oxidation. In order to realize the functionality of the fin-shaped semiconductor device, the fin-shaped semiconductor device further includes a gate stack structure 501 formed at the periphery of the channel layer 40, and a sidewall 502 formed at the periphery of the gate stack structure 501.
Referring to fig. 1, the source-drain regions 70 illustratively include a source region 701 formed on one side of the channel layer and a drain region 702 formed on the other side of the channel layer 40. The isolation layer 30 includes a first isolation layer 301 formed between the substrate 10 and the source region 701, and a second isolation layer 302 formed between the substrate 10 and the drain region 702. In the embodiment of the present invention, in order to avoid leakage and parasitic capacitance caused by junction depth variation, the top of the first isolation layer 301 may be flush with the top of the second isolation layer 302.
Referring to fig. 1, for example, in order to reduce the manufacturing cost of the fin-shaped semiconductor device, the substrate 10 may be a semiconductor substrate with low cost such as a silicon substrate or a silicon germanium substrate. In the case of a fin-shaped semiconductor device for isolating active regions, a Shallow Trench Isolation (STI) 60 is formed on a substrate 10 of the semiconductor device. The shallow trench isolation 60 may be made of SiN or Si3N4、SiO2Or an insulating material such as SiCO.
Referring to fig. 1, the isolation layer 30 is formed by a selective oxidation process to solve the leakage problem of the source/drain region 70. The isolation layer 30 is formed by selectively oxidizing the auxiliary layer to be oxidized, and therefore the material of the isolation layer 30 is determined by the material of the auxiliary layer to be oxidized. The material of the auxiliary layer to be oxidized is the same as that of the auxiliary layer 20, and after the selective oxidation treatment is performed on the predetermined region of the auxiliary layer to be oxidized, the auxiliary layer 20 is formed on the non-oxidized region. For example, when oxidation assist layer 20 is a silicon germanium oxidation assist layer, isolation layer 30 can be one or more of a silicon oxide isolation layer, a silicon germanium oxide isolation layer, or a germanium oxide isolation layer.
Referring to fig. 1, in order to satisfy the performance of the device, when the oxidation auxiliary layer 20 is a sige oxidation auxiliary layer, the mass percentage of the germanium element in the sige oxidation auxiliary layer is 30% to 80%. Illustratively, the channel layer 40 is a silicon channel or a silicon germanium channel layer. When the channel layer 40 is a germanium-silicon channel layer, the mass percentage of germanium element in the germanium-silicon channel layer is greater than 0% and less than or equal to 50%.
Illustratively, in fabricating the fin-shaped semiconductor device, the sige oxidation auxiliary layer and the sige channel layer may be provided with a sufficient oxidation selectivity in order to avoid excessive oxidation of the channel layer during formation of the isolation layer 30. At this time, the difference between the mass percentage of the germanium element in the sige oxidation auxiliary layer and the mass percentage of the germanium element in the sige channel layer may be set to be greater than or equal to 30%.
Referring to fig. 1, when the oxidation auxiliary layer 20 is a sige oxidation auxiliary layer, the oxidation auxiliary layer is suppressedThe parasitic channel can also be selectively doped with the SiGe auxiliary oxide layer in an in-situ doping manner or an ion implantation manner, wherein the type of the doped ions is opposite to that of the source/drain regions, and the concentration of the doped ions is 1 × 1017cm-3-5×1018cm-3。
Illustratively, the doping ions may also be selected according to the type of device when doping the sige-si oxide auxiliary layer. For example, when the fin-shaped semiconductor device is N-type, the doped ions may be B. For another example, when the fin-shaped semiconductor device is P-type, the doped ions may be one or both of P and As.
Referring to fig. 1, the above-described oxidation assist layer 20 is formed on a substrate 10, a channel layer 40 is formed on a first region 201 of the oxidation assist layer 20, and an isolation layer 30 is formed on a second region 202 of the oxidation assist layer 20. The specific formation of the isolation layer 30 is as follows: and carrying out oxidation treatment on the preset area of the auxiliary layer to be oxidized by adopting a selective oxidation mode to obtain the isolation layer 30. The selective oxidation treatment mode can be a furnace tube oxidation mode or a rapid thermal treatment mode. The oxidizing atmosphere of the selective oxidation treatment is oxygen, nitrogen or an atmosphere containing ozone. The temperature and time of the different oxidation treatment modes can be defined differently. For example: when the oxidation treatment mode is a furnace tube oxidation mode, the temperature of the furnace tube oxidation mode is 500-850 ℃, and the time is 10-60 min. For another example, when the oxidation treatment is rapid thermal treatment at a temperature of 600 ℃ to 850 ℃, the treatment cycle is 1 to 10 cycles, and the treatment time per cycle is 30s to 60 s.
Referring to fig. 1, for example, in order to achieve isolation of source drain regions 70, the isolation layer 30 needs to have a certain thickness, but too thick isolation layer 30 may affect the performance of the device. Based on this, the embodiment of the present invention sets the thickness of the isolation layer 30 to be in the range of 5nm to 50 nm. To further balance the isolation effect and the device performance, the thickness of the isolation layer 30 may be set in the range of 10nm to 20 nm.
Referring to fig. 1, it can be understood that in order to obtain the above-mentioned thickness of the isolation layer 30, it is necessary to provide the auxiliary layer to be oxidized with a certain thickness, i.e., the thickness of the auxiliary layer to be oxidized is at least equal to or greater than the thickness of the isolation layer 30. The thickness of the auxiliary layer to be oxidized is, for example, 5nm to 50nm, which is the same as that of the above-mentioned spacer layer. At this time, since the isolation layer 30 is obtained by performing selective oxidation treatment on a predetermined region of the auxiliary layer to be oxidized, and the first region of the auxiliary layer to be oxidized is a region of the auxiliary layer to be oxidized which is not subjected to the selective oxidation treatment, the thickness of the first region 201 of the auxiliary layer 20 to be oxidized may be 5nm to 50 nm.
Referring to fig. 1, when the isolation layer 30 is formed and the auxiliary layer to be oxidized is subjected to oxidation treatment, a predetermined region of the auxiliary layer to be oxidized may be partially or entirely oxidized in a thickness direction. For example, when the thickness of the isolation layer to be oxidized is larger, the predetermined region of the auxiliary layer to be oxidized may be selected to be partially oxidized in the thickness direction. At this time, the predetermined region of the auxiliary oxide layer has a certain thickness after the isolation layer 30 is formed. The thickness may be greater than 0nm and equal to or less than 45 nm. The non-oxidized part of the predetermined area forms a second area 202 of the oxidation assistance layer 20, at which time the isolation layer 30 is formed on the second area 20 of the oxidation assistance layer 20. For another example, when the thickness of the isolation layer to be oxidized is small, in order to satisfy the isolation effect of the isolation layer 30, the predetermined region 202 of the auxiliary layer to be oxidized may be selected to be completely oxidized along the thickness direction, and the isolation layer 30 is directly formed on the substrate 10.
The embodiment of the invention also provides a manufacturing method of the fin-shaped semiconductor device. Referring to fig. 2 to 11, the method of fabricating the fin-shaped semiconductor device includes the steps of:
referring to fig. 2, step S1, a substrate 10 is provided. The substrate 10 may be a silicon substrate, a silicon germanium substrate, or an inexpensive semiconductor substrate.
Referring to fig. 3, step S2, an oxidation assistant material layer 21 is formed on the substrate. Specifically, the oxidation auxiliary material layer 21 may be formed in an epitaxial manner. For example, in order to suppress the parasitic channel leakage, the oxidation auxiliary material layer 21 may be doped in situ or ion implantedSelecting doped ions according to the type of the fin-shaped semiconductor device, wherein the concentration of the doped ions is 1 × 1017cm-3-5×1018cm-3。
As a possible implementation manner, in the case of doping the oxidation auxiliary material layer 21 in an in-situ doping manner, in order to simplify the manufacturing process of the semiconductor, the oxidation auxiliary material layer 21 and the channel material layer 41 may be formed by simultaneous epitaxy.
In an embodiment of the invention, the oxidation auxiliary material layer 21 is a sige oxidation auxiliary material layer, and in order to adapt to the performance of the fin-shaped semiconductor device, the mass percentage of the germanium element in the sige oxidation auxiliary material layer is greater than or equal to 30% and less than or equal to 80%.
Referring to fig. 3, in step S3, a channel material layer 41 is formed on the oxidation assistant material layer 21. Channel material layer 41 may be a silicon channel material layer or a silicon germanium channel material layer. Illustratively, the germanium element of the germanium-silicon channel material layer is greater than 0% and less than or equal to 50% by mass. In order to satisfy the selective oxidation ratio when the isolation layer is formed subsequently, the difference between the mass percentage of the germanium element in the germanium-silicon channel material layer and the mass percentage of the germanium element in the germanium-silicon oxidation auxiliary material layer is set to be more than 30%.
It is understood that a protective layer may be further epitaxially grown on the silicon germanium channel material layer in order to protect the silicon germanium channel layer. The protective layer may be made of silicon.
In step S4, the substrate, the oxidation assistant material layer, and the channel material layer are patterned. Illustratively, referring to fig. 4 to 7, the patterning of the oxidation assisting material layer and the stacked material layer includes the following sub-steps:
s41, referring to fig. 4, a first patterning process is performed on the substrate 10, the oxidation-assisting material layer 21, and the channel material layer 41 to obtain a fin structure, wherein the fin structure includes, from bottom to top, a fin 101 formed by etching a portion of the substrate 10, a to-be-assisted oxide layer 22 formed by etching a portion of the oxidation-assisting material layer 21, and a front channel layer 42 formed by etching a portion of the channel material layer 41. Where 102 in fig. 4 is the base of the substrate.
As a possible implementation manner, referring to fig. 5, after step S41, the method for manufacturing a semiconductor further includes forming shallow trench isolations 60 on both sides of the fin 101 and the auxiliary layer 22 to be oxidized of the substrate 10, where the shallow trench isolations 60 are used for isolating active regions of the fin-shaped semiconductor device.
S42, referring to fig. 6, a dummy gate 50 and a sidewall 502 are formed on the outer periphery of the front channel layer 42. For example, the dummy gate 50 may be made of silicon in order to meet the etching selectivity of the subsequent fabrication process.
S43, referring to fig. 7, a second patterning process is performed by using the dummy gate 50 and the sidewall spacers 502 as a pattern, so as to obtain the channel layer 40 formed on the auxiliary layer 22 to be oxidized.
For example, the first patterning process may be to cover a hard mask on the channel material layer 41, and etch the hard mask according to a preset scheme by using photolithography and etching processes to form a hard mask pattern. And etching the substrate, the oxidation auxiliary material layer and the channel material layer based on the hard mask pattern to form the fin-shaped structure. The second patterning process may be to etch the front channel layer based on the mask pattern by using the dummy gate 50 and the sidewall 502 as masks, so as to form a channel layer.
S5, referring to fig. 8, selectively oxidizing the predetermined region of the auxiliary layer 22 to be oxidized to obtain the isolation layer 30. The predetermined region of the auxiliary layer 22 to be oxidized is a region of the auxiliary layer 22 to be oxidized where no channel layer is formed.
As a possible implementation manner, when the auxiliary layer to be oxidized 22 is a sige auxiliary layer to be oxidized, and the channel layer is a sige channel layer, the difference between the mass percentage of the ge element in the sige auxiliary layer to be oxidized and the mass percentage of the ge element in the channel layer is greater than a preset threshold, so that the sige auxiliary layer to be oxidized and the sige channel layer have a larger oxidation selection ratio. Wherein the preset threshold may be 30%. With the above arrangement, the channel layer is not excessively oxidized when the auxiliary layer to be oxidized 22 is selectively oxidized.
Referring to fig. 8, a selective oxidation process is performed on a predetermined region of the auxiliary layer 22 to be oxidized, so as to obtain the isolation layer 30 and the oxidation auxiliary layer 20 (including the first region 201 and the second region 202). The selective oxidation treatment mode can be a furnace tube oxidation mode or a rapid thermal treatment mode. The oxidizing atmosphere of the selective oxidation treatment is oxygen, nitrogen or an atmosphere containing ozone. The temperature and time of the different oxidation treatment modes can be defined differently. For example: when the oxidation treatment mode is a furnace tube oxidation mode, the temperature of the furnace tube oxidation mode is 500-850 ℃, and the time is 10-60 min. For another example, when the oxidation treatment is rapid thermal treatment at a temperature of 600 ℃ to 850 ℃, for 1 to 10 cycles, the time for each cycle is 30s to 60 s.
The specific values of the oxidation parameters (temperature and time) in the embodiment of the present invention may be determined according to the germanium element in the oxidation auxiliary layer, and the selective oxidation treatment may perform the selective oxidation treatment on the oxidation auxiliary layer at the set oxidation temperature and oxidation time. After the selective oxidation treatment, a thin oxide layer is formed on the channel layer. In order to improve the performance of the device, the oxide layer can be cleaned and removed before the source and drain epitaxy.
Illustratively, in order to achieve isolation of the source and drain regions, the isolation layer needs to have a certain thickness, but too thick isolation layer may affect the performance of the device. Based on this, the embodiments of the present invention set the thickness of the isolation layer to be in the range of 5nm to 50 nm. To further balance the isolation effect and the device performance, the thickness of the isolation layer may be set in the range of 10nm-20 nm.
S6, referring to fig. 9, fig. 9 is a schematic structural diagram of forming a source/drain region on an isolation layer according to an embodiment of the present invention. Source drain regions 70 are a stacked structure, and illustratively, forming source drain regions 70 on isolation layer 30 includes forming a stacked structure of silicon germanium material on isolation layer 30. The germanium-silicon material laminated structure may be three layers or five layers, which is not limited in the embodiment of the present invention. The mass percentages of germanium elements in the germanium-silicon material laminated structure can be the same or different. When the mass percentages of the germanium elements in the stacked structure of the germanium-silicon material are different, the germanium-silicon material may be in the stacked structure of the germanium-silicon material under the condition of considering the degree of lattice matching and the stress. According to the direction from bottom to top, the mass percentage of the germanium element in each germanium-silicon material layer is gradually increased and then gradually decreased.
S7, referring to fig. 10, fig. 10 is a schematic structural diagram of the invention with the dummy gate removed. Illustratively, the dummy gate can be removed by etching. The process of removing the dummy gate in the embodiment of the present invention is the same as the process of removing the sacrificial layer in the conventional method for manufacturing the fin-shaped semiconductor device, and the details of the embodiment of the present invention are not repeated.
S8, referring to fig. 11, fig. 11 is a schematic structural diagram of a gate stack structure formed according to an embodiment of the present invention. As an example, referring to fig. 11, a gate stack structure 501 is formed in the sidewall 502 at the outer periphery of the channel layer 40. Specifically, the gate dielectric layer and the metal gate layer may be sequentially formed on the periphery of the channel layer 40 by Atomic Layer Deposition (ALD), or the like. The gate dielectric layer can be made of HfO2、ZrO2、TiO2Or Al2O3And materials with higher dielectric constants. The metal gate can be made of TiN, TaN or TiSiN and other conductive materials.
The embodiment of the invention also provides electronic equipment which comprises the fin-shaped semiconductor device provided by the embodiment. The electronic device may be a terminal device or a communication device, but is not limited thereto. Further, the terminal device comprises a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligence device, a mobile power supply and the like. The communication device includes a base station and the like, but is not limited thereto.
The advantageous effects of the electronic device provided by the embodiment of the present invention are the same as those of the fin-shaped semiconductor device provided by the above embodiment, and are not described herein again.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (17)
1. A finned semiconductor device, comprising: the field effect transistor structure comprises a substrate and a fin type field effect transistor formed on the substrate;
the fin field effect transistor comprises a source drain region and a channel layer connected with the source drain region;
the semiconductor device further comprises an isolation layer formed between the substrate and the source drain region; wherein the isolation layer is formed by selective oxidation treatment.
2. The finned semiconductor device of claim 1 wherein said source and drain regions comprise a source region formed on one side of said channel layer and a drain region formed on the other side of said channel layer;
the isolation layer comprises a first isolation layer formed between the substrate and the source region and a second isolation layer formed between the substrate and the drain region, and the top of the first isolation layer is flush with the top of the second isolation layer.
3. The fin-shaped semiconductor device according to claim 1, further comprising an oxidation assist layer formed on the substrate, the channel layer being formed on a first region of the oxidation assist layer, the isolation layer being formed on a second region of the oxidation assist layer.
4. The fin-shaped semiconductor device of claim 3, wherein the oxidation assist layer is a silicon germanium oxidation assist layer;
the mass percentage of germanium element in the germanium-silicon oxidation auxiliary layer is 30-80%.
5. The fin-shaped semiconductor device of claim 4, wherein the channel layer is a silicon channel layer or a silicon germanium channel layer;
the mass percentage of germanium element in the germanium-silicon channel layer is more than 0% and less than or equal to 50%, and the difference between the mass percentage of germanium element in the germanium-silicon oxidation auxiliary layer and the mass percentage of germanium element in the germanium-silicon channel layer is more than or equal to 30%.
6. The fin-shaped semiconductor device of claim 3, wherein the SiGe oxidation auxiliary layer contains dopant ions at a concentration of 1 × 1017cm-3-5×1018cm-3。
7. The finned semiconductor device of claim 3 wherein the thickness of the first region is 5nm-50 nm;
and/or the thickness of the second region is 0nm-45 nm.
8. The fin-shaped semiconductor device of any one of claims 1-7, further comprising a gate stack structure formed at a periphery of the channel layer.
9. The fin-shaped semiconductor device of any of claims 1-7, wherein the isolation layer is a silicon oxide isolation layer or a silicon germanium oxide isolation layer, the isolation layer having a thickness of 5nm-50 nm.
10. A manufacturing method of a fin-shaped semiconductor device is characterized by comprising the following steps:
providing a substrate;
forming a fin field effect transistor and an isolation layer on the substrate; the fin field effect transistor comprises a source drain region and a channel layer connected with the source drain region; the isolation layer is formed between the substrate and the source drain region; wherein the isolation layer is formed by selective oxidation treatment.
11. The method of fabricating the fin-shaped semiconductor device of claim 10, wherein the forming the fin field effect transistor and the isolation layer on the substrate comprises:
forming an oxidation auxiliary material layer and a channel material layer on the substrate; wherein the oxidation auxiliary material layer is a germanium-silicon oxidation auxiliary material layer;
performing first patterning treatment on the substrate, the oxidation auxiliary material layer and the channel material layer to obtain a fin-shaped structure; the fin-shaped structure comprises a fin part formed by performing first patterning on the substrate, an auxiliary layer to be oxidized formed by performing first patterning on the auxiliary material layer to be oxidized, and a front channel layer formed by performing first patterning on the channel material layer;
carrying out second patterning treatment on the front channel layer to obtain a channel layer;
carrying out selective oxidation treatment on a preset area of the auxiliary layer to be oxidized to obtain an isolation layer and an oxidation auxiliary layer; wherein the channel layer is formed on a first region of the oxidation auxiliary layer, and the isolation layer is formed on a second region of the oxidation auxiliary layer;
and forming a source drain region on the isolation layer.
12. The method of claim 11, wherein the forming the fin field effect transistor and the isolation layer on the substrate further comprises, after the first patterning the substrate, the oxidation assist material layer, and the channel material layer to obtain the fin structure, and before the second patterning the front channel layer to obtain the channel layer, the step of forming the fin field effect transistor and the isolation layer on the substrate further comprises:
and forming a dummy gate and a side wall on the periphery of the front channel layer.
13. The method of fabricating the fin-shaped semiconductor device according to claim 12, wherein the forming the fin field effect transistor on the substrate further comprises, after the selectively oxidizing the predetermined region of the auxiliary layer to be oxidized to obtain an isolation layer and an oxidation auxiliary layer, and before forming a source drain region on the isolation layer:
and removing the oxide layer formed on the side wall of the side wall and the side wall of the channel layer.
14. The method as claimed in claims 10 to 13, wherein the selective oxidation is performed in an oxidizing atmosphere of oxygen, nitrogen or ozone;
and/or the isolating layer is a silicon oxide isolating layer or a germanium silicon oxide isolating layer.
15. The method for manufacturing a fin-shaped semiconductor device according to any one of claims 10 to 13, wherein the selective oxidation treatment is performed by a furnace oxidation method at a temperature of 500 ℃ to 850 ℃ for 10min to 60 min;
or, the selective oxidation treatment adopts rapid thermal treatment, the temperature of the rapid thermal treatment is 600-850 ℃, the rapid thermal treatment comprises 1-10 treatment cycles, and the treatment time of each treatment cycle is 30-60 s.
16. An electronic device comprising the fin-shaped semiconductor device according to any one of claims 1 to 9.
17. The electronic device of claim 16, comprising a communication device or a terminal device.
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| US20130234215A1 (en) * | 2012-03-12 | 2013-09-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US9590038B1 (en) * | 2015-10-23 | 2017-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device having nanowire channel |
| CN107785266A (en) * | 2016-08-26 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor structure |
| US20180233586A1 (en) * | 2012-08-24 | 2018-08-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement with substrate isolation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20130234215A1 (en) * | 2012-03-12 | 2013-09-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20180233586A1 (en) * | 2012-08-24 | 2018-08-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement with substrate isolation |
| US9590038B1 (en) * | 2015-10-23 | 2017-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device having nanowire channel |
| CN107785266A (en) * | 2016-08-26 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor structure |
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