KR102436689B1 - Capacitance reduction for back-side power rail device - Google Patents

Abstract

The semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a backside source/drain contact. The gate structure surrounds the channel structure. A first source/drain epitaxial structure and a second source/drain epitaxial structure are disposed on opposite ends of the channel structure. A gate contact is disposed on the gate structure. The backside source/drain contacts are disposed below the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface in contact with the backside source/drain contacts.

Description

Capacitance REDUCTION FOR BACK-SIDE POWER RAIL DEVICE

This application claims priority to U.S. Provisional Patent Application No. 63/022,666, filed on May 11, 2020, the contents of which are incorporated herein by reference in their entirety.

The semiconductor integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have created generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a manufacturing process) or line)) decreased. This scaling down process generally offers advantages of increasing production efficiency and lowering associated costs. This scaling down also increased the complexity of IC processing and manufacturing.

The semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a backside source/drain contact. The gate structure surrounds the channel structure. A first source/drain epitaxial structure and a second source/drain epitaxial structure are disposed on opposite ends of the channel structure. A gate contact is disposed on the gate structure. The backside source/drain contacts are disposed below the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface in contact with the backside source/drain contacts.

Aspects of the present disclosure are best understood from the following detailed description read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.
1 shows a cross-sectional view of some embodiments of a semiconductor transistor device having a back-side power rail.
2 shows a cross-sectional view of some further embodiments of a semiconductor transistor device having a backside power rail.
3 shows a cross-sectional view of some additional embodiments of a semiconductor transistor device having a backside power rail.
4 shows a cross-sectional view of some further embodiments of a semiconductor transistor device having a backside power rail.
5 shows a cross-sectional view of some embodiments of a semiconductor transistor device having a backside power rail.
6A illustrates a cross-sectional view of some embodiments of a semiconductor transistor device along line A-A' in FIG. 5;
6B shows a cross-sectional view of some embodiments of a semiconductor transistor device along line B-B' of FIG. 5 .
6C illustrates a cross-sectional view of some embodiments of a semiconductor transistor device along line C-C' in FIG. 5 .
7-27B show various views of some embodiments of a method of forming a semiconductor transistor device having a backside power rail at various stages.
Fig. 28 shows a flow diagram of some embodiments of the method corresponding to Figs. 7-27B.

The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific example components and arrangements are described below to simplify the present disclosure. These are, of course, examples only and are not intended to be limiting. For example, in the description below, forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and also the first feature and embodiments in which additional features may be formed between the first and second features such that the second features may not be in direct contact. In addition, this disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for simplicity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

Also, spatially related terms such as “immediately below,” “below,” “below,” “above,” “above,” and the like, refer herein to the relationship of one element or feature to another element(s) or feature(s). It may be used for convenience of description for description as shown in the drawings. These spatially related terms are intended to include various orientations of the device in use or in operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may likewise be interpreted accordingly.

As used herein, “around”, “about”, “approximately” or “substantially” generally means within 20%, or within 10% of a given value or range, or It would mean within 5%. The quantities provided herein are approximations, meaning that the terms “about,” “about,” “approximately,” or “substantially,” can be inferred, unless explicitly stated otherwise.

Gate all around (GAA) transistor structures may be patterned by any suitable method. For example, these structures may be patterned using one or more photolithographic processes including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine a photolithography process with a self-aligned process, which can be otherwise obtained using, for example, a single, direct photolithography process. It is possible to create patterns with smaller pitches than possible. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structures. After forming the GAA transistor structures, an interconnect structure including power rails and signal lines disposed in interlayer dielectric (ILD) layers may be formed over the GAA transistor structures.

Current power rail designs will suffer from complex metal layer routing at the back-end-of-line (BEOL) as semiconductor processes continue to shrink beyond, for example, 3 nm. As a result of complex metal layer routing, more masks are needed, and a voltage drop (sometimes referred to as an IR drop) occurs as the metal wires become thinner.

In this respect, the present disclosure relates to a semiconductor transistor device having a backside power rail and methods of manufacturing the same. Moving the power rails from the front side to the back side of the semiconductor transistor device relieves metal layer routing in the BEOL. Thus, less masks are needed, the IR drop is improved, and both the power rail area and the active area can be enlarged.

More specifically, some embodiments of the present disclosure relate to GAA devices. The GAA device includes a channel structure, a gate structure surrounding the channel structure, first source/drain epitaxial structures and second source/drain epitaxial structures disposed on opposite ends of the channel structure, and a gate contact disposed on the gate structure. includes The GAA device has a back side source/drain contact landing on a recessed bottom surface of the first source/drain epitaxial structure, and a back side source/drain contact disposed below the back side source/drain contact and connected to the back side source/drain contact. It further includes a power rail. The back side source/drain contact and the back side power rail may include, for example, metallic materials. In some embodiments, the bottom surface of the first source/drain epitaxial structure may be recessed to a position that is vertically deeper than the bottom surface of the gate structure or channel structure. Accordingly, cell capacitance may be reduced.

In some embodiments, the backside source/drain contacts are formed to self-align by forming a sacrificial backside contact prior to forming the first source/drain epitaxial structure. The dummy back-side contact is later optionally removed and replaced with a back-side source/drain contact, eliminating the overlay shift of the contact landing.

In some further embodiments, the GAA device further includes a back-side dielectric cap disposed below the gate structure and the second source/drain epitaxial structure. The backside dielectric cap may include oxide, nitride, carbon nitride, or low-k dielectric materials. The backside dielectric cap replaces the original semiconductor body material, thereby reducing cell capacitance, thereby eliminating current leakage problems such as leakage between the gate structure and the backside source/drain contacts.

Additionally, the second source/drain epitaxial structure may have a recessed bottom surface. The bottom surface of the second source/drain epitaxial structure may be recessed into a position vertically aligned with the bottom surface of the gate structure or even deeper than the bottom surface of the gate structure. Accordingly, the cell capacitance can be further reduced.

The GAA devices presented herein include a p-type GAA device or an n-type GAA device. Additionally, GAA devices may have one or more channel regions (eg, semiconductor nanowires, or nanodots, etc.) associated with a single continuous gate structure or multiple gate structures. One of ordinary skill in the art may recognize other examples of semiconductor transistor devices that could benefit from aspects of the present disclosure. GAA devices include static random access memory (SRAM), logic circuits, passive components such as resistors, capacitors, and inductors, and/or active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide semiconductor field effect transistors ( MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. ) may be part of

1 illustrates a cross-sectional view of a semiconductor transistor device 100 in accordance with some embodiments. The semiconductor transistor device 100 includes a channel structure 102 and a gate structure 104 surrounding the channel structure 102 . The channel structure 102 may include a stack of semiconductor layers separated and surrounded by a stack of metal components of the gate structure 104 . A first source/drain epitaxial structure 106 and a second source/drain epitaxial structure 108 are disposed on opposite ends of the channel structure 102 . The inner spacers 128 are disposed on opposite ends of the metal components of the gate structure 104 to isolate the gate structure 104 from the first and second source/drain epitaxial structures 106 , 108 . . In some embodiments, the gate spacers 134 are disposed along opposite sidewalls of the upper portion of the gate structure 104 . The outer surfaces of the inner spacers 128 may be substantially coplanar with the outer surfaces of the channel structure 102 and/or the gate spacers 134 . In some embodiments, the upper isolation structure 220 is disposed in the trenches between the gate spacers 134 . The upper isolation structure 220 provides electrical insulation between the gate structures 104 . As an example, the channel structure 102 may be pure silicon layers that are not doped with p-type and n-type impurities. The thickness of the channel structure 102 may range from about 3 nm to about 15 nm. As an example, the gate structure 104 may include a gate dielectric material, such as high-κ materials (κ is greater than 7), a work function metal material, and a filling metal material, such as tungsten or aluminum. The thickness of the gate structure 104 may range from about 2 nm to about 10 nm. In some embodiments, the first and second source/drain epitaxial structures 106 , 108 include a semiconductor material such as silicon, germanium, or silicon germanium. The first and second source/drain epitaxial structures 106 , 108 may be hexagonal or diamond-shaped shapes. In some embodiments, the first and second source/drain epitaxial structures 106 , 108 have different conductivity types. For example, the first source/drain epitaxial structure 106 may be an N-type epitaxial structure, and the second source/drain epitaxial structure 108 may be a P-type epitaxial structure, or vice versa. have. The first and second source/drain epitaxial structures 106 , 108 may be the source and drain of the semiconductor transistor device 100 , respectively.

On the front side of the semiconductor transistor device 100 , a front side interconnect structure 114 may be disposed over the gate structure 104 and the first and second source/drain epitaxial structures 106 , 108 . The front side interconnect structure 114 may include a plurality of front side metal layers 116 disposed within and surrounded by the front side interlayer dielectric layer 112 . Front side metal layers 116 include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The front side interconnect structure 114 electrically connects various features or structures of the semiconductor transistor device. For example, the gate contact 110 may be disposed on the gate structure 104 and may be connected to external circuits through the front side metal layers 116 .

On the back side of the semiconductor transistor device 100 , in some embodiments, a back side source/drain contact 120 is disposed below the first source/drain epitaxial structure 106 , the first source/drain epitaxial structure ( 106 is connected to a backside power rail 122 disposed below the backside source/drain contacts 120 . In some embodiments, dielectric sidewall spacers 118 are disposed along the sidewalls of the backside source/drain contacts 120 and separate the backside source/drain contacts 120 from the backside dielectric caps 126 . The back side source/drain contact 120 and the back side power rail 122 may include, for example, metallic materials. For example, the back side source/drain contacts 120 may include a metal such as tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable materials. can Accordingly, the first source/drain epitaxial structure 106 may be connected to external circuits from the backside of the semiconductor transistor device 100 through the backside source/drain contacts 120 . Accordingly, more metal routing flexibility is provided and cell capacitance can be reduced.

Further, the backside source/drain contacts 120 may land on the recessed bottom surface 106b of the first source/drain epitaxial structure 106 . In some embodiments, the bottom surface 106b of the first source/drain epitaxial structure 106 may be recessed into a convex shape that reaches a position vertically deeper than the bottom surface 104b of the gate structure 104 . have.

Also on the backside of the semiconductor transistor device 100 , in some embodiments, a backside dielectric cap 126 is disposed below the gate structure 104 . The backside dielectric cap 126 may also extend below the second source/drain epitaxial structure 108 . The backside dielectric cap 126 replaces the original semiconductor body material and helps to isolate and insulate the gate structure 104 and the backside source/drain contacts 120 , thus reducing cell capacitance and the gate structure. Eliminates current leakage problems such as leakage between 104 and the back side source/drain contact 120 . The backside dielectric cap 126 may include oxide, nitride, carbon nitride, or low-k dielectric materials.

2 illustrates a cross-sectional view of a semiconductor transistor device 200 with a backside power rail in accordance with some embodiments. In addition to the features disclosed with reference to FIG. 1 , in some further embodiments, the bottom surface 106b of the first source/drain epitaxial structure 106 vertically exceeds the bottom surface 102b of the channel structure 102 . may be recessed deeper into position. The cell capacitance is further reduced compared to the semiconductor transistor device 100 of FIG. 1 , where the bottom surface 106b of the first source/drain epitaxial structure 106 is below the bottom of the channel structure 102 .

3 illustrates a cross-sectional view of a semiconductor transistor device 300 with a backside power rail in accordance with some embodiments. In addition to the features disclosed with reference to FIGS. 1 and 2 , in some further embodiments, the bottom surface 108b of the second source/drain epitaxial structure 108 is rearwardly the bottom surface 104b of the gate structure 104 . It may be recessed to a position at the same level as , and may have a concave shape as shown in FIGS. 1 and 2 . The cell capacitance can be further reduced compared to the semiconductor transistor devices 100 and 200 of FIGS. 1 and 2 .

4 illustrates a cross-sectional view of a semiconductor transistor device 400 with a backside power rail in accordance with some embodiments. In addition to the features disclosed above, in some further embodiments, the bottom surface 108b of the second source/drain epitaxial structure 108 is recessed to a position vertically deeper than the bottom surface 104b of the gate structure 104 . , and the cell capacitance can be further reduced compared to the semiconductor transistor devices 100 , 200 , and 300 of FIGS. 1 , 2 , and 3 .

5 illustrates a perspective view of the semiconductor transistor device 400 of FIG. 4 in accordance with some embodiments. FIG. 4 may be regarded as a cross-sectional view taken along the x-direction of FIG. 5 . 6A to 6C may be regarded as cross-sectional views along the y-direction in the gate region, the first source/drain region, and the second source/drain region of FIG. 5 , respectively. Alternatively, FIGS. 4-6C , and other figures thereafter, may also be standalone to illustrate various embodiments, and features discussed in relation to one figure may be incorporated into other figures where applicable. .

5-6C , in some embodiments, the lower isolation structure 160 , the intermediate isolation structure 132 , and the hard mask 136 are collectively two semiconductor transistor devices 400a , 400b . ) can function as an insulating structure that separates them along the y-direction. As shown in FIG. 6A , in some embodiments, the gate structure 104 includes a gate dielectric layer 232 and a gate electrode 230 . The gate electrode 230 includes one or more work function metal layer(s) and a filling metal. The gate dielectric layer 232 may be conformally formed to line the outer surfaces of the gate electrode 230 . The gate dielectric layer 232 may contact the underlying isolation structure 160 and the channel structure 102 . In some embodiments, the gate dielectric layer 232 includes hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), hafnium aluminum oxide (HfAlO2), hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), or a high-k material (k greater than 7) such as other suitable materials.

5 and 6C, the first source/drain epitaxial structure 106 has a recessed bottom surface (e.g., convex) and back-side source/drain contacts electrically connected to the recessed bottom surface (e.g., convex). 120) may have. 5 , 6A, and 6B , the second source/drain epitaxial structure 108 has a recessed bottom surface (eg, convex), and a second source/drain epitaxial structure 108 . and a backside dielectric cap 126 disposed directly below the gate structure 104 . The backside dielectric cap 126 may be surrounded by a lower isolation structure 160 . In some embodiments, air gaps 192 may be formed to surround lower portions of the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 .

7-27B illustrate a method of manufacturing a semiconductor transistor device at various stages in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor transistor devices shown in FIGS. 7-27B may be intermediate devices fabricated during processing of an integrated circuit (IC) or portion thereof, the integrated circuit comprising a static random access memory (SRAM), a logic circuit , passive components such as resistors, capacitors, and inductors, and/or active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multiple gates FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

As shown in the perspective view of FIG. 7 , in some embodiments, the stacked structure 150 is formed on the substrate 140 . In some embodiments, the substrate 140 may be part of a wafer and may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or other suitable semiconductor materials. In some embodiments, the substrate 140 is a semiconductor on insulator ( semiconductor-on-insulator (SOI) structures. In various embodiments, substrate 140 may include any of a variety of substrate structures and materials.

The stacked structure 150 includes first semiconductor layers 152 and second semiconductor layers 154 that are alternately stacked. The first semiconductor layers 152 will serve as channel regions of the semiconductor transistor device, and the second semiconductor layers 154 are sacrificial layers to be subsequently removed and replaced with gate material. The first semiconductor layers 152 and the second semiconductor layers 154 are made of materials having different lattice constants, and are Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. may include one or more layers of In some embodiments, first semiconductor layers 152 and second semiconductor layers 154 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. The stacked structure 150 may be formed on the substrate 140 through epitaxy, so that the stacked structure 150 forms crystal layers. 7 shows a first semiconductor layer 152 of four layers and a second semiconductor layer 154 of three layers, the number of these layers is not so limited and may be as small as one for each layer. . In some embodiments, 2 to 10 layers are formed for each of the first and second semiconductor layers. By adjusting the number of stacked layers, it is possible to adjust the drive current of the semiconductor transistor device.

In some embodiments, the first semiconductor layers 152 may be pure silicon layers free of germanium. The first semiconductor layers 152 may also be substantially pure silicon layers, for example, having an atomic percent germanium of less than about 1%. Furthermore, the first semiconductor layers 152 may be intrinsic layers that are not doped with p-type and n-type impurities. In some embodiments, the thickness of the first semiconductor layers 152 is in the range of about 3 nm to about 15 nm.

In some embodiments, the second semiconductor layers 154 may be SiGe layers having a germanium atomic percentage greater than zero. In some embodiments, the germanium percentage of the second semiconductor layers 154 is in a range from about 10 percent to about 50 percent. In some embodiments, the thickness of the second semiconductor layers 154 is in the range of about 2 nm to about 10 nm.

As shown in the perspective view of FIG. 8 , in some embodiments, the stacked structure 150 is patterned to form fin structures 156 and trenches 158 extending in the X direction (see FIG. 7 ). In some embodiments, the stacked structure 150 is patterned by an etching process using the patterned mask layer 157 as an etching mask, and thus the stacked structure 150 is not covered by the patterned mask layer 157 . parts of the are removed. The semiconductor substrate layer 146 may be partially or completely removed during this process. The mask layer 157 may include a first mask layer and a second mask layer. The first mask layer may be a pad oxide layer made of silicon oxide, which may be formed by thermal oxidation. The second mask layer is a chemical vapor deposition (CVD), physical vapor deposition, including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD). silicon nitride (SiN) formed by (PVD), atomic layer deposition (ALD), or other suitable process. Mask layer 157 may be patterned using a variety of multiple patterning techniques. Although FIG. 8 shows two fin structures 156 arranged in the Y direction and parallel to each other, the number of the fin structures is not limited thereto, and may be as small as one and may be three or more. In some embodiments, one or more dummy fin structures are formed on either side of the fin structure 156 to improve pattern fidelity in patterning operations.

As shown in the perspective view of FIG. 9 , in some embodiments, an underlying isolation structure 160 is formed over the insulator substrate layer 144 in lower portions of the trenches 158 , which also provides shallow trench isolation. Also referred to as a trench isolation (STI) structure. Upper portions of the fin structures 156 are exposed from the lower isolation structure 160 . The lower isolation structure 160 may be formed by forming an insulating material over the insulator substrate layer 144 followed by a planarization operation. The insulating material is then recessed to form the lower isolation structure 160 , thereby exposing upper portions of the fin structures 156 . The insulating material may be, for example, a nitride (eg, silicon nitride, silicon oxynitride, silicon oxygen carbon nitride, silicon carbon nitride), a carbide (eg, silicon carbide, silicon oxygen carbide), an oxide (eg, silicon oxide), boro borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low-κ dielectric materials with a dielectric constant less than 7 (e.g., carbon doped oxide, SiCOH), etc. In some embodiments, the underlying isolation structure 160 may be formed by a thermal oxidation or deposition process (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), PECVD, It is formed through atomic layer deposition (ALD), sputtering, etc.), and removal processes (eg, wet etching, dry etching, chemical mechanical planarization (CMP), etc.).

As shown in the perspective view of FIG. 10 , in some embodiments, a cladding semiconductor layer 161 is formed over outer surfaces of the fin structures 156 . In some embodiments, the cladding semiconductor layer 161 includes a semiconductor material such as germanium, silicon germanium, or the like. In some embodiments, the cladding semiconductor layer 161 includes the same material as the second semiconductor layers 154 . Further, in some embodiments, the cladding semiconductor layer 161 may be formed by an epitaxial growth process or a deposition process (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.).

As shown in the perspective view of FIG. 11 , in some embodiments, an intermediate isolation structure 132 is formed over the lower isolation structure 160 between the fin structures 156 . The dielectric liner 130 may be formed between the intermediate isolation structure 132 and the lower isolation structure 160 along sidewalls of the cladding semiconductor layer 161 and the lower isolation structure 160 . A hard mask 136 may then be formed on top of the intermediate isolation structure 132 and the dielectric liner 130 . The intermediate isolation structure 132 and the dielectric liner 130 provide electrical insulation between the fin structures 156 and the hard mask 136 prevents loss of the intermediate isolation structure 132 during subsequent patterning steps. .

In some embodiments, dielectric liner 130 , intermediate isolation structure 132 , and hard mask 136 are deposited (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.) and removed (eg, etched, chemically mechanical planarization (CMP), etc.) processes. The intermediate isolation structure 132 may have a lower top surface than the top surface of the fin structures 156 . In some embodiments not shown in FIG. 11 , the planarization process of the hard mask 136 may also remove the overlying cladding semiconductor layer 161 from the fin structures 156 . The hard mask 136 may have a top surface that is coplanar with a top surface of the fin structures 156 . In some embodiments, the dielectric liner 130, the intermediate isolation structure 132, and the lower isolation structure 160 are each formed of a low-k dielectric material having a dielectric constant of less than 7, e.g., silicon oxynitride, silicon carbon nitride, silicon oxycarbide, silicon oxycarbon nitride, silicon nitride, or some other suitable low-k dielectric material. The dielectric liner 130 may include a different material than the intermediate isolation structure 132 for selective removal processes. The hard mask 136 is formed of a high-k dielectric material having a dielectric constant greater than 7, for example, hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, or some other suitable high-κ dielectric material. may include

12 , in some embodiments, the hard mask 136 is selectively removed from the top of the fin structures 156 . Top surfaces of the first semiconductor layer 152 and the cladding semiconductor layer 161 may be exposed from the removal process. In some embodiments, the hard mask 136 is selectively etched by, for example, a dry etching process and/or a wet etching process.

As shown in the perspective view of FIG. 13 , in some embodiments, the dummy gate structures 170 are formed along the y-direction spaced apart from each other in the x-direction on the fin structures 156 . In some embodiments, dummy gate structures 170 may include a sacrificial gate dielectric layer 162 , a sacrificial gate electrode layer 164 , a pad layer 166 , and a mask layer 168 , each layer is stacked on top of the other layers in the specified order. Although two dummy gate structures 170 are illustrated in FIG. 13 , the number of dummy gate structures 170 is not limited thereto, and may be more or less than two. In some embodiments, the sacrificial gate dielectric layer 162 is, for example, a dielectric material such as a nitride (eg, silicon nitride, silicon oxynitride), a carbide (eg, silicon carbide), an oxide (eg, silicon) oxide), or some other suitable material. The sacrificial gate electrode layer 164 may include, for example, polysilicon. Pad layer 166 and mask layer 168 may include thermal oxide, nitride, and/or other hard mask materials, and are formed by photolithography processes.

Next, gate spacers 134 are formed along opposite sidewalls of the dummy gate structures 170 . For example, a blanket layer of insulating material for sidewall spacers can be made using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), etc. Thus, it is conformally formed to cover the dummy gate structures. Since the blanket layer is deposited in a conformal manner, it is formed to have substantially the same thickness at the top, horizontal surfaces, and vertical surfaces, such as sidewalls of the dummy gate structures 170 . In some embodiments, the insulating material of the blanket layer may include a silicon nitride based material. The blanket layer is then etched using an anisotropic process to form gate spacers 134 on opposite sidewalls of the dummy gate structures 170 .

As shown in the perspective view of FIG. 14A in the gate region, the cross-sectional view in the x-direction of FIG. 14B, the cross-sectional view in the y direction of FIG. 14C, and the cross-sectional view in the y direction of FIG. 14D in the source or drain region, in some embodiments, a dummy gate A removal process for removing the fin structures 156 from the first source/drain region 176 and the second source/drain region 178 is performed according to the structures 170 . As a result, the first semiconductor layers 152 and the second semiconductor layers 154 may be shortened along the x direction and vertically aligned with the gate spacers 134 . As an example, exposed portions of the fin structures 156 are removed using a strained source/drain (SSD) etch process. The SSD etching process may be performed in a variety of ways. In some embodiments, the SSD etching process may be performed by dry chemical etching using a plasma source and a reactive gas. The plasma source is an inductively coupled plasma (ICR) etch, a transformer coupled plasma (TCP) etch, an electron cyclotron resonance (ECR) etch, a reactive ion etch ) (RIE), and the like, and the reactive gas may be a fluorine-based gas, chloride (Cl2), hydrogen bromide (HBr), oxygen (O2), etc., or combinations thereof. In some other embodiments, the SSD etching process comprises ammonium peroxide mixture (APM), ammonium hydroxide (NHOH), tetramethylammonium hydroxide (TMAH), these may be performed by wet chemical etching, such as combinations of In some other embodiments, the SSD etching step may be performed by a combination of dry chemical etching and wet chemical etching. Further, in some embodiments, the removal process may also remove an upper portion of the semiconductor substrate layer 146 between the dummy gate structures 170 after removing the lowermost first semiconductor layer 152 . The semiconductor substrate layer 146 or the lowermost first semiconductor layer 152 may have a top surface concave along the x-direction in the first source/drain region 176 and the second source/drain region 178 . The top surface may be recessed between the lower isolation structures 160 .

Further, the removal process may also include an isotropic etchant to further remove the end portions of the second semiconductor layers 154 under the gate spacers 134 and/or the dummy gate structures 170 . Accordingly, after the removal process, the first semiconductor layers 152 are wider than the second semiconductor layers 154 in the x direction. The first semiconductor layers 152 may be formed as a channel structure of the transistor device after the removal process. It will be appreciated that the channel structure may exhibit a stacked rectangular shape as shown in the cross-sectional views of FIG. 14B and other figures, while in other embodiments the channel structure may exhibit other shapes such as circles, octagons, ellipses, diamonds, and the like. will be.

As shown in the perspective view of FIG. 15A and the cross-sectional view in the x-direction of FIG. 15B , in some embodiments, the inner spacers 128 are on the ends of the second semiconductor layers 154 in the x-direction having outermost sidewalls. is formed The outermost sidewalls of the inner spacers 128 may be substantially coplanar with the outer surfaces of the first semiconductor layers 152 and/or the gate spacers 134 . In some embodiments, the inner spacers 128 are formed by a deposition process (eg, CVD, PVD, PE-CVD, ALD, sputtering, etc.), followed by a selective removal process (eg, etching). For example, in some embodiments, a continuous layer may first be formed over the dummy gate structures 170 along sidewalls. A vertical etch process may then be performed to remove portions of the continuous layer not vertically covered by gate spacers 134 to form inner spacers 128 . Further, in some embodiments, the inner spacers 128 may be formed of a low-κ dielectric material (ie, a dielectric constant less than 7), such as silicon oxynitride, silicon carbon nitride, silicon oxycarbide, silicon oxycarbon nitride, silicon nitride, or some other suitable material.

As shown in the perspective view of FIG. 16A, the cross-sectional view in the x-direction of FIG. 16B, and the cross-sectional view in the y-direction of FIG. 16C in the first source/drain region, in some embodiments, the first sacrificial source/drain contact 180 is A hard mask layer 182 is formed under the first source/drain region 176 and covers the second source/drain region 178 . In some embodiments, the trenches are formed by first etching a portion of the first semiconductor layer 152 and/or the semiconductor substrate layer 146 directly below the first source/drain regions 176 . A sacrificial material is then filled into the trenches to form first sacrificial source/drain contacts 180 . In some embodiments, the first sacrificial source/drain contact 180 may include a SiGe material having an atomic percentage germanium greater than zero. In some embodiments, the germanium percentage of the first sacrificial source/drain contact 180 is in a range from about 10 percent to about 50 percent. In some embodiments, the first sacrificial source/drain contact 180 includes the same material as the second semiconductor layers 154 . Further, in some embodiments, the first sacrificial source/drain contact 180 may be formed by an epitaxial growth process or a deposition process (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.). By forming the first sacrificial source/drain contacts 180 in the trench and therein, the source/drain contacts may later be formed to self-align to replace the first sacrificial source/drain contacts 180, thus overlaying the contact landings. The shift is removed.

As shown in the perspective view of FIG. 17A in the first source/drain region, the cross-sectional view in the x-direction of FIG. 17B, and the cross-sectional view in the y direction of FIG. 17C, and the cross-sectional view in the y-direction of FIG. 17D in the second source/drain region, some In an embodiment, the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 are formed on opposite sides of the dummy gate structure 170 (see FIG. 17B ). In some embodiments, the first and second source/drain epitaxial structures 106 , 108 may be in direct contact with ends of the first semiconductor layer 152 . A first source/drain epitaxial structure 106 may be formed on the first sacrificial source/drain contact 180 (see FIG. 17C ). The second source/drain epitaxial structure 108 may be formed on the lowermost first semiconductor layer 152 or the semiconductor substrate layer 146 (see FIG. 17D ). The first and second source/drain epitaxial structures 106 and 108 may be the source and drain of a semiconductor transistor device, respectively. In some embodiments, the first and second source/drain epitaxial structures 106 , 108 include a semiconductor material. In some embodiments, the first and second source/drain epitaxial structures 106 , 108 may include silicon, germanium, or silicon germanium. In some embodiments, the first and second source/drain epitaxial structures 106 , 108 are formed by an epitaxial growth process. The first and second source/drain epitaxial structures 106 , 108 may be hexagonal or diamond-shaped shapes. Air gaps 192 may be formed to surround lower portions of the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 .

As shown in the perspective view of FIG. 18A in the first source/drain region, the cross-sectional view in the x-direction of FIG. 18B, and the cross-sectional view in the y direction of FIG. 18C, and the cross-sectional view in the y direction of FIG. 18D in the second source/drain region, some In an embodiment, the upper isolation structure 220 is formed over the previously formed structure to cover the first and second source/drain epitaxial structures 106 , 108 . A planarization process is then performed to lower the gate spacers 134 and expose the sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164 on the same horizontal plane. Although not shown in the figure, an etch stop liner may be conformally formed to line the previously formed structure prior to forming the upper isolation structure 220 . The etch stop liner may have a tensile stress and may be formed of Si3N4. In some other embodiments, the etch stop liner includes materials such as oxynitrides. In some other embodiments, the etch stop liner may have a composite structure comprising a plurality of layers, such as a silicon nitride layer overlying a silicon oxide layer. The etch stop liner may be formed using plasma enhanced CVD (PECVD), although other suitable methods may also be used, such as low pressure CVD (LPCVD), atomic layer deposition (ALD), and the like. The upper isolation structure 220 may be formed by chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable methods. In some embodiments, upper isolation structure 220 includes silicon oxide. In some other embodiments, the upper isolation structure 220 comprises silicon oxynitride, silicon nitride, compounds comprising Si, O, C and/or H (e.g., silicon oxide, SiCOH and SiOC), a low-κ material, or organic materials (eg, polymers). The planarization operation may include a chemical-mechanical planarization (CMP) process.

As shown in the perspective view of FIG. 19A , the x-direction cross-sectional view of FIG. 19B , and the y-direction cross-sectional view of FIG. 19C in the gate region, in some embodiments, a replacement gate process is performed to form the gate structure 104 . The sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164 are removed to expose the first and second semiconductor layers 152 , 154 . The upper isolation structure 220 protects the first and second source/drain epitaxial structures 106 , 108 during the removal of the sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164 . The sacrificial gate electrode layer 164 may be removed using plasma dry etching and/or wet etching. When the sacrificial gate electrode layer 164 is polysilicon and the upper isolation structure 220 is silicon oxide, a wet etchant such as a TMAH solution may be used to selectively remove the sacrificial gate electrode layer 164 . The sacrificial gate electrode layer 164 may be removed using plasma dry etching and/or wet etching. Thereafter, the sacrificial gate dielectric layer 162 is also removed. Accordingly, the first and second semiconductor layers 152 and 154 are exposed.

Thereafter, the second semiconductor layers 154 and the cladding semiconductor layer 161 (see FIG. 14C ) are applied to the second semiconductor layers 154 and the cladding semiconductor layer at a faster etch rate than etching the first semiconductor layers 152 . 161 is removed or etched using an etchant capable of selectively etching 161 . Since the inner spacers 128 are made of a material having an etch selectivity with respect to the material of the second semiconductor layers 154 and the cladding semiconductor layer 161 , the inner spacers 128 are formed from the second semiconductor layers 154 and Protects the first and second source/drain epitaxial structures 106 , 108 from the etchant used to etch the cladding semiconductor layer 161 .

Gate structure 104 is then formed and/or filled between gate spacers 134 and inner spacers 128 . That is, the gate structure 104 surrounds (or surrounds or surrounds) the first semiconductor layers 152 , where the first semiconductor layers 152 are referred to as channels of the semiconductor transistor device. Gate spacers 134 are disposed on opposite sides of the gate structure 104 . The gate structure 104 includes a gate dielectric layer 232 and a gate electrode 230 . The gate electrode 230 includes one or more work function metal layer(s) and a filling metal. The gate dielectric layer 232 may be conformally formed. That is, the gate dielectric layer 232 is in contact with the lower isolation structure 160 and the first semiconductor layers 152 . In some embodiments, the gate dielectric layer 232 includes hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), hafnium aluminum oxide (HfAlO2), hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), or a high-k material (k greater than 7) such as other suitable materials. In various embodiments, the gate dielectric layer 232 may be formed by performing an ALD process or other suitable process.

A workfunction metal layer of the gate electrode 230 is formed on the gate dielectric layer 232 , which in some embodiments surrounds the first semiconductor layers 152 . The work function metal layer may be formed of materials such as titanium nitride (TiN), tantalum (TaN), titanium aluminum silicon (TiAlSi), titanium silicon nitride (TiSiN), titanium aluminum (TiAl), tantalum aluminum (TaAl), or Other suitable materials may be included. In some embodiments, the work function metal layer may be formed by performing an ALD process or other suitable process. The filling metal of the gate electrode 230 fills the remaining space between the gate spacers 134 and between the inner spacers 128 . That is, the work function metal layer(s) is between and in contact with the gate dielectric layer 232 and the fill metal. The filling metal may include a material such as tungsten or aluminum. After deposition of gate dielectric layer 232 and gate electrode 230 , a planarization process, such as a CMP process, is performed to remove excess portions of gate dielectric layer 232 and gate electrode 230 to form gate structure 104 . can do.

In some embodiments, an interfacial layer (not shown) is optionally formed prior to forming the gate structure 104 , such that the exposed surfaces of the first semiconductor layers 152 and the exposed surface of the semiconductor substrate layer 146 are surround them In various embodiments, the interfacial layer may comprise a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may include chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods.

As shown in the perspective view of FIG. 20 , in some embodiments, a front side interconnect structure 114 is formed over the gate structure 104 and the first and second source/drain epitaxial structures 106 , 108 . . The front side interconnect structure 114 may include a plurality of front side metal layers 116 disposed within and surrounded by the front side interlayer dielectric layer 112 . The front side interconnect structure 114 electrically connects various features or structures (eg, gate contact 110 and/or other contacts) of the semiconductor transistor device. Front side metal layers 116 include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnect features may implement various conductive materials including copper, tungsten and silicide. In some examples, a damascene process is used to form a copper multi-layer interconnect structure. A carrier substrate 240 is then formed over the front side interconnect structure 114 . For example, the carrier substrate 240 is bonded to the front side interconnect structure 114 . In some embodiments, the carrier substrate 240 is sapphire. In some other embodiments, carrier substrate 240 is silicon, a thermoplastic polymer, oxide, carbide, or other suitable material.

As shown in the perspective view of FIG. 21 , in some embodiments, the workpiece is “flipped” upside down to expose the first sacrificial source/drain contact 180 and the semiconductor substrate layer 146 from the back side and thinned out. thinned. At least a top portion of the bulk substrate 142 , the insulator substrate layer 144 , and the underlying isolation structure 160 is removed. The bulk substrate 142 and the lower isolation structure 160 may be formed in a plurality of process operations, for example, first removing the bulk substrate 142 and subsequently removing the lower isolation structure 160 . can be removed. In some embodiments, the removal processes include removing the bulk substrate 142 and underlying isolation structure 160 using, for example, CMP, HNA, and/or TMAH etching.

As shown in the perspective view of FIG. 22A , the cross-sectional view in the x-direction of FIG. 22B, and the cross-sectional view in the y-direction of FIG. 22C in the first source/drain region, in some embodiments, the first sacrificial source/drain contact 180 is removed. and a backside source/drain contact trench 234 with the underlying first source/drain epitaxial structure 106 recessed from its backside side and recessed into an upper portion of the first source/drain epitaxial structure 106 . ) to form The first source/drain epitaxial structure 106 is recessed using an etchant capable of selectively etching the first source/drain epitaxial structure 106 at an etch rate that is faster than etching the surrounding dielectric materials. or can be etched.

As shown in the perspective view of FIG. 23A , the cross-sectional view in the x-direction of FIG. 23B, and the cross-sectional view in the y-direction of FIG. 23C in the first source/drain region, in some embodiments, the second sacrificial source/drain contact 236 is Filled in side source/drain contact trench 234 . In some embodiments, the second sacrificial source/drain contact 236 is formed by depositing a dielectric material such as silicon nitride within the backside source/drain contact trench 234 and then removing the excess portions by a subsequent planarization process. Thus, the second sacrificial source/drain contact 236 may be coplanar with the underlying isolation structure 160 and the semiconductor substrate layer 146 .

As shown in the perspective view of FIG. 24A , the cross-sectional view in the x-direction of FIG. 24B, and the cross-sectional view in the y-direction of FIG. 24C in the second source/drain region, in some embodiments, the semiconductor substrate layer 146 includes the second source/drain It is removed to form backside capping trenches 238 over the epitaxial structure 108 and the gate structure 104 . The lower second source/drain epitaxial structure 108 and the gate structure 104 may be exposed. In some embodiments, the second source/drain epitaxial structure 108 is recessed from the back side, and the back side capping trench 238 is formed in an upper portion of the second source/drain epitaxial structure 108 .

As shown in the perspective view of FIG. 25A in the gate region, the cross-sectional view in the x-direction of FIG. 25B, and the cross-sectional view in the y direction of FIG. 25C, and the cross-sectional view in the y direction of FIG. 25D in the second source/drain region, in some embodiments: A backside dielectric cap 126 is formed in the backside capping trenches 238 (see FIG. 24A ). A backside dielectric cap 126 may be formed directly over the second source/drain epitaxial structure 108 and the gate structure 104 . The backside dielectric cap 126 is formed by, for example, a deposition process that deposits dielectric material within the backside capping trenches 238 , followed by a CMP process to remove excess dielectric material outside the backside capping trenches 238 . It can be formed by a process. In some embodiments, the backside dielectric cap 126 includes a different dielectric material than the second sacrificial source/drain contact 236 , eg, silicon oxide. Other applicable materials may include SiO2, SiN, SiCN, SiOCN, Al2O3, AlON, ZrO2, HfO2, or combinations thereof, and the like. In some embodiments, the backside dielectric cap 126 has a convex top surface 126s at the interface between the backside dielectric cap 126 and the second source/drain epitaxial structure 108 .

As shown in the perspective view of FIG. 26A, the cross-sectional view in the x-direction of FIG. 26B, and the cross-sectional view in the y-direction of FIG. 26C in a first source/drain region, in some embodiments, the back-side source/drain contact 120 is the back-side Formed in at least a portion of the source/drain contact trench 234 to replace the second sacrificial source/drain contact 236 (see FIG. 23A ). In some embodiments, an outer portion of the second sacrificial source/drain contact 236 remains in the backside source/drain contact trench 234 as a dielectric sidewall spacer 118 so that the backside source/drain cap 126 is removed from the backside source in some embodiments. / Disconnect the drain contact 120 . The backside source/drain contacts 120 will reach on the recessed bottom surface 106b of the first source/drain epitaxial structure 106 . The bottom surface 106b may be recessed during the previous steps, for example, as shown in FIGS. 22A-22C . In some embodiments, prior to forming the backside source/drain contacts 120 , a backside metal alloy layer may be formed on the first source/drain epitaxial structure 106 . The back side metal alloy layer may be silicide layers formed by a self-aligned salicide process. The backside metal alloy layer may include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel platinum silicide, erbium silicide, palladium silicide, combinations thereof, or other suitable materials. In some embodiments, the back side metal alloy layer may include germanium. In some embodiments, the backside source/drain contacts 120 may be made of a metal such as W, Co, Ru, Al, Cu, or other suitable materials. After deposition of the backside source/drain contacts 120 , a planarization process such as a chemical mechanical planarization (CMP) process may be performed. In some embodiments, a barrier layer may be formed in the backside source/drain contact trench 234 prior to formation of the backside source/drain contact 120 . The barrier layer may be made of TiN, TaN, or combinations thereof.

As shown in the perspective view of FIG. 27A and the cross-sectional view in the x-direction of FIG. 27B , in some embodiments, the backside power rail 122 and the backside interconnect structure 124 are electrically connected to the backside source/drain contacts 120 . formed to be connected to

28 shows a flow diagram of some embodiments of a method 2800 of forming an integrated chip having multi-transistor devices with high device density due to air spacer structures and high-κ dielectric spacer structures.

Although method 2800 is illustrated and described below as a series of acts or events, it will be understood that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some acts may occur in a different order and/or concurrently with other acts or events other than those illustrated and/or described herein. Additionally, not all illustrated acts may be required to implement one or more aspects or embodiments herein. In addition, one or more acts depicted herein may be performed in one or more separate acts and/or steps.

In operation 2802 , a plurality of fin structures of the stacked first and second semiconductor layers are formed on the substrate. Isolation structures are formed between the fin structures (see, eg, FIGS. 7-12 ). 7-12 show perspective views of some embodiments corresponding to operation 2802 .

In operation 2804 , a plurality of dummy gate structures are formed over the fin structures. 13 shows a perspective view of some embodiments corresponding to operation 2804 .

In an operation 2806 , portions of the fin structures not covered by the dummy gate structures are etched and removed from opposite sides of the dummy gate structure. The second semiconductor layers are horizontally recessed from the first semiconductor layers. 14A-14C show various views of some embodiments corresponding to operation 2806.

In operation 2808 , inner spacers are formed on opposite ends of the second semiconductor layers. 15A and 15B show various views of some embodiments corresponding to operation 2808 .

At operation 2810 , a first dummy backside contact is formed in the substrate. 16A-16C show various views of some embodiments corresponding to act 2810 .

In operation 2812 , first and second source/drain epitaxial structures are formed on opposite sides of the recessed fin structure. 17A-17D show various views of some embodiments corresponding to act 2812 .

In operation 2814 , the second semiconductor layers are replaced with a metal gate structure. 18A-19C show various views of some embodiments corresponding to act 2814 .

In operation 2816, the gate contact and front side interconnect structures are formed. 20 shows a perspective view of some embodiments corresponding to act 2816 .

At operation 2818 , the bottom surface of the first source/drain epitaxial structure is recessed. 21-22C show various views of some embodiments corresponding to act 2818 .

In an operation 2820 , a second dummy backside contact is formed that reaches the recessed bottom surface of the first source/drain epitaxial structure. 23A-23C show various views of some embodiments corresponding to operation 2820 .

At operation 2822 , the bottom surface of the second source/drain epitaxial structure is recessed. 24A-24D show various views of some embodiments corresponding to act 2822 .

In operation 2824 , a backside dielectric cap is formed on the bottom surface of the second source/drain epitaxial structure. 25A-25D show various views of some embodiments corresponding to act 2824 .

In operation 2826 , a backside source/drain contact is formed that reaches the bottom surface of the first source/drain epitaxial structure. 26A-26C show various views of some embodiments corresponding to act 2826 .

At operation 2828 , the backside power rail and backside interconnect structure are formed. 27A and 27B show various views of some embodiments corresponding to act 2828 .

Accordingly, in some embodiments, the present disclosure relates to a semiconductor transistor device. A semiconductor transistor device includes a channel structure and a gate structure surrounding the channel structure. The semiconductor transistor device includes a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure, and a backside source disposed below the first source/drain epitaxial structure. /Includes more drain contacts. The first source/drain epitaxial structure has a concave bottom surface in contact with the backside source/drain contacts. The semiconductor transistor device further includes a gate contact disposed on the gate structure.

In another embodiment, the present disclosure relates to a semiconductor transistor device. A semiconductor transistor device includes a channel structure and a gate structure surrounding the channel structure. A semiconductor transistor device includes a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure, and a first source/drain epitaxial structure disposed below the first source/drain epitaxial structure. It further includes a backside source/drain contact in contact with the source/drain epitaxial structure. A semiconductor transistor device has a gate contact disposed on the gate structure, and a back side disposed below the second source/drain epitaxial structure and the gate structure and in contact with the second source/drain epitaxial structure and the gate structure. It further includes a dielectric cap.

In yet another embodiment, the present disclosure relates to a method of manufacturing a semiconductor transistor device. The method includes forming a fin structure over a substrate by alternately stacking first semiconductor layers and second semiconductor layers, and forming a dummy gate structure over the fin structure. The method further includes removing a portion of the fin structure not covered by the dummy gate structure and forming inner spacers on opposite sides of remaining portions of the first semiconductor layers. The method further includes forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin structure. The method further includes replacing the dummy gate structure and the first semiconductor layers with a metal gate structure. The method further includes removing the substrate and forming a backside capping trench to expose bottom surfaces of the metal gate structure and a bottom surface of the second source/drain epitaxial structure. A bottom surface of the second source/drain epitaxial structure is recessed. The method includes forming a backside dielectric cap within the backside capping trench and forming a backside source/drain contact below the first source/drain epitaxial structure and in contact with the first source/drain epitaxial structure. further comprising steps.

The foregoing has outlined features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. A person skilled in the art can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same effects as the embodiments introduced herein. you have to understand Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure. do.

Example

Embodiment 1. A semiconductor transistor device comprising:

channel structures;

a gate structure surrounding the channel structure;

a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure;

a gate contact disposed on the gate structure; and

a back-side source/drain contact disposed below the first source/drain epitaxial structure;

and the first source/drain epitaxial structure has a concave bottom surface in contact with the backside source/drain contact.

Example 2. The method of Example 1,

and a backside dielectric cap disposed below the second source/drain epitaxial structure and in direct contact with the second source/drain epitaxial structure.

Example 3. The method of Example 2,

and the second source/drain epitaxial structure has a concave bottom surface in contact with the backside dielectric cap.

Example 4. The method of Example 2,

and the backside dielectric cap extends below the gate structure.

Example 5. The method of Example 4,

and the backside dielectric cap is in direct contact with the gate structure.

Example 6. The method of Example 2,

and an intermediate isolation structure surrounding the gate structure, the first source/drain epitaxial structure, and the second source/drain epitaxial structure.

Example 7. The method of Example 6,

and a lower isolation structure disposed below the intermediate isolation structure and surrounding the backside dielectric cap.

Example 8. The method of Example 1,

and a dielectric sidewall spacer disposed along sidewalls of the backside source/drain contacts.

Example 9. The method of Example 1,

and an inner spacer separating the gate structure from the first source/drain epitaxial structure and the second source/drain epitaxial structure.

Example 10. The method of Example 1,

wherein the channel structure comprises a stack of semiconductor nanowires.

Embodiment 11. A semiconductor transistor device comprising:

channel structures;

a gate structure surrounding the channel structure;

a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure;

a gate contact disposed on the gate structure;

a backside source/drain contact disposed below the first source/drain epitaxial structure and in contact with the first source/drain epitaxial structure; and

a backside dielectric cap disposed under the second source/drain epitaxial structure and the gate structure and in contact with the second source/drain epitaxial structure and the gate structure

A semiconductor transistor device comprising:

Example 12. The method of Example 11,

and the second source/drain epitaxial structure has a bottom surface positioned higher than a bottom surface of the gate structure.

Example 13. The method of Example 11,

and the backside source/drain contacts have a top surface positioned higher than a bottom surface of the gate structure.

Example 14. The method of Example 11,

and a dielectric sidewall spacer disposed between the backside source/drain contact and the backside dielectric cap.

Example 15. The method of Example 11,

The gate structure comprises:

gate electrode; and

a gate dielectric between the gate electrode and the channel structure

A semiconductor transistor device comprising:

Example 16. The method of Example 11,

wherein the channel structure comprises a stack of semiconductor nanowires.

Example 17. The method of Example 11,

and an inner spacer separating the gate structure from the first source/drain epitaxial structure and the second source/drain epitaxial structure.

Example 18. The method of Example 11,

and the backside dielectric cap comprises SiO ₂ , SiN, SiCN, SiOCN, Al ₂ O ₃ , AlON, ZrO ₂ , HfO ₂ , or combinations thereof.

Embodiment 19. A method of forming a semiconductor transistor device, comprising:

forming a fin structure over the substrate by alternately stacking first semiconductor layers and second semiconductor layers;

forming a dummy gate structure on the fin structure;

removing a portion of the fin structure not covered by the dummy gate structure;

forming inner spacers on opposite sides of the remaining portions of the first semiconductor layers;

forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin structure;

replacing the dummy gate structure and the first semiconductor layers with a metal gate structure;

removing the substrate and forming a backside capping trench to expose bottom surfaces of the metal gate structure and a bottom surface of the second source/drain epitaxial structure - a bottom of the second source/drain epitaxial structure surface is recessed;

forming a backside dielectric cap within the backside capping trench; and

forming a backside source/drain contact under the first source/drain epitaxial structure and in contact with the first source/drain epitaxial structure;

A method of forming a semiconductor transistor device comprising:

Example 20. The method of Example 19,

The step of forming the back-side source/drain contact comprises:

after forming the inner spacers, forming a backside contact trench;

filling the backside contact trench with a sacrificial semiconductor material;

prior to forming the backside capping trench, removing the sacrificial semiconductor material and replacing it with a sidewall spacer dielectric material;

removing at least a portion of the sidewall spacer dielectric material; and

After forming the backside dielectric cap, replacing the backside source/drain contacts with the

A method of forming a semiconductor transistor device comprising:

Claims (10)

A semiconductor transistor device comprising:
channel structures;
a gate structure surrounding the channel structure;
a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure;
a gate contact disposed on the gate structure; and
a back-side source/drain contact disposed below the first source/drain epitaxial structure;
and the first source/drain epitaxial structure has a concave bottom surface in contact with the backside source/drain contact. The method according to claim 1,
and a backside dielectric cap disposed below the second source/drain epitaxial structure and in direct contact with the second source/drain epitaxial structure. 3. The method according to claim 2,
and the second source/drain epitaxial structure has a concave bottom surface in contact with the backside dielectric cap. 3. The method according to claim 2,
and the backside dielectric cap extends below the gate structure. 3. The method according to claim 2,
and an intermediate isolation structure surrounding the gate structure, the first source/drain epitaxial structure, and the second source/drain epitaxial structure. The method according to claim 1,
and a dielectric sidewall spacer disposed along sidewalls of the backside source/drain contacts. The method according to claim 1,
and an inner spacer separating the gate structure from the first source/drain epitaxial structure and the second source/drain epitaxial structure. The method according to claim 1,
wherein the channel structure comprises a stack of semiconductor nanowires. A semiconductor transistor device comprising:
channel structures;
a gate structure surrounding the channel structure;
a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure;
a gate contact disposed on the gate structure;
a backside source/drain contact disposed below the first source/drain epitaxial structure and in contact with the first source/drain epitaxial structure; and
a backside dielectric cap disposed under the second source/drain epitaxial structure and the gate structure and in contact with the second source/drain epitaxial structure and the gate structure
including,
and the backside source/drain contact has a top surface positioned higher than a bottom surface of the gate structure. A method of forming a semiconductor transistor device, comprising:
forming a fin structure over the substrate by alternately stacking first semiconductor layers and second semiconductor layers;
forming a dummy gate structure on the fin structure;
removing a portion of the fin structure not covered by the dummy gate structure;
forming inner spacers on opposite sides of the remaining portions of the first semiconductor layers;
forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin structure;
replacing the dummy gate structure and the first semiconductor layers with a metal gate structure;
removing the substrate and forming a backside capping trench to expose bottom surfaces of the metal gate structure and a bottom surface of the second source/drain epitaxial structure - a bottom of the second source/drain epitaxial structure surface is recessed - ;
forming a backside dielectric cap within the backside capping trench; and
forming a backside source/drain contact under the first source/drain epitaxial structure and in contact with the first source/drain epitaxial structure;
A method of forming a semiconductor transistor device comprising:

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