CN117410184A - NMOS transistor preparation method and NMOS transistor - Google Patents
NMOS transistor preparation method and NMOS transistor Download PDFInfo
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- CN117410184A CN117410184A CN202311696955.0A CN202311696955A CN117410184A CN 117410184 A CN117410184 A CN 117410184A CN 202311696955 A CN202311696955 A CN 202311696955A CN 117410184 A CN117410184 A CN 117410184A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention relates to an NMOS transistor preparation method and an NMOS transistor, wherein a substrate is provided, the substrate comprises a plurality of active areas which are arranged in an array manner and a groove used for limiting the plurality of active areas, a liner oxide layer is formed on the inner side wall of the groove, a filling layer with the top surface lower than that of the liner oxide layer is formed in the groove, a first preamorphism blocking layer and a second preamorphism blocking layer are sequentially formed in the active areas at least through the inner side wall of the groove, P-type ion implantation is carried out between the first preamorphism blocking layer and the second preamorphism blocking layer, after the filling layer is removed, a buffer isolation layer which covers the liner oxide layer is formed in the groove, the growth stress during the subsequent formation of an isolation structure is relieved, the isolation structure with the top surface not lower than that of the liner oxide layer is formed in the groove, an NMOS transistor is formed in the active area, the threshold voltage of the NMOS transistor is improved, and the reverse narrow channel effect of the NMOS transistor is improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a method for manufacturing an NMOS transistor and an NMOS transistor.
Background
With the development of semiconductor technology, shallow trench isolation technology is widely used to isolate the mutual interference between different circuits in an integrated circuit, reduce the manufacturing cost and improve the integration level of the integrated circuit.
However, as the trench width decreases, some negative effects, such as anti-narrow channel effects, occur during integrated circuit fabrication. The anti-narrow channel effect refers to a phenomenon that the concentration of electrons in an isolation region increases, and due to the existence of stress of a shallow trench isolation material deposited in a shallow trench isolation technology, doped ions in an active region are precipitated into a shallow trench, so that the voltage threshold of an N-Metal-Oxide-Semiconductor (NMOS) is reduced, and the electrical specification cannot be met. Therefore, how to improve the inverse narrow channel effect of the NMOS device is one of the problems that are currently urgently needed to be solved.
Disclosure of Invention
Based on this, it is necessary to provide an NMOS transistor manufacturing method and an NMOS transistor for solving the problem that the trench isolation structure in the prior art causes the NMOS voltage threshold to be low.
To achieve the above object, in one aspect, the present application provides an NMOS transistor manufacturing method, including: providing a substrate, wherein the substrate comprises a plurality of active areas arranged in an array manner and a groove used for limiting the plurality of active areas, and a liner oxide layer is formed on the inner side wall of the groove; forming a filling layer with the top surface lower than the top surface of the liner oxide layer in the groove; after forming a first preamorphization barrier layer into the active region at least through the inner side wall of the groove, performing a P-type ion implantation process on the active region, and forming a second preamorphization barrier layer in the active region, wherein the implanted P-type ions are positioned between the first preamorphization barrier layer and the second preamorphization barrier layer; after removing the filling layer, forming a buffer isolation layer covering the liner oxide layer in the groove; and forming an isolation structure with the top surface not lower than the top surface of the liner oxide layer in the groove, and then forming an NMOS transistor in the active region.
In one embodiment, after forming a first preamorphized barrier layer into the active region at least through the inner sidewall of the trench, performing a P-type ion implantation process on the active region, and forming a second preamorphized barrier layer in the active region, comprising: implanting ions into the active region through the uncovered sidewalls of the trench to form a first pre-amorphization barrier; taking the first preamorphization blocking layer as a blocking layer, and executing a P-type ion implantation process on the active region; ion implantation is performed again into the active region through the uncovered sidewalls of the trench to form a second pre-amorphized barrier layer.
In one embodiment, the NMOS transistor manufacturing method includes: the ion implantation energy for forming the first pre-amorphization barrier is greater than the ion implantation energy for forming the second pre-amorphization barrier; and forming the first pre-amorphized barrier layer at an ion implantation concentration equal to an ion implantation concentration at which the second pre-amorphized barrier layer is formed.
In one embodiment, the first preamorphized barrier layer is formed with the same type of implanted ions as the second preamorphized barrier layer, both being tetravalent ions.
In one embodiment, the buffer spacer layer has a thickness of 80 angstroms to 160 angstroms.
In one embodiment, the NMOS transistor manufacturing method includes: and carrying out thermal oxidation treatment on the inner side wall of the groove of the substrate in the furnace tube, so that the corner of the groove is rounded to form a liner oxide layer with a smooth cambered surface.
In one embodiment, the NMOS transistor manufacturing method includes: a hard mask layer and an interface oxide layer positioned between the hard mask layer and the substrate are formed on the top surface of the substrate; and etching the hard mask layer, the interface oxide layer and the substrate to obtain the trench.
In one embodiment, forming an isolation structure having a top surface not lower than a top surface of the liner oxide in the trench includes: forming an isolation material with a top surface higher than the top surface of the liner oxide layer at least in the groove; taking the hard mask layer as a stop layer, and removing part of isolation materials by adopting a chemical mechanical polishing process; and taking the interface oxide layer as a stop layer, removing the hard mask layer and part of the isolation material by adopting a wet etching process, and forming an isolation structure by using the rest of the isolation material.
In one embodiment, after forming the isolation material with a top surface higher than the top surface of the liner oxide layer at least in the trench, the method further comprises: and annealing the isolation material to enable the first preamorphized barrier layer, the second preamorphized barrier layer and the substrate to conduct covalent bond recombination.
The application also provides an NMOS transistor which is prepared by adopting the NMOS transistor preparation method in any one embodiment of the present disclosure.
The NMOS transistor preparation method and the NMOS transistor have the following unexpected beneficial effects:
according to the NMOS transistor preparation method and the NMOS transistor, firstly, a substrate is provided, the substrate comprises a plurality of active areas distributed in an array and grooves used for limiting the plurality of active areas, the active areas are used for forming semiconductor devices, the grooves are used for isolating charges among different active areas, mutual interference among the active areas is avoided, a liner oxide layer is formed on the inner side wall of each groove, in the process of forming the liner oxide layer, damage when the grooves are formed can be repaired, then a filling layer with the top surface lower than the top surface of the liner oxide layer is formed in each groove, a first pre-amorphization blocking layer and a second pre-amorphization blocking layer are sequentially formed in the active areas at least through the inner side wall of each groove, P-type ions in the active areas are prevented from being separated out to each groove, the P-type ion concentration in the active areas is improved, after the filling layer is removed, a buffer layer covering the liner oxide layer is formed in each groove, the subsequent growth of an isolation structure is relieved, the top surface is not lower than the liner oxide layer in each groove, and the threshold voltage of the NMOS transistor is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for manufacturing an NMOS transistor according to one embodiment;
FIG. 2 is a schematic cross-sectional view of a structure obtained after forming a trench in step S200 in an NMOS transistor manufacturing method according to an embodiment;
FIG. 3 is a schematic cross-sectional view of a structure obtained after forming a pad oxide layer in step S200 in an NMOS transistor manufacturing method according to an embodiment;
FIG. 4 is a schematic cross-sectional view of a structure obtained after forming a first pre-amorphized barrier layer in step S400 in an NMOS transistor manufacturing method according to an embodiment;
FIG. 5 is a schematic cross-sectional view of a structure obtained after forming a buffer isolation layer in step S500 in an NMOS transistor manufacturing method according to an embodiment;
FIG. 6 is a schematic cross-sectional view of a structure obtained after filling isolation material in step S600 in an NMOS transistor manufacturing method according to an embodiment;
FIG. 7 is a schematic cross-sectional view of a structure obtained after forming an isolation structure in step S600 in an NMOS transistor manufacturing method according to an embodiment;
FIG. 8 is a schematic cross-sectional view of a structure obtained after removing the hard mask layer in step S600 in the method for manufacturing an NMOS transistor according to an embodiment;
fig. 9 is a schematic diagram showing a variation of a voltage threshold with a trench width in different NMOS transistor manufacturing methods according to an embodiment.
Reference numerals illustrate:
10. a substrate; 20. an interface oxide layer; 30. a hard mask layer; 40. a groove; 410. a pad oxide layer; 420. a buffer isolation layer; 430. a spacer material; 50. and (5) a filling layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Referring to fig. 1, the present application provides a method for preparing an NMOS transistor, including the following steps:
step S200: providing a substrate, wherein the substrate comprises a plurality of active areas arranged in an array manner and a groove used for limiting the plurality of active areas, and a liner oxide layer is formed on the inner side wall of the groove;
step S300: forming a filling layer with the top surface lower than the top surface of the liner oxide layer in the groove;
step S400: after forming a first preamorphization barrier layer into the active region at least through the inner side wall of the groove, performing a P-type ion implantation process on the active region, and forming a second preamorphization barrier layer in the active region, wherein the implanted P-type ions are positioned between the first preamorphization barrier layer and the second preamorphization barrier layer;
step S500: after removing the filling layer, forming a buffer isolation layer covering the liner oxide layer in the groove;
step S600: and forming an isolation structure with the top surface not lower than the top surface of the liner oxide layer in the groove, and then forming an NMOS transistor in the active region.
In step S200, the substrate may be formed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate may have a single-layer structure or a multilayer structure. For example, the substrate may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate should not limit the scope of the present disclosure.
In addition, the substrate is a P-type doped substrate, and the type of P-type impurity ions is not particularly limited in the embodiments of the present disclosure. As an example, the P-type impurity ions may include, but are not limited to, any one or more of Boron (B) ions, gallium (Ga) ions, indium (In) ions, and the like.
In the embodiment, the substrate is provided to support the subsequent film layer, the substrate is provided with the grooves arranged at intervals and the active region defined by the grooves, the grooves are used for isolating charges between different devices, the devices are prevented from being interfered with each other, the liner oxide layer is formed on the inner surface of the grooves, sharp corner parts of the grooves can be rounded, meanwhile, damage during forming the grooves can be repaired, the first preamorphization blocking layer and the second preamorphization blocking layer are sequentially formed on the inner side wall of the grooves towards the active region, P-type ion implantation is performed between the first preamorphization blocking layer and the second preamorphization blocking layer, then after the filling layer is removed, a buffer isolation layer covering the liner oxide layer is formed in the grooves, growth stress during subsequent forming of the isolation structure is relieved, the top surface of the liner oxide layer is not lower than that of the isolation structure is formed in the grooves, then the NMOS transistor is formed in the active region, P-type ions in the substrate are prevented from being separated out into the grooves, threshold voltage of the NMOS is improved, and reverse narrow channel effect of the NMOS transistor is improved.
In one embodiment, please continue with reference to fig. 1, the nmos transistor manufacturing method further includes:
step S110: forming a hard mask layer on the top surface of the substrate and an interface oxide layer between the hard mask layer and the substrate;
step S120: and etching the hard mask layer, the interface oxide layer and the substrate to obtain the trench.
The hard mask layer may be a single-layer structure or a multi-layer stacked structure, and the material of the hard mask layer may be silicon nitride. A hard mask layer is deposited on the substrate and the deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD), and Spin-on Dielectric (SOD) processes.
In step S120, referring to fig. 1 and 2, the interfacial oxide layer 20, the hard mask layer 30 and the substrate 10 are etched to obtain a trench 40, and a photoresist layer may be coated on the hard mask layer 30, and exposed and developedShadow, etc., a series of steps, forming a patterned photoresist layer defining the location, shape, and size of trench 40, etc. As an example, a dry etching process may be selected to etch the interfacial oxide layer 20, the hard mask layer 30, and the substrate 10, and the etching gas of the dry etching process may include: one or more of fluorocarbon gas, HBr, and carrier gas, the fluorocarbon gas including CF 4 、CHF 3 、CH 2 F 2 Or CH (CH) 3 F, the carrier gas is an inert gas, such as He.
In one embodiment, referring to fig. 3, a liner oxide layer 410 is formed overlying the inner surface of trench 40, comprising:
step S210: the inner sidewall of the trench 40 of the substrate 10 is subjected to a thermal oxidation process in the furnace tube, so that the corner of the trench 40 is rounded to form a pad oxide layer 410 having a rounded arc surface.
The material of the pad oxide layer 410 may be silicon oxide, silicon nitride, aluminum nitride, etc. The furnace tube is selected for deposition of the pad oxide layer 410 because the low pressure chemical vapor deposition process performed in the furnace tube has advantages of low deposition temperature, easy control of film composition and thickness, proportional film thickness to deposition time, good uniformity and repeatability, good step coverage, convenient operation, etc.
In the above embodiment, the pad oxide layer 410 may be used to round the sharp corner in the trench 40, disperse stress, avoid precipitation of P-type ions, improve the reliability of the structure, avoid concentration of leakage current and electric field at the sharp corner, cause electrical breakdown, reduce crystal defects, and planarize the substrate 10.
In one embodiment, referring to fig. 4, the material of the filling layer 50 may be a Bottom Anti-reflective coating (BARC) for reducing light reflection and improving uniformity of photoresist exposure, which can reduce reflected light intensity, prevent unnecessary light spots or shadows, and thereby improve accuracy and reliability of transistor fabrication. The fill layer 50 height may be 1/2-2/3 of the trench depth, for example: 3/5, 4/7, 5/8, 5/9, etc.
In one embodiment, please continue to refer to fig. 4, after forming a first pre-amorphization barrier (not shown) into the active region at least through the inner sidewall of the trench 40, performing a P-type ion implantation process on the active region, and forming a second pre-amorphization barrier (not shown) in the active region, comprising:
step S410: implanting ions into the active region through the uncovered sidewalls of the trench 40 to form a first pre-amorphized barrier;
step S420: taking the first preamorphization blocking layer as a blocking layer, and executing a P-type ion implantation process on the active region;
step S430: ion implantation is performed again into the active region through the uncovered sidewalls of the trench to form a second pre-amorphized barrier layer.
In step S410, the sidewalls of the active region that are not covered are the top corners at both sides of the active region, and when the width of the isolation structure is too small, the implantation may be performed on the entire sidewalls of the active region. In addition, to avoid affecting the threshold voltage of the P-type metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS), the first pre-amorphized barrier layer, the P-type ion implantation, and the second amorphized barrier layer may be formed simultaneously with the formation of the first pre-amorphized barrier layer, the P-type ion implantation, and the second amorphized barrier layer, and the region for forming the PMOS may be covered with photoresist, so as to avoid ion implantation into the active region of the region for forming the PMOS, thereby affecting the performance of the PMOS device.
In step S420, the P-type ions may include boron ions or boron difluoride ions, and the implantation energy may be 30Kev to 50Kev when the P-type ion implantation is performed, for example, 35Kev, 40Kev, 45Kev, or the like may be used; the implantation concentration may be 1×10 13 /cm 2 -3×10 13 /cm 2 For example: 1.2X10 13 /cm 2 、1.4×10 13 /cm 2 、1.6×10 13 /cm 2 、1.8×10 13 /cm 2 、2.0×10 13 /cm 2 、2.2×10 13 /cm 2 、2.5×10 13 /cm 2 、2.6×10 13 /cm 2 、2.8×10 13 /cm 2 Etc.; the implantation angle may be 35-45 degrees, for example, 37 degrees, 38 degrees, 39 degrees, 40 degrees, 42 degrees, 43 degrees, 44 degrees, or the like may be employed.In other embodiments, other numerical ranges may be selected according to actual requirements.
In the above embodiment, the first pre-amorphization barrier layer is formed, so that the effect of diffusing the P-type ions subsequently implanted into the deep portion of the active region to affect the ion concentration of the active region can be avoided, the P-type ion concentration can be supplemented in advance by performing P-type ion implantation, the concentration reduction caused by the precipitation of the P-type ions in the active region can be avoided, the second pre-amorphization barrier layer is formed again, the P-type ions are blocked from precipitating into the trench, the positions of the implanted P-type ions are fixed by using the first pre-amorphization barrier layer and the second pre-amorphization barrier layer, and the influence on other performances of the semiconductor device can be avoided while the threshold voltage of the NMOS is improved.
In one embodiment, the ion implantation energy to form the first pre-amorphized barrier layer is greater than the ion implantation energy to form the second pre-amorphized barrier layer; and forming the first pre-amorphized barrier layer at an ion implantation concentration equal to an ion implantation concentration at which the second pre-amorphized barrier layer is formed.
As an example, the ion implantation energy to form the first pre-amorphized barrier layer may be 30Kev to 60Kev, for example: 35Kev, 40Kev, 45Kev, 50Kev, 55Kev, etc.; the ion implantation energy of the second preamorphization barrier layer needs to be less than the implantation energy of the first preamorphization barrier layer; the implantation concentration for forming the first preamorphization barrier layer and the second preamorphization barrier layer is 1×10 15 /cm 2 -3×10 15 /cm 2 For example: 1.2X10 15 /cm 2 、1.4×10 15 /cm 2 、1.6×10 15 /cm 2 、1.8×10 15 /cm 2 、2.0×10 15 /cm 2 、2.2×10 15 /cm 2 、2.5×10 15 /cm 2 、2.6×10 15 /cm 2 、2.8×10 15 /cm 2 Etc. In addition, the implantation angle for forming the first pre-amorphized barrier layer and the second pre-amorphized barrier layer is 35 degrees to 45 degrees, and for example, 37 degrees, 38 degrees, 39 degrees, 40 degrees, 42 degrees, 43 degrees, 44 degrees may be used. The implantation energy and implantation of the first preamorphization barrier layer and the second preamorphization barrier layer are formedValues for concentration, implantation angle include, but are not limited to, the ranges described above, and in other embodiments, suitable ranges may be selected depending on device requirements.
In the above embodiment, the implantation energy is associated with the implantation depth, the implantation depth is deeper as the implantation energy is larger, the implantation energy is controlled to select a proper implantation depth, the implantation concentration is associated with the voltage threshold, the voltage threshold is higher as the implantation concentration is larger, and a proper implantation concentration is required to be selected to ensure that the voltage threshold is between the upper limit and the lower limit of the specification.
In one embodiment, the implantation angle at which the first pre-amorphized barrier layer and the second pre-amorphized barrier layer are formed is associated with the width of the trench, the implantation angle being closer to horizontal as the width is wider.
In one embodiment, the first preamorphized barrier layer is formed with the same type of implanted ions as the second preamorphized barrier layer, both being tetravalent ions.
As an example, the implanted ions may include, but are not limited to, any of carbon ions, germanium ions, silicon ions.
In the above embodiment, the implantation of tetravalent ions can break down the crystal lattice of crystalline silicon to form an amorphous silicon layer for controlling the deformation of crystalline silicon, and the defect of the implantation of P-type ions is limited to the amorphous silicon layer, thereby protecting the integrity of crystalline silicon, i.e., the substrate.
In one embodiment, referring to fig. 5, after forming the second pre-amorphization barrier, the method further includes:
step S510: a buffer isolation layer 420 is formed within the inner surface of trench 40.
The material of the buffer isolation layer 420 may be silicon nitride. As an example, the buffer isolation layer 420 is formed on the upper surfaces of the hard mask layer 30 and the pad oxide layer 410, and the buffer isolation layer 420 except for the inner surface of the trench may be removed through a grinding process in a subsequent process of forming the isolation structure.
In the above embodiment, the silicon nitride layer is used as the buffer isolation layer 420, which can assist in isolation and stress improvement, and reduce the influence of the deposition stress of the trench 40 on the electron mobility of the NMOS, thereby reducing the precipitation of P-type ions in the active region and further increasing the threshold voltage of the NMOS.
In one embodiment, the buffer spacer layer has a thickness of 80 angstroms to 160 angstroms. For example, 90 angstroms, 100 angstroms, 110 angstroms, 120 angstroms, 130 angstroms, 140 angstroms, 150 angstroms, etc. may be selected.
In one embodiment, referring to fig. 6, 7 and 8, an isolation structure having a top surface not lower than a top surface of the pad oxide layer 410 is formed in the trench 40, comprising:
step S610: forming an isolation material 430 having a top surface higher than the top surface of the pad oxide layer 410 at least in the trench 40;
step S620: taking the hard mask layer 30 as a stop layer, and removing part of the isolation material 430 by adopting a chemical mechanical polishing process;
step S630: with the interfacial oxide layer 20 as a stop layer, a wet etching process is used to remove a portion of the isolation material 430 and the hard mask layer 30, and the remaining isolation material 430 is used to form an isolation structure.
The isolation material 430 may include silicon oxide, silicon nitride, aluminum oxide, various polymer materials, and the like, among others.
In step S620, as an example, the removal of a portion of the isolation material 430 may be performed by combining chemical mechanical polishing and wet etching, a chemical mechanical polishing process is used to planarize the upper surface of the isolation material 430, the hard mask layer 30 is set as a stop layer, and the polishing time is set such that the hard mask layer 30 is not damaged, so as to avoid unnecessary damage to the NMOS device caused by the chemical mechanical polishing. After chemical mechanical polishing, the isolation material 430 is wet etched with an acidic or alkaline solution such as hydrofluoric acid, ammonia, etc., and the filling height of the isolation material 430 is adjusted.
In step S630, referring to fig. 7 and 8, the hard mask layer 30 is wet etched, and the etching solution may be phosphoric acid solution. The phosphoric acid solution has high selectivity to the hard mask layer 30, so that the interface oxide layer 20 can be prevented from being damaged when the hard mask layer 30 is etched; in order to avoid damaging the interfacial oxide layer 20, an optical instrument such as ellipsometer, electron microscope, etc. may be selected to observe the film surface during etching, and when the hard mask layer 30 disappears, the etching is stopped immediately, and the etching solution is cleaned by using the solution, so as to avoid the etching solution from continuing to react.
In one embodiment, after forming the isolation material with a top surface higher than the top surface of the liner oxide layer at least in the trench, the method further comprises:
step S611: and annealing the isolation material to enable the first preamorphized barrier layer, the second preamorphized barrier layer and the substrate to conduct covalent bond recombination.
Wherein the annealing process can be wet annealing process or dry annealing process, and the annealing gas comprises H 2 、O 2 、N 2 One or more combinations of Ar and He for an anneal time of 1.5 hours to 2.5 hours, for example, the anneal time may be 1.5 hours, 2.0 hours, or 2.5 hours. Wherein, when the annealing gas comprises H 2 And O 2 In this case, the annealing process is a wet annealing process.
In the above embodiment, the annealing process is used to treat the semiconductor device, so that the first pre-amorphization barrier layer, the second pre-amorphization barrier layer and the implanted P-type ions are recombined with the substrate by covalent bonds, the pre-amorphization effect is eliminated, the implanted P-type ions are fixed in the required region, the purpose of precisely controlling the implantation concentration and the implantation region range is achieved, and the problem that the NMOS threshold is affected due to the fact that the P-type ions are directly implanted or the P-type ions continue to diffuse into the trench in the subsequent process due to the pre-amorphization is avoided.
In one embodiment, the annealing temperature is 900 degrees celsius to 1200 degrees celsius. For example: the annealing temperature may be 950 degrees celsius, 970 degrees celsius, 990 degrees celsius, 1000 degrees celsius, 1030 degrees celsius, 1050 degrees celsius, 1080 degrees celsius, 1100 degrees celsius, 1150 degrees celsius, 1180 degrees celsius, or the like.
In one embodiment, forming an NMOS transistor within an active region includes:
step S640: and forming a gate dielectric layer, a gate conducting layer, a gate side wall, a source electrode and a drain electrode in the active region in sequence.
In step S640, the gate dielectric layer may be made of a material selected from silicon dioxide (SiO 2 ) Silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxideAl 2 O 3 ) Aluminum oxynitride (AlON) and combinations thereof. The gate conductive layer may include, but is not limited to, titanium nitride (TiN), titanium (Ti), tungsten silicide (Tungsten silicide, si) 2 W) and Tungsten (W), etc. The gate sidewall may include, but is not limited to, one or more of silicon oxide, silicon nitride, polysilicon, and a metal material. In addition, to form an NMOS device, when the substrate is a P-type substrate, the source region may be formed by implanting N-type ions. The embodiments of the present disclosure are not particularly limited As to the kind of the N-type impurity ion, and the N-type impurity ion may include, by way of example, one or more of phosphorus (P) ion, arsenic (As) ion, or antimony (Sb) ion.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
The application also provides an NMOS transistor comprising: a substrate in which alternately arranged trenches are present and an active region defined by the trenches; the interface oxidation layer covers the top surface of the active region; the grid structure is positioned on the top surface of the active area interface oxide layer; the source electrode and the drain electrode are respectively positioned at two sides of the grid electrode structure, and at least one transistor structure is arranged in each active region; a liner oxide layer covering the inner surface of the trench; the buffer isolation layer covers the liner oxide layer and is used for improving the growth stress of the groove; and the isolation structure fills the groove to a certain height.
In the embodiment, the active region in the substrate is used for manufacturing the NMOS semiconductor device, the trench is used for isolating charges in different semiconductor devices, mutual interference between the active regions is avoided, when the trench is formed, the method further comprises the steps of forming a first preamorphization blocking layer, a second preamorphization blocking layer and P-type ion implantation between the first preamorphization blocking layer and the second preamorphization blocking layer from the inner side wall of the trench at a certain angle, supplementing P-type ions in the active region in advance, avoiding voltage threshold reduction caused by P-type ion precipitation in the active region substrate, the first preamorphization blocking layer and the second preamorphization blocking layer can prevent the P-type ions from diffusing into the active region or the trench, the liner oxide layer can round sharp corner portions of the trench, avoiding P-type ion precipitation, the buffer isolation layer can relieve deposition stress of the trench, relieving the P-type ion precipitation, after the isolation material is formed, the first preamorphization blocking layer and the second preamorphization blocking layer are processed by using an annealing process, the P-type ion recombination layer and the P-type ions are fixed at positions in the NMOS transistor, and the covalent bond effect is further improved.
Referring to fig. 9, where the abscissa is the width of the trench and the ordinate is the voltage threshold, it can be seen that when the trench is wider, the effect of the P-type ion concentration in the trench is negligible, and there is basically no anti-narrow channel effect, and when the trench is smaller, the effect of the P-type ion concentration on the voltage threshold is extremely large. The legend 1 is the voltage threshold under ideal conditions, the legend 2 is the upper limit of the voltage threshold in the electrical specification, the legend 3 is the lower limit of the voltage threshold in the electrical specification, and the voltage threshold must be between the upper limit and the lower limit according to the electrical specification. The voltage threshold value of P-type ions with higher concentration is implanted in the legend 4, the voltage threshold value of P-type ions with proper concentration is implanted in the legend 5, and the voltage threshold value of P-type ions in the active region are precipitated into the groove when P-type ion implantation is not performed in the legend 6, so that the problem of low voltage threshold value in the general preparation method can be effectively solved by the NMOS transistor preparation method, and the voltage threshold value can be controlled by controlling the implantation concentration of P-type ions so as to ensure that the voltage threshold value is in the range of electrical specifications.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application.
Claims (10)
1. A method of manufacturing an NMOS transistor, comprising:
providing a substrate, wherein the substrate comprises a plurality of active areas arranged in an array manner and a groove used for limiting the plurality of active areas, and a liner oxide layer is formed on the inner side wall of the groove;
forming a filling layer with the top surface lower than the top surface of the liner oxide layer in the groove;
after forming a first preamorphization barrier layer into the active region at least through the inner side wall of the groove, performing a P-type ion implantation process on the active region, and forming a second preamorphization barrier layer in the active region, wherein the implanted P-type ions are positioned between the first preamorphization barrier layer and the second preamorphization barrier layer;
after removing the filling layer, forming a buffer isolation layer covering the liner oxide layer in the groove;
and forming an isolation structure with the top surface not lower than the top surface of the liner oxide layer in the groove, and then forming an NMOS transistor in the active region.
2. The method of claim 1, wherein forming a first pre-amorphized barrier layer into the active region at least through an inner sidewall of the trench, performing a P-type ion implantation process on the active region, and forming a second pre-amorphized barrier layer in the active region, comprises:
implanting ions into the active region through the uncovered sidewalls of the trench to form the first pre-amorphization barrier;
taking the first pre-amorphization barrier layer as a barrier layer, and executing a P-type ion implantation process on the active region;
and implanting ions into the active region again through the uncovered side wall of the groove to form the second pre-amorphization barrier layer.
3. The method of claim 2, wherein the ion implantation energy to form the first pre-amorphized barrier layer is greater than the ion implantation energy to form the second pre-amorphized barrier layer; and
and forming the first pre-amorphized barrier layer at an ion implantation concentration equal to that of the second pre-amorphized barrier layer.
4. The method of claim 2, wherein the first pre-amorphized barrier layer is formed with the same type of implanted ions as the second pre-amorphized barrier layer, both being tetravalent ions.
5. The method of any one of claims 1-4, wherein the buffer spacer layer has a thickness of 80 angstroms to 160 angstroms.
6. The method according to any one of claims 1 to 4, wherein the inside walls of the trench of the substrate are subjected to a thermal oxidation treatment in a furnace tube so that corners of the trench are rounded to form the pad oxide layer having a rounded arc surface.
7. The method of any one of claims 1-4, wherein a top surface of the substrate is formed with a hard mask layer and an interfacial oxide layer between the hard mask layer and the substrate;
and etching the hard mask layer, the interface oxide layer and the substrate to obtain the groove.
8. The method of claim 7, wherein forming an isolation structure in the trench having a top surface not lower than a top surface of the liner oxide layer, comprises:
forming an isolation material in at least the trench, wherein the top surface of the isolation material is higher than the top surface of the liner oxide layer;
taking the hard mask layer as a stop layer, and removing part of the isolation material by adopting a chemical mechanical polishing process;
and taking the interface oxide layer as a stop layer, removing part of the isolation material and the hard mask layer by adopting a wet etching process, and forming the isolation structure by using the rest of the isolation material.
9. The method of claim 8, further comprising, after forming at least the isolation material in the trench having a top surface higher than the top surface of the liner oxide layer:
and annealing the isolation material to enable the first preamorphized barrier layer, the second preamorphized barrier layer and the substrate to conduct covalent bond recombination.
10. An NMOS transistor manufactured by the NMOS transistor manufacturing method of any one of claims 1 to 9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117747535A (en) * | 2024-02-21 | 2024-03-22 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method |
| CN117747536A (en) * | 2024-02-21 | 2024-03-22 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
| CN117747535B (en) * | 2024-02-21 | 2024-05-28 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770485A (en) * | 1997-03-04 | 1998-06-23 | Advanced Micro Devices, Inc. | MOSFET device with an amorphized source and fabrication method thereof |
| US20050012173A1 (en) * | 2003-07-14 | 2005-01-20 | Yi-Ming Sheu | Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
| US20050074931A1 (en) * | 2003-10-07 | 2005-04-07 | Yu-Ren Wang | Method of manufacturing metal-oxide-semiconductor transistor |
| US7033916B1 (en) * | 2004-02-02 | 2006-04-25 | Advanced Micro Devices, Inc. | Shallow junction semiconductor and method for the fabrication thereof |
| CN106847683A (en) * | 2015-12-07 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | The method for improving fin field effect pipe performance |
| US20220069103A1 (en) * | 2020-08-28 | 2022-03-03 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor device |
| CN114759094A (en) * | 2022-04-27 | 2022-07-15 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method |
-
2023
- 2023-12-12 CN CN202311696955.0A patent/CN117410184B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770485A (en) * | 1997-03-04 | 1998-06-23 | Advanced Micro Devices, Inc. | MOSFET device with an amorphized source and fabrication method thereof |
| US20050012173A1 (en) * | 2003-07-14 | 2005-01-20 | Yi-Ming Sheu | Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
| US20050074931A1 (en) * | 2003-10-07 | 2005-04-07 | Yu-Ren Wang | Method of manufacturing metal-oxide-semiconductor transistor |
| US7033916B1 (en) * | 2004-02-02 | 2006-04-25 | Advanced Micro Devices, Inc. | Shallow junction semiconductor and method for the fabrication thereof |
| CN106847683A (en) * | 2015-12-07 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | The method for improving fin field effect pipe performance |
| US20220069103A1 (en) * | 2020-08-28 | 2022-03-03 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor device |
| CN114759094A (en) * | 2022-04-27 | 2022-07-15 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117747535A (en) * | 2024-02-21 | 2024-03-22 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method |
| CN117747536A (en) * | 2024-02-21 | 2024-03-22 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
| CN117747535B (en) * | 2024-02-21 | 2024-05-28 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method |
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