WO2024040883A1

WO2024040883A1 - Semiconductor structure and manufacturing method therefor

Info

Publication number: WO2024040883A1
Application number: PCT/CN2023/076338
Authority: WO
Inventors: 张卫民
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-25
Filing date: 2023-02-16
Publication date: 2024-02-29
Also published as: CN115411091A

Abstract

The embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The structure comprises: a substrate, which comprises a first active area and a second active area; a channel layer located on a surface of the substrate; a first gate electrode and a second gate electrode, wherein the first gate electrode is located above the part of the channel layer in the first active area, and the second gate electrode is located above the part of the channel layer in the second active area; first semiconductor layers, which are located on two sides of the first gate electrode and are embedded into the channel layer and the substrate, the material of the first semiconductor layers being the same as that of the channel layer; and second semiconductor layers, which are located on two sides of the second gate electrode and are embedded into the channel layer and the substrate, the material of the second semiconductor layers being different from that of the channel layer.

Description

Semiconductor structures and manufacturing methods

cross reference

This disclosure claims priority to the Chinese patent application titled "Semiconductor Structure and Fabrication Method thereof" and application number 202211028523.8, which was submitted on August 25, 2022, which is fully incorporated by reference into this disclosure.

Technical field

Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.

Background technique

Semiconductor integrated circuits are developing rapidly, and the characteristic size of semiconductor devices has entered the order of nanometers. The subsequent short channel effect limits the further improvement of the performance of semiconductor devices. The use of strained silicon technology can improve the current driving capability of semiconductor devices by increasing the carrier mobility of semiconductor devices, and has good compatibility with existing process technologies.

In strained silicon technology, the tensile stress in the channel region of the MOS transistor can increase the mobility of electrons, and the compressive stress can increase the mobility of holes. Generally speaking, tensile stress is introduced in the channel area of the N-type metal oxide semiconductor field effect transistor (NMOS tube) to improve the performance of the NMOS device. In the channel area of the P-type metal oxide semiconductor field effect transistor (PMOS tube) Compressive stress is introduced to improve the performance of PMOS devices.

For PMOS devices, the silicon germanium layer is used as the channel of the PMOS device. The compressive stress of the silicon germanium layer can increase the mobility of holes, making the PMOS device have higher carrier mobility. However, for NMOS devices, the compressive stress of the silicon germanium layer will cause the electron mobility of the NMOS device to decrease, thereby causing the carrier mobility of the NMOS device to decrease.

Contents of the invention

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to improve the carrier mobility of the transistor.

According to some embodiments of the present disclosure, on one hand, embodiments of the present disclosure provide a semiconductor structure, including: a substrate, the substrate includes a first active region and a second active region; a channel layer, the channel layer is located on the surface of the substrate ; A first gate and a second gate, the first gate is located above part of the channel layer in the first active region, and the second gate is located above part of the channel layer in the second active region; the first semiconductor layer, The first semiconductor layer is located on both sides of the first gate and is embedded in the channel layer and the substrate. The material of the first semiconductor layer and the material of the channel layer The same; the second semiconductor layer is located on both sides of the second gate and is embedded in the channel layer and the substrate. The material of the second semiconductor layer is different from the material of the channel layer.

In some embodiments, the material of the channel layer includes crystalline Si _1-x Ge _x , where 0.2≤x≤0.3.

In some embodiments, the content of germanium element in the first semiconductor layer is greater than the content of germanium element in the channel layer.

In some embodiments, the material of the first semiconductor layer includes Si _1-y Ge _y , where 0.3≤y≤0.6.

In some embodiments, the material of the second semiconductor layer includes Si _1-z C _z , where 0<z≤0.02.

In some embodiments, the top surfaces of the first semiconductor layer and the second semiconductor layer are both higher than the channel layer, and the bottom surfaces of the first semiconductor layer and the second semiconductor layer are lower than the channel layer.

In some embodiments, an isolation structure is further included, the isolation structure penetrates the channel layer and is located within the substrate, and at least one isolation structure is located between the first active region and the second active region.

In some embodiments, the first active area is a PMOS area and the second active area is an NMOS area.

According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, including: providing a substrate including a first active region and a second active region; forming a channel layer, The channel layer covers the entire surface of the substrate; a first gate electrode and a second gate electrode are formed, the first gate electrode is located above the first active area, and the second gate electrode is located above the second active area; a first semiconductor layer is formed , the first semiconductor layer is located on both sides of the first gate and is embedded in the channel layer and the substrate. The material of the first semiconductor layer is the same as the material of the channel layer; a second semiconductor layer is formed, and the second semiconductor layer is located in the channel layer. On both sides of the second gate and embedded in the channel layer and the substrate, the material of the second semiconductor layer is different from the material of the channel layer.

In some embodiments, after forming the channel layer, the method further includes: forming an isolation trench, the isolation trench is located in the channel layer and the substrate, and filling the isolation trench with an insulating material to form an isolation structure.

In some embodiments, the process temperature for forming the isolation structure is: 300°C-600°C.

In some embodiments, the steps of forming the first semiconductor layer include: etching the channel layer on both sides of the first gate and removing part of the substrate to form the first trench; filling the first trench with the first semiconductor material to form the first semiconductor layer.

In some embodiments, filling the first semiconductor material includes: using an epitaxial growth process to form a silicon germanium layer in situ in the first trench.

In some embodiments, the step of forming the second semiconductor layer includes: etching two sides of the second gate electrode. channel layer, and remove part of the substrate to form a second trench; fill the second trench with a second semiconductor material to form a second semiconductor layer.

In some embodiments, filling the second semiconductor material includes: using an epitaxial growth process to form a silicon carbide layer in situ in the second trench.

Description of drawings

One or more embodiments are exemplified by the pictures in the corresponding drawings. These illustrative illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a limitation on proportions; in order to To more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

2 to 7 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

Detailed ways

It can be known from the background technology that the silicon germanium layer is used as the channel of the PMOS device. The compressive stress of the silicon germanium layer can increase the mobility of holes, so that the PMOS device has higher carrier mobility. However, for NMOS devices, the compressive stress of the silicon germanium layer will cause the electron mobility of the NMOS device to decrease, thereby causing the carrier mobility of the NMOS device to decrease.

The analysis found that since the lattice constant of germanium atoms is larger than that of silicon atoms, when a silicon germanium layer is epitaxially grown on a silicon substrate, compressive stress is introduced into the silicon germanium layer. This layer of germanium with compressive stress is used to The silicon germanium layer serves as the channel of PMOS, which can improve the mobility of holes. At the same time, the germanium material has higher carrier mobility, so that the silicon germanium layer serves as the channel of PMOS and can improve the carrier mobility of PMOS. ; However, for NMOS, when the silicon germanium layer with compressive stress is used as the channel of NMOS, it will cause the tensile stress of NMOS to decrease, thereby reducing the carrier mobility of NMOS. Therefore, NMOS uses a silicon germanium layer. When the channel is used, the performance of NMOS is degraded.

An embodiment of the present disclosure provides a semiconductor structure to improve carrier mobility of a transistor.

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, in order to allow readers to better understand the present disclosure, Many technical details were proposed. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can also be implemented.

Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

Referring to FIG. 1 , the semiconductor structure includes: a substrate 100 including a first active region 101 and a second active region 102 ; a channel layer 200 located on the surface of the substrate 100 ; a first gate 210 and a second gate 220, the first gate 210 is located above part of the channel layer 200 of the first active region 101, and the second gate 220 is located above part of the channel layer 200 of the second active region 102; the first semiconductor Layer 214, the first semiconductor layer 214 is located on both sides of the first gate 210 and is embedded in the channel layer 200 and the substrate 100. The material of the first semiconductor layer 214 is the same as the material of the channel layer 200; the second semiconductor layer 224. The second semiconductor layer 224 is located on both sides of the second gate 220 and is embedded in the channel layer 200 and the substrate 100. The material of the second semiconductor layer 224 is different from the material of the channel layer 200.

By covering the surface of the substrate 100 with the channel layer 200, transistor structures with the same channel material can be formed in the first active region 101 and the second active region 102, without the need to make corresponding materials for different types of transistors. The channel region simplifies the manufacturing process of the channel region in the transistor structure; the first gate 210 is used to form the gate of the transistor structure in the first active region 101, and the second gate 220 is used to form the second active region. The gate electrode of the transistor structure in 102; a first semiconductor layer 214 is embedded in the substrate 100 and the channel layer 200 on both sides of the first gate electrode 210, which can be used to form the source electrode of the transistor structure in the first active region 101 or Drain, the second semiconductor layer 224 is embedded in the substrate 100 and the channel layer 200 on both sides of the second gate electrode 220, which can be used to form the source or drain of the transistor structure in the second active region 102. The channel layer 200 and the first semiconductor layer 214 can be used to increase the carrier mobility of the transistor structure in the first active region 101 , and the second semiconductor layer 224 can offset the effect of the channel layer 200 on the transistor structure in the second active region 102 The carrier mobility of the transistor structure in the second active region 102 is improved.

For the substrate 100, the material of the substrate 100 may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc.

In some embodiments, the substrate 100 may have doping ions. For example, the doping ions may be N-type ions or P-type ions. The N-type ions may specifically be phosphorus ions, arsenic ions or antimony ions; the P-type ions may be specifically It can be boron ion, indium ion or boron fluoride ion.

For the first active area 101 and the second active area 102, in this embodiment, the first active area is PMOS area, and the second active area is an NMOS area, that is, the first active area is used to form PMOS tubes, and the second active area is used to form NMOS tubes; in other embodiments, the first active area is an NMOS area, The second active area is a PMOS area, that is, the first active area can be used to form NMOS transistors, and the second active area can be used to form PMOS transistors.

For the channel layer 200, in this embodiment, the material of the channel layer includes crystal Si _1-x Ge _x , where 0.2≤x≤0.3, for example, x may be 0.2, 0.25 or 0.3. Crystal Si _1-x Ge _x materials have higher carrier mobility. The greater the content of Ge element in crystal Si _1-x Ge _x , the greater the compressive stress in the channel formed by crystal Si _1-x _Ge The improvement of PMOS device performance _is beneficial. However, when the content of Ge element is too high, there will be severe lattice mismatch in the crystal Si _1- _x _Ge A large number of dislocations and defects are generated between them, causing the strain part in the crystal Si _1-x Ge _x layer to be relaxed, weakening the stress in the channel formed by the crystal Si _1-x Ge _x layer, thus affecting the performance of the PMOS device; Reducing the content of Ge element in crystal Si _1-x Ge _x will reduce defects, but it will also reduce the compressive stress exerted by the crystal Si _1-x _Ge Rate. Therefore, the content of the Ge element in the crystalline Si _1-x Ge _x material of the channel layer needs to be adjusted within a certain range to meet the effect of improving carrier mobility without affecting the performance of the transistor structure.

Regarding the first semiconductor layer 214 , in this embodiment, the content of the germanium element in the first semiconductor layer 214 is greater than the content of the germanium element in the channel layer 200 . It can be understood that the material of the channel layer 200 is crystal Si _1-x _Ge When the first semiconductor layer 214 is used to form the source or drain of the PMOS tube, when the content of the germanium element in the first semiconductor layer 214 is greater than the content of the germanium element in the channel layer 200, the channel area of the PMOS tube can be further improved. The compressive stress further improves the carrier mobility of the PMOS tube in the first active region.

In some embodiments, the material of the first semiconductor layer may include Si _1-y Ge _y , where 0.3≤y≤0.6, for example, y may be 0.3, 0.4, 0.5 or 0.6. It can be understood that when the first semiconductor layer uses Si _1-y Ge _y to form the source or drain of the PMOS tube in the first active region, the higher the Ge element content in the first semiconductor layer, the lower the source and drain regions. The stronger the carrier migration ability, the better the conductivity. Correspondingly, the compressive stress of the source and drain of the PMOS tube on the channel area increases, and the effect on improving the carrier mobility is better, but first Too high a Ge element in the semiconductor layer can easily cause lattice mismatch, causing defects in the source or drain structure of the PMOS tube; conversely, too low a Ge element content cannot further improve the source and drain pairing of the PMOS tube. The compressive stress in the channel area increases, so that the purpose of improving the carrier mobility of the PMOS tube cannot be achieved. Therefore, the first semiconductor layer uses Si _1-y Ge _y to form the source or drain of the PMOS tube in the first active area. When, the content of Ge element in the first semiconductor layer needs to be controlled Within a certain range, the compressive stress of the first semiconductor layer on the channel region of the PMOS tube is increased, thereby further improving the carrier mobility of the PMOS tube in the first active area, while avoiding the source or drain of the PMOS tube. The structure produces defects and improves the performance of PMOS tubes.

In some embodiments, the material of the second semiconductor layer includes Si _1-z C _z , where 0<z≤0.02, for example, z may be 0.005, 0.01, 0.015 or 0.02. The lattice constant of silicon is The lattice constant of carbon is The mismatch rate between silicon and carbon is 34.27%, which makes the lattice constant of SiC smaller than that of pure silicon, and the lattice constant of carbon is much smaller than that of silicon. The Si _1-z C _z material only requires very few carbon atoms. High stresses can be obtained. For example, when the material of the channel layer is crystalline silicon germanium, the Ge element in the channel layer can be used to increase the compressive stress of the channel in the transistor structure. For PMOS tubes, it can increase the carrier migration of the PMOS tube. rate; but for NMOS tubes, the increase in compressive stress will cause the carrier mobility of the NMOS tube to decrease. Therefore, when a PMOS tube is formed in the first active area and an NMOS tube is formed in the second active area , the second semiconductor layer uses Si _1-z C _z to form the source or drain of the NMOS tube in the second active area, so that the channel compressive stress of the NMOS tube can be offset by Si _1-z C _z , thereby preventing the NMOS tube from The carrier mobility is reduced, so that the NMOS tube can offset the influence of crystalline silicon germanium as the channel and improve the carrier mobility of the NMOS tube. It can be understood that the higher the C content in the second semiconductor layer, the better the offset effect of compressive stress in the NMOS tube channel. However, due to the large difference in the lattice constants of silicon and carbon, too high C content will cause crystal distortion. Too many unpredictable defects appear in the grid, affecting the conductive properties of the source and drain regions. Therefore, when Si _1-z C _z is used as the source or drain of an NMOS tube, the NMOS tube can use silicon germanium as the channel, and at the same time offset the impact of the compressive stress on the NMOS tube when silicon germanium is used as the channel. Thereby achieving the purpose of improving the carrier mobility of the NMOS tube.

In some embodiments, the top surfaces of the first semiconductor layer and the second semiconductor layer are both higher than the channel layer, and the bottom surfaces of the first semiconductor layer and the second semiconductor layer are lower than the channel layer. It can be understood that when the first semiconductor layer and the second semiconductor layer are both thicker than the channel layer, the stress effect generated by the first semiconductor layer and the second semiconductor layer forming corresponding source or drain electrodes can work better. In the channel layer, for example, when the first active region is used to form a PMOS transistor and the second active region is used to form an NMOS transistor, the compressive stress between the first semiconductor layer can completely act on the channel of the PMOS transistor. In the channel layer, the tensile stress between the second semiconductor layers can completely act on the channel layer of the NMOS tube.

For example, in some embodiments, the height range of the top surfaces of the first semiconductor layer and the second semiconductor layer above the channel layer is 1 nm to 3 nm, for example, it may be 1 nm, 2 nm, or 3 nm; The height range of the bottom surface of the two semiconductor layers below the channel layer is 1 nm to 3 nm, for example, it can be 1 nm, 2 nm or 3 nm. It can be understood that when the first semiconductor layer and the second semiconductor layer are both thicker than the channel layer, it is beneficial for the first semiconductor layer and the second semiconductor layer to produce stress on the corresponding channel layer. However, when the difference between the thickness of the first semiconductor layer and the second semiconductor layer and the thickness of the channel layer is large, it is not conducive to the stability of the semiconductor structure. Therefore, the thickness of the first semiconductor layer and the second semiconductor layer is different from that of the channel layer. The thickness difference of the channel layer needs to be adaptively adjusted according to the actual situation to meet the needs of the semiconductor structure and improve the stability of the semiconductor structure.

For the first gate 210 and the second gate 220, in this embodiment, the first gate 210 includes a first gate dielectric layer 212, a first gate conductive layer 213 and a first gate spacer layer 211. The dielectric layer 212 is disposed on the surface of the channel layer 200. The first gate conductive layer 213 covers the surface of the first gate dielectric layer 212. The first gate spacer layer 211 covers the surface of the first gate conductive layer 213 and covers the first gate dielectric. layer 212 and the sidewalls of the first gate conductive layer 213; the second gate includes a second gate dielectric layer 222, a second gate conductive layer 223 and a second gate spacer layer 221, and the second gate dielectric layer 222 is located in the channel layer 200, the second gate conductive layer 223 covers the surface of the second gate dielectric layer 222, the second gate spacer layer 221 covers the surface of the second gate conductive layer 223, and covers the second gate dielectric layer 222 and the second gate conductive layer 222. side walls of layer 223. The gate dielectric layer can prevent the gate conductive layer from reacting with the channel layer during the subsequent process and avoid damage to the semiconductor structure. The gate sidewall layer can isolate the gates of different transistor structures from each other and prevent the gates of different transistors from being connected to each other. , or the gate of the transistor is connected to the source or drain of other transistors to cause leakage, thereby preventing the performance of the semiconductor structure from being affected.

For the first gate dielectric layer 212 and the second gate dielectric layer 222, the materials of the first gate dielectric layer 212 and the second gate dielectric layer 222 each include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

For the first gate conductive layer 213 and the second gate conductive layer 223, the materials of the first gate conductive layer 213 and the second gate conductive layer 223 include polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, At least one of aluminum, lanthanum, copper or tungsten.

For the first gate spacer layer 211 and the second gate spacer layer 221, the materials of the first gate spacer layer 211 and the second gate spacer layer 221 include at least one of silicon oxide, silicon nitride, or silicon oxynitride. kind.

In this embodiment, both the first gate spacer layer and the second gate spacer layer have a single-layer structure; in other embodiments, both the first gate spacer layer and the second gate spacer layer can have a multi-layer structure. . For example, both the first gate spacer layer and the second gate spacer layer may have a silicon oxide-silicon nitride-silicon oxide (Oxide-Nitride-Oxide, ONO) structure. By forming the ONO structure, the insulation of the gate spacer layer can be increased. ability to further avoid leakage between the gate stack and other semiconductor devices. At the same time, silicon nitride has high stress and can well support the gate sidewall layer and maintain the good shape of the gate structure.

In some embodiments, the second gate spacer layer also includes a tensile strained SiN layer. The tensile strained SiN layer contacts both ends of the SiGe channel layer to provide tensile stress to the channel layer to further alleviate stress in the SiGe channel. Effect of compressive stress on carrier mobility.

In some embodiments, the isolation structure 103 is further included. The isolation structure 103 penetrates the channel layer 200 and is located within the substrate 100. At least one isolation structure 103 is located between the first active region 101 and the second active region 102. between. The isolation structure 103 can isolate the first active region 101 and the second active region 102, and can prevent the transistors in the first active region 101 from being connected to each other, and can also prevent the transistors in the second active region 102 from being connected to each other. Transistors are interconnected to avoid damage to the transistor structure and improve the reliability of the semiconductor structure.

In this embodiment, the isolation structure is configured as a single-layer structure; in other embodiments, the isolation structure may be configured as a multi-layer structure. For example, the isolation structure can be a silicon oxide-silicon nitride-silicon oxide (Oxide-Nitride-Oxide, ONO) structure. The silicon oxide located on the surface of the substrate can serve as a buffer layer between the silicon nitride and the substrate to avoid Excessive hardness causes dislocation between silicon nitride and the surface of the substrate, improving the performance of the semiconductor structure; silicon nitride has a higher density and can provide better insulation to isolate adjacent transistors. At the same time, silicon nitride has The higher hardness can support the isolation structure and keep the isolation structure in good shape; the outermost layer of silicon oxide can fill the gaps in the isolation structure, making the top surface of the isolation structure flush with the base surface, and at the same time good Insulation properties can isolate adjacent transistors, prevent adjacent transistors from being conductive to each other, and improve the performance of the semiconductor structure.

The semiconductor structure provided by the embodiments of the present disclosure is based on the channel layer covering the substrate surface, and can form a transistor structure with the same channel material in the first active region and the second active region, without the need for different types of transistors. Making a channel area of corresponding materials simplifies the manufacturing process of the channel area in the transistor structure; the first gate is used to form the gate of the transistor structure in the first active area, and the second gate is used to form the second active area. The gate electrode of the transistor structure in the first active area; a first semiconductor layer is embedded in the substrate and the channel layer on both sides of the first gate electrode, which can be used to form the source or drain electrode of the transistor structure in the first active area. A second semiconductor layer is embedded in the substrate and channel layer on both sides of the second gate, which can be used to form the source or drain of the transistor structure in the second active region. The channel layer and the first semiconductor layer can be used to form the source or drain of the transistor structure in the second active region. To improve the carrier mobility of the transistor structure in the first active region, the second semiconductor layer can offset the influence of the channel layer on the carrier mobility of the transistor structure in the second active region, thereby improving the second active region Carrier mobility in medium transistor structures.

Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure to improve the carrier mobility of a transistor. It should be noted that for parts that are the same as or corresponding to the above-mentioned embodiments, reference may be made to the corresponding descriptions of the foregoing embodiments and will not be described in detail below.

2 to 7 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. The details are as follows:

Referring to FIG. 2 , a substrate 100 is provided, and the substrate 100 includes a first active region 101 and a second active region 102 ; a channel layer 200 is formed, and the channel layer 200 covers the entire surface of the substrate 100 .

For the first active area 101 and the second active area 102, in this embodiment, the first active area is a PMOS area, and the second active area is an NMOS area, that is, the first active area is used to form a PMOS tube. , the second active area is used to form an NMOS tube; in other embodiments, the first active area is an NMOS area, and the second active area is a PMOS area, that is, the first active area can be used to form an NMOS tube, and the second active area can be used to form an NMOS tube. Two active areas can be used to form PMOS tubes.

For the channel layer 200, the process of forming the channel layer 200 includes an epitaxial growth process.

In some embodiments, after providing the substrate and before forming the channel layer, ion doping of the substrate is further included. For example, the doping ions may be N-type ions or P-type ions. The N-type ions may be phosphorus ions, arsenic ions or antimony ions; the P-type ions may be boron ions, indium ions or boron fluoride ions.

Referring to FIG. 3 , in some embodiments, after forming the channel layer 200 , the method further includes: forming isolation trenches located in the channel layer 200 and the substrate 100 , and filling the isolation trenches with insulating material to form the isolation structure 103 . The isolation structure 103 can isolate the first active region 101 and the second active region 102, and can prevent the transistors in the first active region 101 from being connected to each other, and can also prevent the transistors in the second active region 102 from being connected to each other. Transistors are interconnected to avoid damage to the transistor structure and improve the reliability of the semiconductor structure.

In some embodiments, the process temperature for forming the isolation structure 103 is: 300°C-600°C. When the material of the channel layer is crystalline silicon germanium, when the temperature for forming the isolation structure is low, the crystal structure of the channel layer can be avoided from being damaged, thereby avoiding the impact on the performance of the transistor structure based on the channel layer and improving the semiconductor structure. stability.

Referring to FIG. 4 , a first gate 210 and a second gate 220 are formed. The first gate 210 is located above the first active region 101 , and the second gate 220 is located above the second active region 102 .

For example, forming the first gate 210 includes: forming a first gate dielectric layer 212, a first gate conductive layer 213 and the first gate spacer layer 211, the first gate dielectric layer 212 is located on the surface of the channel layer 200, the first gate conductive layer 213 covers the surface of the first gate dielectric layer 212, and the first gate spacer layer 211 covers the first gate spacer layer 213. The surface of the gate conductive layer 213 and covers the first gate dielectric layer 212 and the sidewalls of the first gate conductive layer 213; forming the second gate electrode 220 includes: forming the second gate dielectric layer 222, the second gate conductive layer 223 and the The second gate spacer layer 221 and the second gate dielectric layer 222 are disposed on the surface of the channel layer 200. The second gate conductive layer 223 covers the surface of the second gate dielectric layer 222. The second gate spacer layer 221 covers the second gate conductive layer. 223, and covers the second gate dielectric layer 222 and the sidewalls of the second gate conductive layer 223.

Referring to FIG. 5 , an insulating layer 230 is formed to cover and fill the gap between the first gate electrode 210 and the second gate electrode 220 . Forming an insulating layer to cover the first gate and the second gate can prevent subsequent processes from affecting the first gate and the second gate and avoid damage to the semiconductor structure; and in subsequent processes, the first active area can be targeted When performing process operations with the second active area, the structure in the first active area can be protected from the process influence of the second active area, and the structure in the second active area can also be protected from the influence of the first active area. internal process effects.

Referring to FIG. 6 , a first semiconductor layer 214 is formed. The first semiconductor layer 214 is located on both sides of the first gate 210 and is embedded in the channel layer 200 and the substrate 100 . The material of the first semiconductor layer 214 is different from the channel layer 200 The materials are the same.

In some embodiments, the step of forming the first semiconductor layer 214 includes: removing the insulating layer 230 on both sides of the first gate 210 , etching the channel layer 200 on both sides of the first gate 210 , and removing a portion of the substrate 100 To form a first trench; fill the first trench with the first semiconductor material to form the first semiconductor layer 214 .

In some embodiments, filling the first semiconductor material includes: using an epitaxial growth process to form a silicon germanium layer in situ in the first trench. Through the epitaxial growth process, the silicon germanium layer can be uniformly grown on the surface of the substrate in the first trench. At the same time, through in-situ formation, the grown silicon germanium layer can be filled with doping ions to directly form the first silicon germanium layer. The source or drain of the transistor in the active area does not need to be ion implanted and annealed in the subsequent process, thereby avoiding the destruction of the crystal structure due to high-temperature annealing and improving the stability of the semiconductor structure.

Continuing to refer to FIG. 6 , in some embodiments, forming the first semiconductor layer 214 also includes forming a conductive structure 240 . The conductive structure 240 can electrically connect the first semiconductor layer 214 to other devices, thereby connecting the first active region 101 to the first semiconductor layer 214 . The source or drain of the transistor is energized with other devices to facilitate control of the transistor.

Referring to FIG. 7 , a second semiconductor layer 224 is formed. The second semiconductor layer 224 is located on both sides of the second gate 220 and is embedded in the channel layer 200 and the substrate 100 . The material of the second semiconductor layer 224 and the channel The layers are made of different materials.

In some embodiments, the step of forming the second semiconductor layer 224 includes: removing the insulating layer 230 on both sides of the second gate 220 , etching the channel layer 200 on both sides of the second gate 220 , and removing a portion of the substrate 100 To form a second trench; fill the second trench with the second semiconductor material to form the second semiconductor layer 224 .

In some embodiments, filling the second semiconductor material includes: using an epitaxial growth process to form a silicon carbide layer in situ in the second trench. Through the epitaxial growth process, the silicon carbide layer can be uniformly grown on the surface of the substrate in the second trench. At the same time, through in-situ formation, the grown silicon carbide layer can be filled with doping ions to directly form the second active layer. The source or drain of the transistor in the region does not need to be ion implanted and annealed in the subsequent process, thereby avoiding the destruction of the crystal structure due to high-temperature annealing and improving the stability of the semiconductor structure.

Continuing to refer to FIG. 7 , in some embodiments, forming the second semiconductor layer 224 also includes forming a conductive structure 240 . The conductive structure 240 can electrically connect the second semiconductor layer 224 to other devices, thereby connecting the second active region 102 to the second semiconductor layer 224 . The source or drain of the transistor is energized with other devices to facilitate control of the transistor.

The semiconductor structure manufacturing method provided by the embodiment of the present disclosure can form a transistor structure with the same channel material in the first active region and the second active region by forming a channel layer to directly cover the surface of the substrate, without the need for Different types of transistors make channel regions of corresponding materials, which simplifies the manufacturing process of the channel region in the transistor structure; the first gate is used to form the gate of the transistor structure in the first active region, and the second gate is used to form The gate of the transistor structure in the second active area; a first semiconductor layer is embedded in the substrate and channel layer on both sides of the first gate, which can be used to form the source or drain of the transistor structure in the first active area. electrode, a second semiconductor layer is embedded in the substrate and channel layer on both sides of the second gate electrode, which can be used to form the source or drain of the transistor structure in the second active region, the channel layer and the first semiconductor The second semiconductor layer can be used to improve the carrier mobility of the transistor structure in the first active region, and the second semiconductor layer can offset the influence of the channel layer on the carrier mobility of the transistor structure in the second active region, thereby improving the carrier mobility of the transistor structure in the second active region. Carrier mobility of transistor structures in the active region.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and spirit of the present disclosure. scope.

Claims

A semiconductor structure including:

A substrate including a first active region and a second active region;

A channel layer, the channel layer is located on the surface of the substrate;

A first gate and a second gate, the first gate is located above part of the channel layer in the first active region, and the second gate is located above part of the second active region. above the channel layer;

A first semiconductor layer located on both sides of the first gate and embedded in the channel layer and the substrate. The material of the first semiconductor layer is in contact with the channel layer. The materials are the same;

A second semiconductor layer located on both sides of the second gate and embedded in the channel layer and the substrate. The material of the second semiconductor layer is in contact with the channel layer. The materials are different.
The semiconductor structure of claim 1, wherein the material of the channel layer includes crystalline Si 1-x Ge x , where 0.2≤x≤0.3.
The semiconductor structure of claim 2, wherein the germanium element content in the first semiconductor layer is greater than the germanium element content in the channel layer.
The semiconductor structure according to any one of claims 1 to 3, wherein the material of the first semiconductor layer includes Si 1-y Ge y , where 0.3≤y≤0.6.
The semiconductor structure according to any one of claims 1 to 3, wherein the material of the second semiconductor layer includes Si 1-z C z , where 0<z≤0.02.
The semiconductor structure of claim 1, wherein top surfaces of the first semiconductor layer and the second semiconductor layer are both higher than the channel layer, and the first semiconductor layer and the second semiconductor layer The bottom surfaces are lower than the channel layer.
The semiconductor structure of claim 1, further comprising: an isolation structure penetrating the channel layer and located within the substrate, at least one of the isolation structures located in the first active region and the second active area.
The semiconductor structure of claim 1, wherein the first active region is a PMOS region and the second active region is an NMOS region.
A method of manufacturing a semiconductor structure, including:

providing a substrate, the substrate including a first active region and a second active region;

forming a channel layer covering the entire surface of the substrate;

Forming a first gate and a second gate, the first gate is located above the first active area, and the second gate is located above the second active area;

Forming a first semiconductor layer, the first semiconductor layer is located on both sides of the first gate and embedded in the channel layer and the substrate, the material of the first semiconductor layer is in contact with the channel The layers are made of the same material;

A second semiconductor layer is formed. The second semiconductor layer is located on both sides of the second gate and is embedded in the channel layer and the substrate. The material of the second semiconductor layer is in contact with the channel. The layers are made of different materials.
The method of manufacturing a semiconductor structure according to claim 9, wherein after forming the channel layer, further comprising: forming an isolation trench, the isolation trench being located in the channel layer and the substrate, in the The isolation trench is filled with insulating material to form an isolation structure.
The method of manufacturing a semiconductor structure according to claim 10, wherein the process temperature for forming the isolation structure is: 300°C-600°C.
The method of manufacturing a semiconductor structure according to claim 9, wherein the step of forming the first semiconductor layer includes etching the channel layer on both sides of the first gate and removing part of the substrate To form a first trench; and fill the first trench with a first semiconductor material to form the first semiconductor layer.
The method of manufacturing a semiconductor structure according to claim 12, wherein filling the first semiconductor material includes: using an epitaxial growth process to form a silicon germanium layer in situ in the first trench.
The method of manufacturing a semiconductor structure according to claim 9, wherein the step of forming the second semiconductor layer includes etching the channel layer on both sides of the second gate and removing part of the substrate To form a second trench; and fill the second trench with a second semiconductor material to form the second semiconductor layer.
The method of manufacturing a semiconductor structure according to claim 14, wherein filling the second semiconductor material includes: forming a silicon carbide layer in-situ in the second trench using an epitaxial growth process.