CN117153865B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN117153865B CN117153865B CN202311421839.8A CN202311421839A CN117153865B CN 117153865 B CN117153865 B CN 117153865B CN 202311421839 A CN202311421839 A CN 202311421839A CN 117153865 B CN117153865 B CN 117153865B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0882—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, which belong to the technical field of semiconductors, wherein the semiconductor device comprises: a substrate; the gate dielectric layer is arranged on the substrate; the grid electrode is arranged on the grid dielectric layer and comprises a first grid electrode structure and a second grid electrode structure, the second grid electrode structure is arranged on the grid dielectric layer, the first grid electrode structure is arranged on the second grid electrode structure, and the width of the second grid electrode structure is larger than that of the first grid electrode structure; the first side wall structures are arranged on two sides of the first grid structure and are positioned on the second grid structure; the second side wall structure is arranged on the side walls of the first side wall and the second grid structure; the drain electrode is arranged in the substrate at one side of the side wall structure; the source electrode is arranged in the substrate at the other side of the side wall structure; the lightly doped region is arranged in the substrate at one side of the grid electrode close to the source electrode. The semiconductor device and the manufacturing method thereof can improve the performance of the semiconductor device and reduce the production cost.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
Metal-Oxide-semiconductor field effect transistors (MOSFETs) are one of the most basic devices in semiconductor fabrication, widely used in various chips, and are classified into NMOS and PMOS transistors according to the carrier and doping type at the time of fabrication. The MOS transistor has characteristics of high input impedance, low noise, large dynamic range, small power consumption, easy integration, and the like, and can be used as an amplifying circuit, a voltage-controlled element, an electronic switch, or controllable rectification in a chip, and the like, and is of great importance. In the use process of the MOS transistor, in order to achieve better power performance, the MOS transistor is required to have higher withstand voltage capability. However, in the process of improving the voltage withstand capability of the MOS transistor, the contact resistance of the drain is easily increased, and thus the turn-on current of the MOS transistor is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, and the semiconductor device and the manufacturing method thereof can obtain a semiconductor device with low resistance and high voltage resistance, improve the breakdown voltage of the semiconductor device and improve the performance of the semiconductor device.
In order to solve the above technical problems, the present invention provides a semiconductor device, at least comprising:
a substrate;
the gate dielectric layer is arranged on the substrate;
the grid electrode is arranged on the grid dielectric layer and comprises a first grid electrode structure and a second grid electrode structure, the second grid electrode structure is arranged on the grid dielectric layer, the first grid electrode structure is arranged on the second grid electrode structure, and the width of the second grid electrode structure is larger than that of the first grid electrode structure;
the first side wall structure is arranged on two sides of the first grid structure and is positioned on the second grid structure;
the second side wall structure is arranged on the side walls of the first side wall and the second grid structure;
the drain electrode is arranged in the substrate at one side of the side wall structure;
the source electrode is arranged in the substrate at the other side of the side wall structure; and
and the lightly doped region is arranged in the substrate at one side of the grid electrode close to the source electrode and is not arranged in the substrate at one side of the grid electrode close to the drain electrode.
In an embodiment of the present invention, the first sidewall and the second sidewall are implanted with a first type of ions, where the first type of ions includes fluorine ions.
In an embodiment of the present invention, a width of the second gate structure is 1.8 times to 2.2 times that of the first gate structure.
In an embodiment of the present invention, the height of the second gate structure is 10% -20% of the height of the gate.
In one embodiment of the present invention, the semiconductor device further includes a conductive plug disposed on the drain, the first gate structure is located at a first distance d1 from the conductive plug, and the second gate structure is located at a second distance d2 from the conductive plug, wherein d1/d2 is greater than or equal to 1.4 and less than or equal to 1.7.
The invention also provides a manufacturing method of the semiconductor device, which at least comprises the following steps:
providing a substrate;
forming a gate dielectric layer on the substrate;
forming a grid electrode on the grid dielectric layer, wherein the grid electrode comprises a first grid electrode structure and a second grid electrode structure, the second grid electrode structure is arranged on the grid dielectric layer, the first grid electrode structure is arranged on the second grid electrode structure, and the width of the second grid electrode structure is larger than that of the first grid electrode structure;
forming first side wall structures on two sides of the first grid structure, wherein the first side wall structures are positioned on the second grid structure;
forming a second side wall structure on the side walls of the first side wall and the second grid structure;
forming a drain electrode in the substrate at one side of the side wall structure, wherein a lightly doped region is not arranged in the substrate at one side of the gate electrode, which is close to the drain electrode; and
and forming a source electrode in the substrate at the other side of the side wall structure, wherein a lightly doped region is formed in the substrate, which is close to one side of the source electrode, of the gate electrode.
In an embodiment of the present invention, the manufacturing method further includes:
forming a gate dielectric layer and a first gate material layer on the substrate;
forming a second gate material layer on the gate dielectric layer and on the side wall and the top of the first gate material layer;
forming a first dielectric layer on the second gate material layer;
performing first type ion implantation on the first dielectric layer to form a first side wall dielectric layer; and
and etching part of the first side wall dielectric layer and the second gate material layer to form the first gate structure, the second gate structure and the first side wall.
In an embodiment of the present invention, the method for manufacturing the sidewall structure includes:
forming a second dielectric layer on the grid electrode and the first side wall after forming the first side wall;
performing first type ion implantation on the second dielectric layer to form a second side wall dielectric layer; and
and etching part of the second side wall dielectric layer to form a side wall structure.
In an embodiment of the present invention, the method for manufacturing the source electrode and the drain electrode includes:
after the side wall structure is formed, placing the substrate into ion implantation equipment;
performing second type ion implantation in an inclined ion implantation mode to form a first lightly doped region and a second lightly doped region;
in the ion implantation device, the ion implantation angle is changed, heavy doping is performed in a manner of being perpendicular to the substrate, the source electrode and the drain electrode are formed, the source electrode and the first lightly doped region are located on the same side of the grid electrode and are partially overlapped, and the drain electrode covers the second lightly doped region.
In an embodiment of the present invention, when the first lightly doped region is formed by implantation, an edge of the first lightly doped region is aligned with a side edge of the second gate structure adjacent to the first lightly doped region.
In summary, the present invention provides a semiconductor device and a method for manufacturing the same, which have the unexpected technical effect of reducing the dielectric constant of the sidewall structure, thereby reducing the parasitic capacitance from the gate to the drain conductive plug; the working frequency is improved, the resistance-capacitance delay effect can be reduced, and the service life of the instability of the negative bias temperature is improved; an inversion layer with increased width can be formed on the surface of the substrate, so that the starting resistance is reduced, and the starting current of the semiconductor device is improved; the manufacturing process can be simplified, the manufacturing procedure can be reduced, the production efficiency of enterprises can be improved, and the production cost can be reduced; the voltage withstand capability of the semiconductor device can be improved, the channel resistance can be reduced, the on-resistance can be reduced, the semiconductor device with low resistance and high voltage withstand can be obtained, the breakdown voltage of the semiconductor device can be improved, and the performance of the semiconductor device can be improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a substrate distribution in an embodiment.
Fig. 2 is a schematic diagram illustrating formation of a first gate material layer in an embodiment.
Fig. 3 is a schematic diagram illustrating formation of a second gate material layer and a first dielectric layer in an embodiment.
FIG. 4 is a schematic diagram illustrating formation of a first sidewall dielectric layer according to one embodiment.
Fig. 5 is a schematic diagram of a first sidewall, a first gate structure and a second gate structure formed in an embodiment.
Fig. 6 is a schematic diagram illustrating formation of a second sidewall dielectric layer in an embodiment.
Fig. 7 is a schematic diagram illustrating formation of a sidewall structure in an embodiment.
FIG. 8 is a schematic diagram of forming lightly doped regions in an embodiment.
FIG. 9 is a schematic diagram of forming a source and a drain in one embodiment.
Fig. 10 is a schematic diagram of salicide formation in one embodiment.
Fig. 11 is a schematic diagram of a semiconductor device in an embodiment.
Description of the reference numerals:
10. a substrate; 11. a pad oxide layer; 12. pad nitriding layer; 13. patterning the photoresist layer; 131. a first opening; 14. shallow trench isolation structures; 15. a gate dielectric layer; 16. a first gate material layer; 17. a second gate material layer; 18. a first dielectric layer; 191. a first sidewall dielectric layer; 192. a second side wall dielectric layer; 20. a first gate structure; 21. a second gate structure; 22. a side wall structure; 221. a first side wall; 222. a second side wall; 231. a first lightly doped region; 232. a second lightly doped region; 241. a source electrode; 242. a drain electrode; 25. self-aligned silicide; 26. an interlayer dielectric layer; 27. a first conductive plug; 28. a second conductive plug; 29. and a third conductive plug.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Referring to fig. 11, the present invention provides a semiconductor device, such as a MOS transistor, wherein the semiconductor device includes a gate, the gate includes a first gate structure 20 and a second gate structure 21, the second gate structure 21 is located on a substrate 10, the first gate structure 20 is located on the second gate structure 21, and a width of the second gate structure 21 is greater than a width of the first gate structure 20. The sidewall structures 22 are disposed on both sides of the gate electrode, and the source electrode 241 and the drain electrode 242 are disposed on both sides of the sidewall structures 22, wherein a lightly doped region is disposed on one side of the source electrode 241. By providing the second gate structure 21 and the lightly doped region, the breakdown voltage of the semiconductor device can be increased, while the on-current of the semiconductor device can be increased, and the performance of the semiconductor device can be improved. In this application, a method for fabricating a semiconductor device is also provided, and the fabrication of the semiconductor device in a specific embodiment is described in detail below.
Referring to fig. 1, in one embodiment of the present invention, a material of a substrate 10 is, for example, undoped monocrystalline silicon or doped monocrystalline silicon. In the present embodiment, the substrate 10 is single crystal silicon doped with impurities, and the type of impurities in the substrate 10 may be set according to the type of semiconductor device. The N-type semiconductor device can be selected from a P-type semiconductor substrate, and the P-type semiconductor device can be selected from an N-type semiconductor substrate. In other embodiments, depending on the semiconductor device, the substrate 10 may be selected from silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, or other III/V compound semiconductor materials, and the like, and may include a stacked structure of these semiconductor materials, or may be silicon on insulator, silicon on insulator stacked, silicon germanium on insulator, or the like.
Referring to fig. 1 to 2, in an embodiment of the present invention, shallow trench isolation structures (Shallow Trench Isolation, STI) 14 are further disposed in the substrate 10. Shallow trench isolation structures 14 are provided between adjacent semiconductor devices. Specifically, the pad oxide layer 11 is formed on the substrate 10, and the pad oxide layer 11 is made of a material such as dense silicon oxide, and the pad oxide layer 11 is prepared by a thermal oxidation method, an In-situ vapor growth method (In-Situ Steam Generation, ISSG), a chemical vapor deposition (Chemical Vapor Deposition, CVD), or the like. The thickness of the pad oxide layer 11 is, for example, 20nm to 40nm. A pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, a silicon nitride layer, and the pad nitride layer 12 is formed by, for example, chemical vapor deposition or the like. The thickness of the pad nitride layer 12 is, for example, 50nm to 90nm. In the process of forming the shallow trench isolation structure 14, the pad oxide layer 11 is used for buffering stress in the nitride layer 12, so that defects caused by the stress to the substrate 10 are avoided, and meanwhile, the pad oxide layer is used as a stop layer when the pad nitride layer 12 is etched and removed.
Referring to fig. 1 to 2, in an embodiment of the invention, a photoresist layer is formed on the pad nitride layer 12, and a patterned photoresist layer 13 is formed through an exposure and development process, wherein a plurality of first openings 131 are disposed on the patterned photoresist layer 13, the first openings 131 are used for defining the positions of the shallow trench isolation structures 14, and the pad nitride layer 12 is exposed by the first openings 131. Shallow trenches (not shown) are formed by etching the patterned photoresist layer 13 in the direction of the substrate 10, for example, by dry etching, and the etching gas includes, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr), etc. An isolation medium, such as an insulating material, for example, silicon oxide, is deposited within the shallow trench, for example, by high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the isolation medium deposition is completed, the isolation medium and the pad nitride layer 12 are planarized, for example, by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process, and then the pad nitride layer 12 is removed to form the shallow trench isolation structure 14, wherein the shallow trench isolation structure 14 is higher than the pad oxide layer 11, and the height difference is determined according to the manufacturing requirements.
Referring to fig. 1-2, in one embodiment of the present invention, after forming the shallow trench isolation structure 14, a first gate material layer 16 is formed on the substrate 10. Specifically, the pad oxide layer 11 on the substrate 10 is removed first. The pad oxide layer 11 is removed, for example, by wet etching, and the etching solution is, for example, a buffer oxide etching solution or dilute hydrofluoric acid, etc., and the shallow trench isolation structure 14 on the substrate 10 is also etched during the etching process of the pad oxide layer 11, and the height difference between the shallow trench isolation structure 14 and the pad oxide layer 11 is transferred between the shallow trench isolation structure 14 and the substrate 10. After removing the pad oxide layer 11, a gate dielectric layer 15 is formed on the substrate 10, and a surface of the gate dielectric layer 15 is flush with a surface of the shallow trench isolation structure 14, for example. The gate dielectric layer 15 is, for example, silicon oxide or silicon oxynitride, and has a thickness of, for example, 5nm to 10nm, and the gate dielectric layer 15 is formed by, for example, thermal oxidation or in-situ vapor growth. A first gate material layer 16 is formed on the gate dielectric layer 15, and a material of the first gate material layer 16 is, for example, polysilicon or a metal material. In this embodiment, the first gate material layer 16 is polysilicon, and the work function of the polysilicon can be adjusted by N-type or P-type doping, so that the MOS device obtains a suitable threshold voltage. And etching the first gate material layer 16, for example, etching the first gate material layer 16 by dry etching, and reserving the first gate material layer 16 in the middle of the adjacent shallow trench isolation structure 14, wherein the width of the remaining first gate material layer 16 is 40 nm-180 nm, and the height of the first gate material layer 16 is 100 nm-300 nm, which is specifically selected according to the manufacturing requirement.
Referring to fig. 2 to 3, in an embodiment of the present invention, after etching the first gate material layer 16, a second gate material layer 17 is formed on the substrate 10, and the second gate material layer 17 covers the top and the sidewall of the first gate material layer 16, the gate dielectric layer 15 and the shallow trench isolation structure 14. The thickness of the second gate material layer 17 is, for example, 10% -20% of the thickness of the first gate material layer 16. And forming a first dielectric layer 18 on the second gate material layer 17, wherein the thickness of the first dielectric layer 18 is, for example, 80% -140% of the width of the remaining first gate material layer 16, and is, for example, equal to the width of the first gate material layer 16, and the first dielectric layer 18 covers the surface of the second gate material layer 17 and the side wall of the first gate material layer 16. The second gate material layer 17 is, for example, polysilicon or a metal material. In this embodiment, the second gate material layer 17 is polysilicon doped with ions, and the ion-doped type thereof can be set according to the type of the semiconductor device. The N-type semiconductor device may be selectively doped with N-type ions, the P-type semiconductor device may be selectively doped with P-type ions, and the second gate material layer 17 may be obtained by chemical vapor deposition, for example. The first dielectric layer 18 is, for example, a silicon oxide layer, for example, obtained by chemical vapor deposition.
Referring to fig. 3 to 4, in an embodiment of the present invention, after forming the first dielectric layer 18, a first type ion implantation is performed on the entire semiconductor region to dope the first dielectric layer 18, so as to form a first sidewall dielectric layer 191. In the present embodiment, the first type of ions implanted into the first dielectric layer 18 include fluorine ions, for example, and the dose of the ion implantation of fluorine ions is 5×10, for example 15 ions/cm 2 ~1×10 16 ions/cm 2 The implantation energy is, for example, 10KeV to 50KeV. In the first type ion implantation process, the first type ion implantation direction is as indicated by the arrow in fig. 4, i.e., the ion implantation direction is perpendicular to the substrate 10. The photoresist layer is not arranged in the whole semiconductor region, and the first type ions are uniformly injected into the first dielectric layer 18, so that the photomask process can be reduced, and the cost can be reduced. The first sidewall dielectric layer 191 can be formed by the first type ion implantation to form the first sidewall dielectric layer 191 having a low dielectric constant, thereby reducing parasitic capacitance of the gate-to-drain side conductive plugs in the semiconductor device, and thus reducing resistance-capacitance Delay (RC-Delay). And fluorine ions can diffuse to the interface of the gate dielectric layer 15 and the substrate 10 to passivate the silicon dangling bonds, improving the lifetime of the negative bias temperature instability (Negative bias temperature instability NBTI).
Referring to fig. 4 to 5, in an embodiment of the invention, after forming the first sidewall dielectric layer 191, the first sidewall dielectric layer 191 and the second gate material layer 17 are etched to form the first sidewall 221 and the gate. Specifically, the shallow trench isolation structure 14, the first gate material layer 16, and the first sidewall dielectric layer 191 and the second gate material layer 17 on a part of the substrate are selectively removed, for example, by dry etching, so that the first sidewall dielectric layer 191 and the second gate material layer 17 on both sides of the first gate material layer 16 remain. The gate includes a first gate structure 20 and a second gate structure 21, in this embodiment, the second gate material layer 17 on the gate oxide layer 15 and the first gate material layer 16 flush with the second gate material layer 17 are defined as a second gate structure 21, and the first gate material layer 16 on the second gate structure 21 and the second gate material layer 17 on both sides of the first gate material layer 16 are defined as a first gate structure 20. The remaining first sidewall dielectric layer 191 on the second gate structure 21 is defined as the first sidewall 221, i.e., the first sidewall 221 is located on both sides of the first gate structure 20 and is located on the second gate structure 21.
Referring to fig. 5, in an embodiment of the present invention, after etching the first sidewall dielectric layer 191 and the second gate material layer 17, the gate dielectric layer 15 in the region outside the gate is etched by changing the etching gas. In this embodiment, the height of the gate electrode is 100nm to 300nm, and the height of the second gate structure 21 is 10% to 20% of the height of the gate electrode. The width of the first gate structure 20 is the sum of the width of the remaining first gate material layer 16 and the thickness of the second gate material layers 17 on both sides, and the width of the second gate structure 21 is, for example, 1.8 times to 2.2 times, for example, 2 times the width of the first gate structure 20. The second gate structure 21 is connected to the first gate structure 20, and when a voltage is applied to the gate, the second gate structure 21 can form an inversion layer on the surface of the substrate below the second gate structure, so that the on-resistance can be reduced, and the on-current of the device can be improved. I.e., by forming the second gate structure 21 with a larger width, to improve the performance of the semiconductor device.
Referring to fig. 5 to fig. 6, in an embodiment of the present invention, after forming the gate, a second sidewall dielectric layer 192 is formed on the gate, the first sidewall 221, the substrate 10 and the shallow trench isolation structure 14. Specifically, a second dielectric layer (not shown) is formed, and a first type ion doping is performed on the second dielectric layer to form a second sidewall dielectric layer 192. In this embodiment, the first type of ions implanted into the second dielectric layer include fluorine ions, for example, and the ion implantation dose of fluorine ions is 5×10, for example 15 ions/cm 2 ~1×10 16 ions/cm 2 The implantation energy is, for example, 10KeV to 50In the present embodiment, the implantation dose of the first type ion in the second sidewall dielectric layer 192 may be equal to or different from the implantation dose of the first type ion in the first sidewall 221, which is not specifically limited in the present invention. During the first type of ion implantation, the ion implantation direction is perpendicular to the substrate 10. The whole semiconductor region is not provided with a photoresist layer, and the first type ions are uniformly implanted into the second dielectric layer. The second sidewall dielectric layer 192 is formed by the first type ion implantation, so that the second sidewall dielectric layer 192 with low dielectric constant can be formed, thereby reducing parasitic capacitance from the gate to the drain side conductive plug in the semiconductor device.
Referring to fig. 6 to fig. 7, in an embodiment of the present invention, after forming the second sidewall dielectric layer 192, the second sidewall dielectric layer 192 is etched to form a second sidewall 222. Specifically, the shallow trench isolation structure 14, the first gate structure 20 and the second sidewall dielectric layer 192 on a portion of the substrate 10 are selectively removed, for example, by dry etching, so as to retain the first sidewall 221 and the second sidewall dielectric layer 192 on both sides of the second gate structure 21. I.e., the second sidewall 222 is located on the sidewalls of the first sidewall 221 and the second gate structure 21, and is located on the substrate 10. In this embodiment, the sidewall structure 22 includes the second sidewall 222 and the first sidewall 221, and the material of the sidewall structure 22 is a low dielectric constant material, so that parasitic capacitance from the gate to the drain side conductive plug in the semiconductor device can be reduced. In other embodiments, the second sidewall dielectric layer 192 of the stacked material may be formed, thereby forming a stacked sidewall structure, which is specifically selected according to the manufacturing requirements.
Referring to fig. 7 to 8, in an embodiment of the present invention, after forming the sidewall structure 22, ion implantation is performed on the substrate 10 to form a doped region. Specifically, the substrate 10 is placed in an ion implantation apparatus, and the second type ion implantation is performed by means of inclined ion implantation at both sides of the gate electrode as shown by arrow directions in fig. 8, and the first lightly doped region 231 and the second lightly doped region 232 are formed due to the blocking effect of the gate electrode. The first lightly doped region 231 is located in the substrate at one side of the gate, and extends from the substrate 10 to the edge of the second gate structure 21 away from the first gate structure 20, i.e. the edge of the first lightly doped region 231 is aligned with the side of the second gate structure 20 near the first lightly doped region 231. The second lightly doped region 232 is located in the substrate 10 at the other side of the gate, and one end of the second lightly doped region 232 contacts the shallow trench isolation structure 14, and due to the blocking effect of the gate, a distance exists between the sidewall structure 22 and the shallow trench isolation structure 14, i.e. between the other end of the second lightly doped region 232 and the sidewall structure 22. The angle between the ion implantation direction and the substrate surface is defined as the implantation angle of the ions, and the implantation angle is, for example, 50-60 degrees. The extent of overlap of the first lightly doped region 231 and the gate electrode is controlled by controlling the implantation angle.
Referring to fig. 8, in one embodiment of the present invention, during the formation of the doped region, the second type of ion is implanted, for example, as an N-type impurity or a P-type impurity, and is opposite to the doping type of the substrate 10. When the semiconductor device is an N-type semiconductor device, the second type ions implanted in the first and second lightly doped regions 231 and 232 are N-type impurities such As phosphorus (P) or arsenic (As), and when the semiconductor device is a P-type semiconductor device, the second type ions implanted in the first and second lightly doped regions 231 and 232 are P-type impurities such As boron (B) or gallium (Ga). In the present embodiment, the implantation dose of the second type ions in the first lightly doped region 231 and the second lightly doped region 232 is, for example, 5×10 13 ions/cm 2 ~1×10 14 ions/cm 2 The implantation energy of the second type of ions is, for example, 10KeV to 20KeV.
Referring to fig. 8 to 9, in an embodiment of the present invention, after forming the first lightly doped region 231 and the second lightly doped region 232, the ion implantation angle is changed, and as shown by the arrow direction in fig. 9, heavy doping is performed in a manner perpendicular to the substrate 10, so as to form the source electrode 241 and the drain electrode 242. Wherein the first gate structure 20 is also doped during the formation of the source 241 and the drain 242. In this embodiment, the source 241 and the drain 242 are located within the substrate 10 between the sidewall structures 22 and the shallow trench isolation structures 14. Wherein the ion implantation type is not changed, i.e. the ions implanted in the source 241 and the drain 242 are of the second type and the ions of the second type in the source 241 and the drain 242The implantation dose being, for example, 2X 10 15 ions/cm 2 ~5×10 15 ions/cm 2 The implantation energy for forming the source 241 and the drain 242 is, for example, 20KeV to 50KeV. I.e., the doping depth of the source 241 and the drain 242 is greater than the doping depth of the first and second lightly doped regions 231 and 232. By carrying out the light doping region and the heavy doping in the same equipment, the process can be completed by only changing the injection condition, the manufacturing process can be simplified, the manufacturing procedure can be reduced, the production efficiency of enterprises can be improved, and the production cost can be reduced.
Referring to fig. 9, in an embodiment of the invention, the source 241 and the first lightly doped region 231 are located on the same side of the gate, and the source 241 does not completely cover the first lightly doped region 231, so that the lightly doped region is disposed on the source side in the final semiconductor device. The drain 242 and the second lightly doped region 232 are located on the same side of the gate, and the drain 242 completely covers the second lightly doped region 232 and is implanted to a depth and dose greater than the second lightly doped region 232, so that in the final semiconductor device, the lightly doped region is only disposed in the substrate 10 on the side of the gate adjacent to the source 241 and not disposed in the substrate 10 on the side of the gate adjacent to the drain 242. By not providing the lightly doped region on the drain side, the withstand voltage capability of the MOS transistor can be improved, while the second gate structure 21 can reduce on-resistance to prevent an increase in resistance due to the absence of the lightly doped region on the drain side, and thus, a low-resistance high-withstand voltage MOS transistor can be obtained.
Referring to fig. 9, in one embodiment of the present invention, after forming the source 241 and the drain 242, the substrate 10 is subjected to a rapid thermal annealing process (Rapid Thermal Anneal, RTA). The annealing temperature is, for example, 1000 ℃ to 1200 ℃, the annealing time is, for example, 0.5h to 2h, and the annealing process is performed under a stable gas atmosphere, for example, under a nitrogen atmosphere. The doping ions in the source electrode 241, the drain electrode 242 and the first lightly doped region 231 are activated through an annealing process, repairing lattice damage. During the annealing process, the dopant ions in the first lightly doped region 231 may diffuse under the second gate structure 21, and the diffusion distance is small, which is not shown in the drawings.
Referring to fig. 9 to 10, in an embodiment of the present invention, after forming the source electrode 241 and the drain electrode 242, a Self-Aligned Block (SAB) 25 is formed on the gate electrode, the source electrode 241 and the drain electrode 242, i.e., the Self-Aligned silicide 25 covers the top of the gate electrode, the source electrode 241 and the drain electrode 242. The salicide 25 is, for example, a metal silicide such as nickel silicide (NiSi) or cobalt silicide (CoSi), so as to reduce the contact resistance between the subsequent metal line and the semiconductor device. Specifically, a metal material, such as titanium, cobalt or nickel, is deposited on the substrate 10 and the gate electrode, and reacts with silicon in the substrate 10 and the gate electrode by means of a rapid annealing process to form a metal silicide, and finally, unreacted metal material is removed to form the salicide 25.
Referring to fig. 10 to 11, in an embodiment of the present invention, after forming the salicide 25, an interlayer dielectric layer 26 is formed on the salicide 25, and the interlayer dielectric layer 26 covers the surface of the substrate 10. In this embodiment, the interlayer dielectric layer 26 may be formed on the substrate 10 by, for example, high-density plasma chemical vapor deposition, the thickness of the interlayer dielectric layer 26 is, for example, 500nm to 800nm, and the material of the interlayer dielectric layer 26 is, for example, silicon dioxide or the like. A plurality of openings (not shown) are formed in interlayer dielectric 26 in communication with salicide 25, and a conductive material is deposited in the openings, such as by a deposition process, for example, a metal material, such as a titanium/titanium nitride barrier layer and tungsten, is deposited in the openings to form conductive plugs. The conductive plugs include a first conductive plug 27, a second conductive plug 28 and a third conductive plug 29, wherein the first conductive plug 27 is disposed on the source 241 and is connected to the salicide 25 on the source 241, the second conductive plug 28 is disposed on the gate and is connected to the salicide 25 on the gate, and the third conductive plug 29 is disposed on the drain 242 and is connected to the salicide 25 on the drain 242. By arranging a plurality of conductive plugs, the connection between the semiconductor device and a subsequent circuit is facilitated.
Referring to fig. 11, in an embodiment of the present invention, when a voltage is applied to the gate electrode, the second gate structure 21 can form an inversion layer on the surface of the substrate below the second gate structure, so as to reduce the on-resistance and facilitate the improvement of the on-current of the semiconductor device. Wherein the width d3 of the inversion layer is equal to the width of the second gate structure 21, i.e. an inversion layer of increased width is formed. The distance from the first gate structure 20 to the third conductive plug 29 is defined as a first distance d1, the distance from the inversion layer to the third conductive plug 29, i.e., the distance from the second gate structure 21 to the third conductive plug 29 is defined as a second distance d2, and d1> d2, i.e., the distance from the first gate structure 20 to the third conductive plug 29 is increased, so that parasitic capacitance therebetween can be reduced. The invention is not limited to the relationship between d1 and d2, in one embodiment of the invention, 1.4.ltoreq.d1/d2.ltoreq.1.7. And the dielectric constant of the side wall structure 22 is reduced by the doping of the first type ions, so that the parasitic capacitance from the grid electrode to the drain electrode side conductive plug in the semiconductor device is reduced, and the working frequency is improved. After the sidewall structure 22 is formed, the lightly doped region is formed only on the source side and is not formed on the drain side in the semiconductor device by utilizing the inclined ion implantation mode, so that the breakdown voltage of one end of the drain is improved, the pressure resistance of the semiconductor device is improved, and the quality of the semiconductor device is improved.
In summary, the invention provides a semiconductor device and a method for manufacturing the same, which have the unexpected technical effects that the side wall structure is formed by ion implantation, so that the dielectric constant of the side wall structure can be reduced, the parasitic capacitance from the grid electrode to the drain electrode conductive plug can be reduced, the working frequency can be increased, the resistance-capacitance delay effect can be reduced, and the service life of the negative bias temperature instability can be improved; by arranging the second grid structure with larger width, an inversion layer with increased width can be formed on the surface of the substrate, so that the starting resistance can be reduced, and the starting current of the device can be improved; by carrying out the light doping region and the heavy doping in the same equipment, the manufacturing process can be simplified, the manufacturing procedure can be reduced, the production efficiency of enterprises can be improved, and the production cost can be reduced; by not arranging the lightly doped region at one side of the drain, the voltage withstand capability of the semiconductor device can be improved, the channel resistance can be reduced, the on-resistance can be reduced, the semiconductor device with low resistance and high voltage withstand capability can be obtained, the breakdown voltage of the semiconductor device can be improved, and the performance of the semiconductor device can be improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (9)
1. A semiconductor device, comprising at least:
a substrate;
the gate dielectric layer is arranged on the substrate;
the grid electrode is arranged on the grid dielectric layer and comprises a first grid electrode structure and a second grid electrode structure, the second grid electrode structure is arranged on the grid dielectric layer, the first grid electrode structure is arranged on the second grid electrode structure, and the width of the second grid electrode structure is larger than that of the first grid electrode structure;
the side wall structures are arranged on two sides of the grid electrode, and comprise first side walls which are arranged on two sides of the first grid electrode structure and are positioned on the second grid electrode structure;
the side wall structure comprises a second side wall which is arranged on the side walls of the first side wall and the second grid structure, first type ions are implanted into the first side wall and the second side wall, and the first type ions comprise fluorine ions;
the drain electrode is arranged in the substrate at one side of the side wall structure;
the source electrode is arranged in the substrate at the other side of the side wall structure; and
and the lightly doped region is arranged in the substrate at one side of the grid electrode close to the source electrode and is not arranged in the substrate at one side of the grid electrode close to the drain electrode.
2. The semiconductor device of claim 1, wherein a width of the second gate structure is 1.8-2.2 times a width of the first gate structure.
3. The semiconductor device of claim 1, wherein a height of the second gate structure is 10% -20% of a height of the gate.
4. The semiconductor device of claim 1, further comprising a conductive plug disposed on the drain, wherein the first gate structure is a first distance d1 from the conductive plug and the second gate structure is a second distance d2 from the conductive plug, 1.4 ∈d1/d2 ∈1.7.
5. A method of fabricating a semiconductor device, comprising at least the steps of:
providing a substrate;
forming a gate dielectric layer on the substrate;
forming a grid electrode on the grid dielectric layer, wherein the grid electrode comprises a first grid electrode structure and a second grid electrode structure, the second grid electrode structure is arranged on the grid dielectric layer, the first grid electrode structure is arranged on the second grid electrode structure, and the width of the second grid electrode structure is larger than that of the first grid electrode structure;
forming side wall structures on two sides of the grid electrode, wherein the forming step of the side wall structures comprises the steps of forming first side walls on two sides of the first grid electrode structure, and the first side walls are located on the second grid electrode structure;
the forming step of the side wall structure comprises the steps of forming a second side wall on the side walls of the first side wall and the second grid structure, wherein first type ions are implanted into the first side wall and the second side wall, and the first type ions comprise fluorine ions;
forming a drain electrode in the substrate at one side of the side wall structure, wherein a lightly doped region is not arranged in the substrate at one side of the gate electrode, which is close to the drain electrode; and
and forming a source electrode in the substrate at the other side of the side wall structure, wherein a lightly doped region is formed in the substrate, which is close to one side of the source electrode, of the gate electrode.
6. The method of manufacturing a semiconductor device according to claim 5, further comprising:
forming a gate dielectric layer and a first gate material layer on the substrate;
forming a second gate material layer on the gate dielectric layer and on the side wall and the top of the first gate material layer;
forming a first dielectric layer on the second gate material layer;
performing first type ion implantation on the first dielectric layer to form a first side wall dielectric layer, wherein the first type ions comprise fluorine ions; and
and etching part of the first side wall dielectric layer and the second gate material layer to form the first gate structure, the second gate structure and the first side wall.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the method for manufacturing a sidewall structure comprises:
forming a second dielectric layer on the grid electrode and the first side wall after forming the first side wall;
performing first type ion implantation on the second dielectric layer to form a second side wall dielectric layer; and
and etching part of the second side wall dielectric layer to form a side wall structure.
8. The method of manufacturing a semiconductor device according to claim 5, wherein the method of manufacturing the source electrode and the drain electrode comprises:
after the side wall structure is formed, placing the substrate into ion implantation equipment;
performing second type ion implantation in an inclined ion implantation mode to form a first lightly doped region and a second lightly doped region;
in the ion implantation device, the ion implantation angle is changed, heavy doping is performed in a manner of being perpendicular to the substrate, the source electrode and the drain electrode are formed, the source electrode and the first lightly doped region are located on the same side of the grid electrode and are partially overlapped, and the drain electrode covers the second lightly doped region.
9. The method of claim 8, wherein an edge of the first lightly doped region is aligned with a side of the second gate structure adjacent to the first lightly doped region when the first lightly doped region is implanted.
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| US7732310B2 (en) * | 2006-12-05 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sidewall memory with self-aligned asymmetrical source and drain configuration |
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| US6344396B1 (en) * | 1999-09-24 | 2002-02-05 | Advanced Micro Devices, Inc. | Removable spacer technology using ion implantation for forming asymmetric MOS transistors |
| CN102623314A (en) * | 2012-03-23 | 2012-08-01 | 上海华力微电子有限公司 | Source-drain lightly-doping method, semiconductor device and manufacturing method thereof |
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| CN117153865A (en) | 2023-12-01 |
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