JP2009152462A - Nitride semiconductor element and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor element which is reduced in on-state resistance, and to provide a method of manufacturing the same. <P>SOLUTION: The nitride semiconductor element includes a nitride semiconductor laminate structure portion 2 having an n-type layer 3, a p-type layer 4, and an n-type layer 5. The nitride semiconductor laminate structure portion 2 has a trench 6 formed thereon. An n-type channel layer 8 is formed to cover the entire area of a wall surface 7 of the trench 6. In the trench 6, a p-type gate layer 9 made of GaN containing a p-type impurity is buried inside the n-type channel layer 8, and a gate electrode 10 is formed on an outermost surface 15 of the p-type gate layer 9. Further, a source electrode 11 is formed on an outermost surface 16 of the n-type layer 5, and a drain electrode 12 is formed on the other surface of the substrate 1 in contact. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device made of a group III nitride semiconductor and a method for manufacturing the same.

Conventionally, power devices using silicon semiconductors are used in power amplifier circuits, power supply circuits, motor drive circuits, and the like.
However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of nitride semiconductor devices having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and low on-resistance has been studied.

FIG. 3 is a schematic cross-sectional view for explaining the structure of a conventional nitride semiconductor device.
The nitride semiconductor element includes a substrate 81 and a stacked structure portion 93 stacked on the substrate 81.
The stacked structure unit 93 includes an undoped GaN layer 82, an n-type GaN layer 83, a p-type GaN layer 84, and an n-type GaN layer 85 that are sequentially stacked from the substrate 81 side. A wall surface 91 straddling the n-type GaN layer 83, the p-type GaN layer 84, and the n-type GaN layer 85 is formed in the multilayer structure portion 93. A gate insulating film 86 covering the entire wall surface 91 is formed on the surface of the multilayer structure portion 93.

The gate insulating film 86 is formed with an opening 94 and an opening 92 that partially expose the n-type GaN layer 85 and the n-type GaN layer 83, respectively.
A source electrode 88 is electrically connected to the n-type GaN layer 85 exposed from the opening 94. On the other hand, a drain electrode 89 is electrically connected to the n-type GaN layer 83 exposed from the opening 92. A gate electrode 87 is formed on a portion of the gate insulating film 86 facing the wall surface 91.

The source electrode 88, the drain electrode 89, and the gate electrode 87 are insulated from each other by interposing an interlayer insulating film 90 between adjacent electrodes.
Next, the operation of the nitride semiconductor device will be described. For example, first, a bias (reverse bias) in which the drain electrode 89 side becomes positive is applied between the source electrode 88 and the drain electrode 89 (between the source and drain). As a result, a reverse voltage is applied to the interface (pn junction) between the n-type GaN layer 83 and the p-type GaN layer 84, and as a result, between the n-type GaN layer 85 and the n-type GaN layer 83, That is, the source and drain are cut off (reverse bias state).

From this state, when a bias equal to or higher than the gate threshold voltage that is positive with the source electrode 88 as a reference potential is applied to the gate electrode 87, the vicinity of the interface between the wall surface 91 and the gate insulating film 86 in the p-type GaN layer 84. Electrons are induced in the (channel region) to form an inversion layer (channel). Through this inversion layer, conduction between the source and the drain is established. Thus, transistor operation is realized.
JP 2003-163354 A

In the conventional nitride semiconductor device, a channel region for conducting between the source and the drain is formed in the p-type GaN layer 84.
However, the electron mobility of a nitride semiconductor mainly containing p-type impurities such as the p-type GaN layer 84 is lower than the electron mobility of an n-type nitride semiconductor mainly containing n-type impurities. Therefore, in the conventional nitride semiconductor element, the on-resistance is increased due to the low electron mobility of the channel region.

  Therefore, an object of the present invention is to provide a nitride semiconductor device with reduced on-resistance and a method for manufacturing the same.

  In order to achieve the above object, the invention as set forth in claim 1 is a first layer made of an n-type group III nitride semiconductor, and a group III nitride semiconductor comprising a p-type impurity provided in the first layer. A nitride semiconductor multilayer structure portion including two layers and a third layer made of an n-type group III nitride semiconductor provided in the second layer, and having a wall surface straddling the first, second, and third layers; A fourth layer made of an n-type group III nitride semiconductor formed across the first, second, and third layers on the wall surface, and facing the second layer with the fourth layer interposed therebetween A fifth layer formed of a group III nitride semiconductor containing a p-type impurity, a gate electrode formed so as to be electrically connected to the fifth layer, and electrically connected to the third layer. A source electrode formed to be connected to the first layer, and a source electrode formed to be electrically connected to the first layer. And a in-electrode, a nitride semiconductor device.

According to this configuration, the first layer made of an n-type group III nitride semiconductor, the second layer made of a group III nitride semiconductor containing a p-type impurity, and the third layer made of an n-type group III nitride semiconductor are provided. By laminating, a nitride semiconductor multilayer structure portion having an npn structure is formed.
On the wall surface formed across the first, second and third layers, a fourth layer made of an n-type group III nitride semiconductor is formed so as to straddle them. The n-type fourth layer and the second layer containing the p-type impurity form a pn junction.

On the other hand, on the side of the fourth layer opposite to the junction side with the second layer, a fifth layer made of a group III nitride semiconductor containing a p-type impurity is formed so as to face the second layer. The fourth layer forms a pn junction also in relation to the fifth layer.
A gate electrode is formed so as to be electrically connected to the fifth layer. Further, a source electrode is formed so as to be electrically connected to the third layer, and a drain electrode is formed so as to be electrically connected to the first layer.

Note that the source electrode and the drain electrode are only required to be electrically connected to the third layer and the first layer, respectively, and one or more semiconductor layers having different compositions and impurities are interposed between these electrodes and the semiconductor layer. It may be intervened.
Next, the operation of this nitride semiconductor device will be described.
A bias with a positive drain side is applied between the source electrode and the drain electrode. As a result, a reverse voltage is applied to the pn junction at the interface between the first layer and the second layer. As a result, between the third layer and the first layer, that is, between the source electrode and the drain electrode (between the source and the drain) is in a cut-off state (reverse bias state). On the other hand, the fourth layer is pinched off by a depletion layer extending from the pn junction at the interface with the second layer and the pn junction at the interface with the fifth layer.

In this state, when a bias equal to or higher than the gate threshold voltage, which is positive with the source electrode as a reference potential, is applied to the gate electrode, the width of the depletion layer extending to the fourth layer is reduced and a channel is formed.
The first layer and the third layer are electrically connected via the channel (fourth layer). Thus, conduction between the source and the drain is established.

As described above, this nitride semiconductor device is gated with respect to the n-type fourth layer which is normally pinched off by the depletion layer extending from the pn junction with the second layer and the pn junction with the fifth layer. This is a so-called junction field effect transistor in which a source and a drain are electrically connected by applying a voltage.
That is, a channel is formed in the fourth layer made of an n-type group III nitride semiconductor mainly containing n-type impurities, which has a higher electron mobility than a nitride semiconductor mainly containing p-type impurities. Can be reduced.

Furthermore, since the fifth layer containing a p-type impurity is used as a junction gate, it is possible to suppress a decrease in the gate threshold voltage during the operation of the device and achieve a normally-off operation of the device.
For example, a trench is formed in the nitride semiconductor multilayer structure portion from the third layer through the second layer to reach the first layer, and a pair of inner side surfaces of the trench define the wall surface. When formed, the fourth layer may be formed in such a shape that portions along the pair of inner side surfaces oppose each other through the trench. In this case, the fifth layer may be formed in the trench so as to be embedded inside the fourth layer.

In addition, the thickness of the portion sandwiched between the second layer and the fifth layer in the fourth layer is appropriately determined according to the size of the depletion layer extending from the pn junction with the second layer and the pn junction with the fifth layer. The optimal thickness is set. For example, it is set according to the p-type impurity concentration of the second layer or the fifth layer.
According to a second aspect of the present invention, there is provided a first layer forming step of forming a first layer made of an n-type group III nitride semiconductor, and a group III nitride containing a p-type impurity on the first layer. A second layer forming step for forming a second layer made of a semiconductor, a third layer forming step for forming a third layer made of an n-type group III nitride semiconductor on the second layer, A wall surface forming step for forming a wall surface straddling the second and third layers, and a fourth layer made of an n-type group III nitride semiconductor formed on the wall surface so as to straddle the first, second and third layers. A fourth layer forming step, and a fifth layer forming step of forming a fifth layer made of a group III nitride semiconductor containing a p-type impurity so as to face the second layer across the fourth layer; Forming a gate electrode so as to be electrically connected to the fifth layer; and electrically connecting to the third layer. A source electrode forming step of forming a source electrode, and a drain electrode formation step of forming a drain electrode so as to be electrically connected to the first layer, a method for manufacturing a nitride semiconductor device.

By this method, the nitride semiconductor device according to claim 1 can be manufactured.
According to a third aspect of the present invention, the fifth layer forming step includes a growth step of growing a group III nitride semiconductor containing a p-type impurity on the fourth layer, and a group III containing the p-type impurity. Forming the fifth layer by etching through a mask covering a portion of the nitride semiconductor, wherein the gate electrode forming step includes forming the gate electrode on a portion of the fifth layer covered with the mask. The method for manufacturing a nitride semiconductor device according to claim 2, comprising a step of forming a layer.

  In general, when a group III nitride semiconductor containing a p-type impurity is etched, the concentration of the n-type impurity in the etched portion increases due to, for example, nitrogen desorption from the semiconductor surface. For example, in the nitride semiconductor device, when a part of the fifth layer is etched, the n-type impurity concentration in the etched part of the fifth layer is higher than the impurity concentration in the part other than the part.

Even if the gate electrode is brought into contact with a portion having a high n-type impurity concentration, it is difficult to obtain good ohmic characteristics at the junction between the fifth layer and the gate electrode.
On the other hand, in the manufacturing method according to claim 3, since the gate electrode is formed in a portion other than the portion to be etched, that is, in the portion covered with the mask in the fifth layer, at the junction between the fifth layer and the gate electrode. Good ohmic characteristics can be obtained. Therefore, good transistor operation can be performed.

Further, the fifth layer forming step, for example, using SiO _2, step of forming the mask by a spin-on-glass (SOG) method, a SiO _2, forming the mask by plasma CVD (Chemical vapor deposition) And a step of forming the mask by ECR (Electron Cyclotron Resonance) sputtering using SiO ₂ . According to the method described above, the mask can be formed with little damage to the fifth layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to an embodiment of the present invention.
This nitride semiconductor device includes a substrate 1 and a nitride semiconductor multilayer structure portion 2 formed on one surface of the substrate 1.

As the substrate 1, for example, an insulating substrate such as a sapphire substrate, or a conductive substrate such as a GaN substrate, a ZnO substrate, a Si substrate, a GaAs substrate, and a SiC substrate can be applied. In this embodiment, a conductive substrate is applied.
The nitride semiconductor multilayer structure portion 2 is laminated on an n-type layer 3 and an n-type layer 3 (first layer) made of n-type GaN (gallium nitride) mainly containing n-type impurities. A p-type layer 4 (second layer) made of GaN mainly containing p-type impurities, and an n-type layer 5 (third layer) made of n-type GaN mainly containing n-type impurities stacked on the p-type layer 4. It has.

From the outermost surface 16 parallel to the stacking direction of the nitride semiconductor stacked structure unit 2 in the n-type layer 5 (hereinafter, this direction may be simply referred to as “stacking direction”) to the nitride semiconductor stacked structure unit 2, A trench 6 having a depth penetrating the n-type layer 5 and the p-type layer 4 and reaching the middle of the n-type layer 3 in the stacking direction is formed.
The trench 6 is formed in a substantially inverted trapezoidal cross section, and is formed in a stripe shape extending in a direction orthogonal to the stacking direction. Further, although not shown in FIG. 1, a plurality of trenches 6 are formed at a certain interval in the width direction orthogonal to the stripe direction (hereinafter, this direction may be simply referred to as “width direction”). ing.

A pair of inclined inner surfaces of the trench 6 form wall surfaces 7 straddling the n-type layer 3, the p-type layer 4 and the n-type layer 5.
For example, when the substrate 1 having a c-plane (0001) as the main surface is used, the n-type layer 3, the p-type layer 4 and the n-type layer 5 grown on the substrate 1 by epitaxial growth are also c-plane (0001). Are stacked as the main surface (lamination interface). Further, the plane orientation of the wall surface 7 of the nitride semiconductor multilayer structure portion 2 is, for example, a plane (a plane other than the c plane) inclined in a range of 15 ° to 90 ° with respect to the c plane (0001). More specifically, for example, non-polar surfaces (non-polar surfaces) such as m-plane (10-10) or a-plane (11-20), (10-13), (10-11), (11-22) ) And other semipolar surfaces (semipolar surfaces).

Further, an n-type channel layer 8 (fourth layer) made of n-type GaN mainly containing n-type impurities is formed so as to cover the entire wall surface 7. In the n-type channel layer 8, a channel that electrically conducts between the n-type layer 3 and the n-type layer 5 is formed by applying an appropriate bias to a gate electrode 10 (described later). The n-type channel layer 8 is formed in such a shape that portions along the pair of wall surfaces 7 face each other through the trench 6, and the thickness thereof is determined by the p-type impurity concentration of the p-type layer 4 and the p-type gate layer 9. It is set according to the p-type impurity concentration (described later). For example, the impurity concentration of the p-type layer 4 is 1 × 10 ¹⁹ to 4 × 10 ¹⁹ cm ⁻³ , and the impurity concentration of the p-type gate layer 9 (described later) is 1 × 10 ¹⁹ to 4 × 10 ¹⁹ cm ⁻³ . In some cases, the thickness t of the portion sandwiched between the p-type layer 4 and the p-type gate layer 9 (described later) in the n-type channel layer 8 is 20 to 50 nm. The n-type channel layer 8 is formed in contact with the p-type layer 4, thereby forming a pn junction with the p-type layer 4.

  In the trench 6, a p-type gate layer 9 made of GaN containing a p-type impurity is buried inside the n-type channel layer 8. The p-type gate layer 9 fills the trench 6, and further has an outermost surface 15 parallel to the stacked interface of the nitride semiconductor stacked structure portion 2 (hereinafter, this interface may be simply referred to as “stacked interface”). The n-type layer 5 is formed in a convex shape protruding above the outermost surface 16. In the p-type gate layer 9, a pair of side surfaces connected to both side lines of the outermost surface 15 form wall surfaces 14 that are inclined with respect to the stack interface of the nitride semiconductor multilayer structure portion 2. The p-type gate layer 9 is formed in contact with the n-type channel layer 8, thereby forming a pn junction with the n-type channel layer 8. The outermost surface 15 of the p-type gate layer 9 may be formed flush with the outermost surface 16 of the n-type layer 5, or a concave surface that is recessed inwardly of the trench 6 from the outermost surface 16. Also good.

  A gate electrode 10 is formed on the outermost surface 15 of the p-type gate layer 9. The gate electrode 10 is made of, for example, Ni and Au laminated on the Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy and Pd / Pt / Au alloy, Pt, Al, polysilicon It can be formed using a conductive material such as, and is electrically connected to the p-type gate layer 9.

  A source electrode 11 is formed on the outermost surface 16 of the n-type layer 5. The source electrode 11 can be formed using, for example, Ti and a metal such as a Ti / Al alloy made of Al laminated on the Ti, and is electrically connected to the n-type layer 5. By forming the source electrode 11 with a metal containing Al, good ohmic characteristics can be obtained at the junction between the source electrode 11 and the n-type layer 5. In addition, the source electrode 11 may be formed using Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

  A drain electrode 12 is formed in contact with the other surface of the substrate 1. The drain electrode 12 can be formed using, for example, a metal such as Al, and is electrically connected to the n-type layer 3 via the substrate 1. In addition, the drain electrode 12 may be formed using Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

Next, the operation of the nitride semiconductor device will be described.
A bias is applied between the source electrode 11 and the drain electrode 12 so that the drain electrode 12 side is positive. As a result, a reverse voltage is applied to the pn junction at the interface between the n-type layer 3 and the p-type layer 4. As a result, between the n-type layer 5 and the n-type layer 3, that is, between the source electrode 11 and the drain electrode 12 (between the source and the drain) is in a cut-off state (reverse bias state). On the other hand, the n-type channel layer 8 is pinched off by a depletion layer extending from the pn junction at the interface with the p-type layer 4 and the pn junction at the interface with the p-type gate layer 9.

  In this state, when a bias equal to or higher than the gate threshold voltage that is positive with the source electrode 11 as a reference potential is applied to the gate electrode 10, the width of the depletion layer extending in the n-type channel layer 8 is reduced, and the n-type channel layer 8 A channel is formed. The n-type layer 3 and the n-type layer 5 are electrically connected via the channel (n-type channel layer 8). Thus, conduction between the source and the drain is established. That is, when a predetermined bias is applied to the gate electrode 10, the source and the drain are conducted, and when no bias is applied to the gate electrode 10, the source and the drain are cut off. Further, the channel width can be controlled by a bias applied to the gate electrode 10. In this way, transistor operation is realized.

2A to 2E are schematic cross-sectional views for explaining a method for manufacturing the nitride semiconductor device of FIG.
In order to manufacture this nitride semiconductor device, first, GaN grows from one surface of the substrate 1 while being doped with n-type impurities, for example, by MOCVD (Metal Organic Chemical Vapor Deposition). Be made. GaN grows in a direction perpendicular to one surface of the substrate 1, thereby forming the n-type layer 3 (first layer forming step). Note that, for example, Si may be used as the n-type impurity doped into the grown GaN.

Next, GaN is grown on the n-type layer 3 by, for example, MOCVD while doping p-type impurities, thereby forming the p-type layer 4 (second layer forming step). Note that, for example, Mg or C may be used as the p-type impurity doped into the grown GaN.
Further, GaN is grown on the p-type layer 4 while being doped with n-type impurities by, for example, MOCVD to form the n-type layer 5 (third layer forming step). Note that, for example, Si may be used as the n-type impurity doped into the grown GaN. 2A, the n-type layer 3, the p-type layer 4 and the n-type layer 5 are formed on one surface of the substrate 1 and have a laminated interface parallel to the main growth surface (one surface) of the substrate 1. The nitride semiconductor multilayer structure portion 2 is formed.

  Thereafter, an etching mask (not shown) is formed on the outermost surface 16 of the n-type layer 5 parallel to the stack interface. Then, the nitride semiconductor multilayer structure portion 2 is etched in a stripe shape through this mask. That is, a trench 6 having a depth extending from the outermost surface 16 of the n-type layer 5 through the n-type layer 5 and the p-type layer 4 and midway in the stacking direction of the n-type layer 3 is formed by etching. Thereby, as shown in FIG. 2B, a plurality of nitride semiconductor multilayer structures 2 are shaped into stripes, and a wall surface 7 straddling the n-type layer 3, the p-type layer 4, and the n-type layer 5 is simultaneously formed. (Wall surface forming step).

The trench 6 can be formed, for example, by dry etching (anisotropic etching) using a chlorine-based gas. In addition, after dry etching, you may perform the wet etching process for improving the wall surface 7 of the trench 6 damaged by dry etching as needed.
For wet etching, it is preferable to use KOH (potassium hydroxide), NaOH (sodium hydroxide) or the like. As a result, Si-based oxide, Ga oxide, and the like are removed, and the wall surface 7 can be leveled. Also, the damaged wall surface 7 can be improved by wet etching with HF (hydrofluoric acid), HCl (hydrochloric acid), etc., and the damaged wall surface 7 can be obtained. By reducing the damage to the wall surface 7, the interface between the wall surface 7 and the n-type channel layer 8 can be a good interface. Note that a low-damage dry etching process can be applied instead of the wet etching process.

  Next, GaN is grown from the inner surface of the trench 6 and the outermost surface 16 of the n-type layer 5 by, for example, MOCVD while doping n-type impurities. Note that, for example, Si may be used as the n-type impurity doped into the grown GaN. As a result, as shown in FIG. 2C, an n-type channel layer 8 that covers the inner surface (wall surface 7) of the trench 6 and the outermost surface 16 of the n-type layer 5 is formed (fourth layer forming step).

  Subsequent to the formation of the n-type channel layer 8, GaN is grown while being doped with p-type impurities. This growth is continued until the GaN grown from the n-type channel layer 8 in the trench 6 has a height protruding from the outermost surface 16 of the n-type layer 5. In this way, as shown in FIG. 2C, the p-type gate layer 9 covering the entire surface of the n-type channel layer 8 is formed (fifth layer forming step).

Since GaN grows from the surface of the n-type channel layer 8 at a uniform growth rate, the grown p-type gate layer 9 is striped above the trench 6 in the stacking direction as shown in FIG. 2C. The cross section has a substantially concave shape having a concave portion 17 that is recessed in a shape. Further, as the p-type impurity doped into the growing GaN, for example, Mg or C may be used.
Next, a mask 13 is formed on the outermost surface 15 of the p-type gate layer 9 parallel to the stack interface in the recess 17, and the outermost surface 15 of the p-type gate layer 9 is covered with the mask 13.

  Then, the p-type gate layer 9 and the n-type channel layer 8 are dry-etched in stripes through this mask 13. In this manner, the p-type gate layer 9 is shaped into a stripe shape, and a wall surface 14 that is inclined with respect to the stacked interface of the nitride semiconductor stacked structure portion 2 is simultaneously formed. Further, the portion outside the trench 6 in the n-type channel layer 8 is removed, and the outermost surface 16 of the n-type layer 5 is exposed as shown in FIG. 2D.

Thereafter, the mask 13 is removed, and the outermost surface 15 of the p-type gate layer 9 covered with the mask 13 is exposed.
Subsequently, a metal used as a material of the source electrode 11 (in this embodiment, Ti and Ti) through a photoresist (not shown) having an opening in a region where the source electrode 11 is to be formed by a known photolithography technique. Al) is sputtered by sputtering. Thereafter, the photoresist is removed, and unnecessary portions of metal (portions other than the source electrode 11) are lifted off together with the photoresist. Through these steps, the source electrode 11 is formed on the outermost surface 16 of the n-type layer 5 (source electrode forming step).

After the source electrode 11 is formed, a thermal alloy (annealing process) is performed.
Next, a metal (Ni and Au in this embodiment) used as a material of the gate electrode 10 is passed through a photoresist (not shown) having an opening in a region where the gate electrode 10 is to be formed by a known photolithography technique. ) Is sputtered by sputtering. Thereafter, by removing the photoresist, unnecessary portions of metal (portions other than the gate electrode 10) are lifted off together with the photoresist. Through these steps, the gate electrode 10 is formed on the outermost surface 15 of the p-type gate layer 9 (gate electrode forming step). That is, the gate electrode 10 is formed in contact with the outermost surface 15 of the p-type gate layer 9 covered with the mask 13 when the p-type gate layer 9 is shaped.

Thereafter, the drain electrode 12 is formed on the other surface of the substrate 1 by the same method as that for the source electrode 11 and the gate electrode 10 (drain electrode forming step).
Thus, as shown in FIG. 2E, the nitride semiconductor device of FIG. 1 can be obtained.
Each of the plurality of nitride semiconductor multilayer structures 2 forms a unit cell. The gate electrode 10 and the source electrode 11 of the nitride semiconductor multilayer structure portion 2 are commonly connected at positions not shown. The drain electrode 12 is formed in contact with the substrate 1 and is a common electrode for all cells.

As described above, this nitride semiconductor element is formed in the n-type channel layer 8 that is normally pinched off by the depletion layer extending from the pn junction with the p-type layer 4 and the pn junction with the p-type gate layer 9. On the other hand, it is a so-called n-type channel junction field effect transistor in which a source-drain is made conductive by applying a gate voltage.
Since the channel is formed in the n-type channel layer 8 made of n-type GaN having higher electron mobility than GaN mainly containing p-type impurities, the on-resistance of the element can be reduced.

Furthermore, since the p-type gate layer 9 made of GaN mainly containing p-type impurities is used as a junction gate, it is possible to suppress a decrease in the gate threshold voltage during the operation of the device and achieve a normally-off operation of the device.
In addition, since the gate electrode 10 is formed in contact with the outermost surface 15 covered with the mask 13 when the p-type gate layer 9 is shaped, the gate electrode 10 is satisfactorily ohmic with respect to the p-type gate layer 9. Can be joined. In general, when a group III nitride semiconductor containing a p-type impurity is etched, the concentration of the n-type impurity in the etched portion increases. For example, the n-type impurity concentration of the portion exposed by dry etching such as the wall surface 14 of the p-type gate layer 9 is higher than the impurity concentration of the portion other than the portion in the p-type gate layer 9. Even if the gate electrode 10 is formed in contact with a portion having a high n-type impurity concentration, it is difficult to obtain good ohmic characteristics at the junction between the p-type gate layer 9 and the gate electrode 10.

On the other hand, in this embodiment, the gate electrode 10 is formed in contact with the outermost surface 15 of the p-type gate layer 9. Therefore, good ohmic characteristics can be obtained at the junction between the p-type gate layer 9 and the gate electrode 10. As a result, good transistor operation can be performed.
As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form. For example, in the above-described embodiment, the n-type layer 3, the p-type layer 4, the n-type layer 5, the n-type channel layer 8 and the p-type gate layer 9 are formed using GaN. Other group III nitride semiconductors, such as aluminum nitride (AlN) and indium nitride (InN), are generally Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y) It can also be formed using a material that can be expressed as ≦ 1).

In the above-described embodiment, the wall surface 7 is a surface that is inclined with respect to the main surface of the substrate 1. However, the wall surface 7 does not have to be inclined and does not have to be a flat surface. That is, the wall surface 7 may be a plane perpendicular to the substrate 1 or a curved surface.
In the above-described embodiment, an example in which the trench 6 having a substantially inverted trapezoidal cross section is formed in the nitride semiconductor multilayer structure portion 2 is described. However, the shape of the trench 6 may be V-shaped, U-shaped, rectangular, or the like. The shape may also be

  In addition, various design changes can be made within the scope of matters described in the claims.

It is typical sectional drawing for demonstrating the structure of the nitride semiconductor element which concerns on one Embodiment of this invention. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the nitride semiconductor device of FIG. 1. It is typical sectional drawing which shows the next process of FIG. 2A. It is typical sectional drawing which shows the next process of FIG. 2B. It is typical sectional drawing which shows the next process of FIG. 2C. It is typical sectional drawing which shows the next process of FIG. 2D. It is typical sectional drawing for demonstrating the structure of the conventional nitride semiconductor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Nitride semiconductor laminated structure part 3 n-type layer 4 p-type layer 5 n-type layer 6 trench 7 wall surface 8 n-type channel layer 9 p-type gate layer 10 gate electrode 11 source electrode 12 drain electrode 13 mask 14 wall surface 15 most Surface 16 outermost surface

Claims (3)

A first layer made of an n-type group III nitride semiconductor, a second layer made of a group III nitride semiconductor containing a p-type impurity provided in the first layer, and an n-type formed in the second layer A nitride semiconductor multilayer structure comprising a third layer made of a group III nitride semiconductor and having a wall surface straddling the first, second and third layers;
A fourth layer made of an n-type group III nitride semiconductor formed on the wall surface and straddling the first, second and third layers;
A fifth layer made of a group III nitride semiconductor containing a p-type impurity formed to face the second layer with the fourth layer interposed therebetween;
A gate electrode formed to be electrically connected to the fifth layer;
A source electrode formed to be electrically connected to the third layer;
And a drain electrode formed to be electrically connected to the first layer. a first layer forming step of forming a first layer made of an n-type group III nitride semiconductor;
A second layer forming step of forming a second layer made of a group III nitride semiconductor containing a p-type impurity on the first layer;
A third layer forming step of forming a third layer made of an n-type group III nitride semiconductor on the second layer;
A wall surface forming step of forming a wall surface straddling the first, second and third layers;
A fourth layer forming step of forming a fourth layer made of an n-type group III nitride semiconductor on the wall surface so as to straddle the first, second and third layers;
A fifth layer forming step of forming a fifth layer made of a group III nitride semiconductor containing a p-type impurity so as to face the second layer across the fourth layer;
Forming a gate electrode so as to be electrically connected to the fifth layer;
A source electrode forming step of forming a source electrode so as to be electrically connected to the third layer; and a drain electrode forming step of forming a drain electrode so as to be electrically connected to the first layer. A method for manufacturing a semiconductor device. The fifth layer forming step includes a growth step of growing a group III nitride semiconductor containing a p-type impurity on the fourth layer, and a mask covering a part of the group III nitride semiconductor containing the p-type impurity. Forming the fifth layer by etching.
The method for manufacturing a nitride semiconductor device according to claim 2, wherein the gate electrode forming step includes a step of forming the gate electrode in a portion of the fifth layer covered with the mask.

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