JP2011155221A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, and so on, capable of stably acquiring low on-resistance, having once obtained high mobility of channel and superior breakdown voltage in the longitudinal direction. <P>SOLUTION: In the semiconductor device, a GaN laminate 15 containing an n-type drift layer 4/a p-type layer 6/an n-type surface layer 8 is formed. The GaN laminate has an opening portion 5 and includes a regrowth layer 27, a gate electrode 11, a source electrode 31 and a drain electrode 39. The regrowth layer 27 contains an electron transit layer 22 and an electron supply layer 26, and a channel is a two-dimensional electron gas, and an epitaxial layer having a lattice constant which is smaller than GaN is inserted in at least one of between the p-type layer 6 and the n-type surface layer 8, and between an end surface of the GaN laminate surrounding the opening portion and the regrowth layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a vertical semiconductor device that is used for high-power switching and has low on-resistance and excellent withstand voltage performance, and a method for manufacturing the same.

  A switching element for large current is required to have a high reverse breakdown voltage and a low on-resistance. Field effect transistors (FETs) using Group III nitride semiconductors are superior in terms of high voltage resistance, high temperature operation, etc. due to their large band gaps, especially vertical type using GaN-based semiconductors. Transistors have attracted attention as high-power control transistors. For example, by providing an opening in a GaN-based semiconductor and providing a regrowth layer including a two-dimensional electron gas (2DEG) channel on the side of the opening, the mobility is increased and the on-resistance is reduced. A vertical GaN FET has been proposed (Patent Document 1).

JP 2006-286542 A

  In the above-mentioned vertical FET, a p-type GaN layer having a guard ring action is inserted around the opening where the regrowth layer is provided. For this reason, since it becomes an npn structure, obtaining the high mobility of the channel which forms two-dimensional electron gas, the pressure | voltage resistant performance of a vertical direction is securable. However, the structure is not necessarily sufficient to ensure low on-resistance.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can ensure a low on-resistance stably while obtaining an excellent longitudinal breakdown voltage.

  The semiconductor device of the present invention is formed in a GaN-based stack including an n-type drift layer, a p-type layer located on the n-type drift layer, and an n-type surface layer located on the p-type layer. . In this GaN-based semiconductor device, an opening reaching the n-type drift layer is provided in the GaN-based stacked body, and a regrowth layer including a channel is positioned so as to cover the opening, and is positioned on the regrowth layer. A gate electrode; a source electrode positioned on the GaN-based stacked body and in contact with the regrowth layer; and a drain electrode positioned so as to sandwich the source electrode and the n-type drift layer. The regrowth layer includes an electron transit layer and an electron supply layer, and a channel is a two-dimensional electron gas formed at the interface of the electron transit layer with the electron supply layer, and is formed between the p-type layer and the n-type surface layer, and the opening An epitaxial layer having a lattice constant smaller than that of GaN is inserted between at least one of the end face of the GaN-based laminate surrounding the portion and the regrowth layer.

According to the above configuration, an epitaxial layer having a lattice constant smaller than that of GaN is present between the p-type layer and the n-type surface layer and / or between the end face of the GaN-based semiconductor layer, particularly the p-type layer, and the regrowth layer. Has been inserted. This effectively blocks the diffusion of p-type impurities (for example, Mg) from the p-type layer to the n-type surface layer and / or the regrowth layer by an epitaxial layer having a lattice constant smaller than that of GaN. Can do. The p-type layer has a back gate effect, shifts the threshold voltage in the positive direction, contributes to the normally-off, and improves the vertical breakdown voltage performance. However, there is a problem that the p-type impurity is diffused around the p-type impurity, particularly in the upper layer, and the on-resistance is increased. The above configuration contributes to the realization of normally-off and improves the vertical breakdown voltage performance, while preventing the n-type surface layer and / or the regrowth layer from increasing in resistance, and turning on the device. Resistance can be kept low.
Here, when the lattice constant of the first or second epitaxial layer having a lattice constant smaller than that of GaN is ai (i = 1, 2) and the lattice constant of GaN is a, ai <a, and The lattice matching condition | ai−a | /a≦0.002 is satisfied, and for example, AlGaN, AlN, and the like are applicable.

The above GaN-based laminate is epitaxially grown on a predetermined crystal plane of GaN. The underlying GaN may be a GaN substrate or a GaN film on a support substrate. Furthermore, it is formed on a GaN substrate or the like during the growth of the GaN-based laminate, and in the subsequent process, except for a predetermined thickness portion such as the GaN substrate, only a thin GaN layer base remains in the product state. There may be. The thin underlying GaN layer may be conductive or non-conductive, and the drain electrode can be provided on the front or back surface of the thin GaN layer, depending on the manufacturing process and the structure of the product.
When the GaN substrate or the supporting base remains in the product, the supporting base or the substrate may be conductive or non-conductive. In the case of conductivity, the drain electrode can be directly provided on the back surface (lower) or front surface (upper) of the supporting base or substrate. In the case of non-conductivity, a drain electrode can be provided on the non-conductive substrate and on the conductive layer located on the lower layer side in the semiconductor layer.

  A first epitaxial layer having a lattice constant smaller than that of GaN is inserted between the p-type layer and the n-type surface layer, and between the GaN-based stacked body surrounding the opening and the regrowth layer, than the GaN layer. A second epitaxial layer having a small lattice constant can be interposed. Thereby, it is possible to reliably prevent the diffusion of the p-type impurity into the regrowth layer and the diffusion of the p-type impurity into the n-type surface layer.

  The regrowth layer can be formed so that there is no region where the second epitaxial layer is not the underlying layer. Accordingly, it is possible to reliably prevent p-type impurities from diffusing into the channel in which the 2DEG in the regrowth layer is formed, and to prevent an increase in on-resistance in the channel.

One chip formed in the range of the GaN-based semiconductor layer, wherein a plurality of openings are provided, and the first epitaxial layer is opened for each opening and positioned over the range of the GaN-based semiconductor layer. In addition, the second epitaxial layer can take a configuration in which the second epitaxial layer is recessed over the opening and penetrates the source electrode on the n-type surface layer and is located over the range of the GaN-based semiconductor layer.
Since current flows through the channel in the regrowth layer located on the wall surface of the opening, the amount of current that can flow per area is determined by the perimeter of the opening per area. By adopting the one-chip configuration described above, it is possible to prevent the diffusion of impurities while increasing the perimeter of the opening per area and increasing the current density per area. As a result, an increase in on-resistance caused by impurity diffusion can be prevented.

  An interlayer insulating film is located so as to cover the gate electrode and the source electrode, and the source electrode can be connected to a conductive layer on the interlayer insulating film through a via hole provided in the interlayer insulating film. As a result, the wiring of the source electrode and the wiring of the gate electrode can be three-dimensionally crossed without interfering with each other, so that the space for these wirings can be reduced, and the openings are arranged closely so that the current per unit area can be reduced. Can be bigger. In addition, since the wiring is not routed, the electrical resistance of the source electrode and the gate electrode can be reduced. Thereby, a low on-resistance can be obtained.

A configuration in which the p-type layer and the source electrode are connected by a conductive portion can be employed. Thereby, the potential of the p-type layer can be set to the potential of the source electrode, the function of the electron blocking layer can be further improved, and a high breakdown voltage can be obtained.

  The opening can be positioned in a honeycomb shape or a hook shape. Thereby, the perimeter of the opening per unit area can be increased, and a large current can be easily passed.

In the method for manufacturing a semiconductor device of the present invention, a GaN-based semiconductor device using a GaN-based stacked body is manufactured. In this manufacturing method, an n-type drift layer and a p-type layer located on the n-type drift layer are formed, and a first epitaxial layer having a lattice constant smaller than that of GaN is formed on the p-type layer. And a step of forming an n-type surface layer on the first epitaxial layer.
By the above method, the diffusion of p-type impurities (Mg, etc.) from the p-type layer to the n-type surface layer can be reliably blocked only by inserting the first epitaxial layer. As a result, after obtaining the back gate effect by the p-type layer, it is possible to prevent an increase in on-resistance due to the diffusion of the p-type impurity.

In another GaN-based semiconductor device manufacturing method of the present invention, an n-type drift layer, a p-type layer located on the n-type drift layer, an n-type surface layer on the p-type layer, and an n-type A step of opening an opening reaching the n-type drift layer by etching in the drift layer, the p-type layer, and the n-type surface layer, and a second epitaxial layer having a lattice constant smaller than that of GaN so as to cover the opening And a step of forming a regrowth layer for generating a two-dimensional electron gas on the second epitaxial layer along the opening.
By the above method, diffusion of p-type impurities (such as Mg) from the p-type layer to the regrown layer, particularly the channel, can be reliably blocked only by interposing the second epitaxial layer. As a result, after obtaining the back gate effect by the p-type layer, it is possible to prevent an increase in on-resistance due to the diffusion of the p-type impurity.

  ADVANTAGE OF THE INVENTION According to this invention, after obtaining the high mobility of a channel and the outstanding vertical direction pressure | voltage resistance, the semiconductor device which can ensure low on-resistance stably and its manufacturing method can be obtained.

FIG. 3 is a cross-sectional view taken along the line II of FIG. 2, showing the vertical GaN-based FET according to the first embodiment of the present invention. It is a top view of the corner part of the chip | tip in which the semiconductor device of FIG. 1 is formed. It is a figure which shows the wiring system | strain of a source electrode. It is a cross-sectional enlarged view in the end surface of the n-type GaN surface layer which comprises the wall surface of an opening part. 1A and 1B show a method of manufacturing the vertical GaN-based FET of FIG. 1, in which FIG. 1A shows a state in which an epitaxial laminated body including a first diffusion prevention layer is formed on a GaN substrate, and FIG. 1B shows a resist pattern for providing an opening. It is a figure which shows the formed state. (A) is the state which provided the opening part by the etching, (b) is a figure which shows the state which removed the resist pattern and further etched the opening part. (A) shows a state in which a second diffusion prevention layer and a regrowth layer are formed on the surface of the opening, and then a conductive part. (B) shows a state in which a gate structure including a source electrode and a gate electrode is formed. FIG. (A) is the state which deposited the interlayer insulation film, (b) is a figure which shows the state which opened the via hole in the interlayer insulation film on a source electrode, and formed the source conductive layer electrically connected to a source electrode. It is sectional drawing which shows the vertical GaN-type FET in Embodiment 2 of this invention. It is a figure which shows the vertical GaN-type FET in Embodiment 3 of this invention. It is sectional drawing which shows the vertical GaN-type semiconductor device before this invention. FIG. 12 is a diagram showing a concentration distribution of Mg in the depth direction measured by SIMS analysis for the semiconductor device of FIG. 11.

It is important for the semiconductor device of the present invention to have a low on-resistance in order to pass a large current. Referring to FIG. 11, an opening 105 reaching the n-type drift layer 104 from the surface of the GaN-based semiconductor layer is opened, and a regrowth layer 127 is formed so as to cover the wall surface and bottom surface of the opening 105. The regrowth layer 127 includes an electron transit layer 122 and an electron supply layer 126, and the channel is a two-dimensional electron gas (2DEG) formed at the interface between the electron transit layer 122 and the electron supply layer 126. The current to be controlled flows roughly through the path of the source electrode 131 → the channel → the n-type drift layer 104 → the drain electrode 139.
In this vertical semiconductor device, a p-type layer 106 is inserted between the n-type drift layer 104 and the n-type surface layer 108 to function as an electron block layer in order to increase the reverse breakdown voltage. The overall structure is a GaN substrate or GaN layer 101 on the support / n-type GaN buffer layer 102 / n-type drift layer 104 / p-type layer 106 / n-type surface layer 108.
In such a vertical semiconductor device, when the stacked structure of the n-type drift layer 104 / p-type layer 106 / n-type surface layer 108 is employed in the surface layer portion close to the source electrode 131 or the channel, the following problems occur. It has been found.

<Problem of the semiconductor device shown in FIG. 11>
12 shows the depth of the n-type surface layer 108 / p-type layer 106 / n-type drift layer 104 from the surface of the regrowth layer 127 (electron supply layer 126 / electron transit layer 122) with respect to the semiconductor device of FIG. It is a figure which shows the result of having performed SIMS (Secondary Ion Mass Spectroscopy: secondary ion mass spectrometry) in the direction. The object of SIMS measurement is Mg, which is a p-type impurity in GaN. In the semiconductor device shown in FIG. 10, the n-type drift layer 104 / p-type layer 106 / n-type surface layer 108 are sequentially formed from the bottom. When forming the p-type layer 106, the p-type impurity Mg is doped. As a result, the p-type layer 106 can obtain a certain level of p-type impurity concentration. However, according to SIMS, not only the p-type layer 106 but also the n-type surface layer 108, the Mg concentration is inclined, but shows a considerably high concentration distribution. Mg in the n-type surface layer 108 has the same concentration as that of the p-type layer 106 at the interface with the p-type layer 106, and decreases with a linear gradient as the distance from the interface increases. In addition, in the n-type drift layer 104 that is in contact with the p-type layer 106 on the lower layer side, no increase in concentration due to Mg inflow is recognized. In the formation of the n-type surface layer 108, the base is heated, and the n-type surface layer 108 in the middle of the film formation is in an active state. It is considered that Mg diffused from the p-type layer 106 to the n-type surface layer 108 in an active state during the formation of the n-type surface layer 108.
The p-type impurity diffused in the n-type surface layer 108 cancels the n-type impurity and lowers the n-type carrier concentration. The source electrode 131 is provided on the n-type surface layer 108, and if there is no high-concentration n-type carrier of a predetermined level or higher, the on-resistance increases and the power loss increases.
A feature of the present invention is to eliminate the above-mentioned problem, and after arranging a p-type layer having an electron blocking action to obtain a withstand voltage performance, the p-type layer is prevented from increasing an on-resistance. On the other hand, an epitaxial layer for preventing diffusion is coated. The epitaxial layer is arranged to conform to the unique structure of the semiconductor device of the present invention. In the following description, the first or second epitaxial layers 17 and 19 will be referred to as first or second diffusion prevention layers 17 and 19.

(Embodiment 1)
FIG. 1 is a cross-sectional view of a GaN-based vertical FET 10 according to Embodiment 1 of the present invention. FIG. 2 is a plan view of a chip on which the semiconductor device is formed, and shows where the cross-sectional view of FIG. 1 is located in the whole.
The vertical FET 10 includes a GaN substrate 1 (or a substrate 1 having a GaN layer on a conductive support base), a GaN-based stacked body 15, an opening 5, a regrowth layer 27, a gate electrode 11 on the regrowth layer 27, A source electrode 31 and a drain electrode 39 are included. (N-type drift layer 4 / p-type layer 6 / n-type surface layer 8), first diffusion prevention layer 17 and second diffusion prevention layer 19 for preventing diffusion of p-type impurities such as Mg, The GaN-based stacked body 15 including is formed over the entire area of the chip 10. The first diffusion prevention layer 17 and the second diffusion prevention layer 19 may be formed of a material that does not contain Ga, such as AlN. It will be described as being included in the GaN-based laminate 15. Between the p-type layer 6 and the n-type surface layer 8, the first diffusion preventing layer 17 described above is inserted.
An opening 5 is formed in the surface layer portion of the GaN-based semiconductor layer 15 so as to reach the n-type drift layer 4 from the surface. A second diffusion preventing layer 19 is formed along the wall surface and bottom surface of the opening 5. When the lattice constants of the first diffusion prevention layer 17 and the second diffusion prevention layer are ai (i = 1, 2) and the lattice constant of GaN is a, the conditions (1) and (2) are satisfied for the lattice constant. There is a need.
Condition (1): ai <a
Condition (2) | ai-a | /a≦0.002,
Condition (1) is a condition for blocking diffusion of p-type impurities, and condition (2) is a lattice matching condition for epitaxial growth. For the first diffusion prevention layer 17 and the second diffusion prevention layer 19, AlN, AlGaN, or the like, which is a material satisfying the above conditions (1) and (2), can be used.
A regrowth layer 27 is epitaxially grown on the second diffusion barrier layer 19. The source electrode 31 may be formed at a predetermined position on the n-type GaN surface layer 8 or may be formed in contact with the regrowth layer 27. The gate electrode 11 is formed in a recess in which the shape of the opening 5 is inherited.

In the GaN-based stacked body 15 shown in FIG. 1, no buffer layer is inserted between the GaN substrate 1 and the n-type drift layer 4; however, a buffer layer may be inserted. Will describe an example in which a buffer layer is inserted. As described above, the GaN-based stacked body 15 is epitaxially grown on a predetermined crystal plane of GaN, but the underlying GaN may be a GaN substrate or a GaN film on a support substrate. Furthermore, it is formed on a GaN substrate or the like during the growth of the GaN-based laminate, and in the subsequent process, except for a predetermined thickness portion such as the GaN substrate, only a thin GaN layer base remains in the product state. There may be. The thin underlying GaN layer may be conductive or non-conductive, and the drain electrode can be provided on the front or back surface of the thin GaN layer, depending on the manufacturing process and the structure of the product.
When the GaN substrate or the supporting base remains in the product, the supporting base or the substrate may be conductive or non-conductive. In the case of conductivity, the drain electrode can be directly provided on the back surface (lower) or front surface (upper) of the supporting base or substrate. In the case of non-conductivity, the drain electrode 39 can be provided on the non-conductive substrate and on the conductive layer located on the lower layer side in the semiconductor layer. The GaN substrate 1 shown in FIG. 1 is understood as meaning a wide variety of substrates containing GaN as described above.
In the vertical FET 10, electrons pass from the source electrode 31 through the GaN electron transit layer 22 in the regrowth layer 27, through the n-type GaN drift layer 4 and the GaN substrate 1 to the drain electrode 39 in the vertical direction (thickness). Direction). Since current flows in the vertical direction (thickness direction), a p-type impurity such as Mg can flow a large current with a low on-resistance unless it diffuses into other layers.

The GaN-based semiconductor layer 15 is a stack of (n-type GaN drift layer 4 / p-type GaN layer 6 / first AlGaN diffusion prevention layer 17 / n-type GaN surface layer 8) on the GaN substrate 1 in order from the bottom. With structure. In this embodiment, the p-type GaN layer 6 is conductively connected to the source electrode 31 for each opening 5 by a conductive portion 6 s disposed so as to surround the opening 5. As can be seen from the above description, the opening 5 is formed by removing a part of the p-type GaN layer 6. The opening 5 is formed such that the bottom surface reaches the n-type GaN drift layer 4 but does not penetrate. By arranging the p-type GaN layer 6 around the opening 5, the pinch-off characteristic can be improved by the back gate effect. If a p-type AlGaN layer is used instead of the p-type GaN layer 6, the band gap can be further increased, and the pinch-off characteristics of the vertical FET 10 can be improved.
The p-type layer 6 contributes to normally-off by the back gate effect in both the GaN layer and the AlGaN layer.

This embodiment is characterized by the following points. That is, the first diffusion prevention layer 17 is disposed between the p-type layer 6 and the n-type surface layer 8, and the second diffusion prevention layer is formed on the wall surface and bottom surface of the opening 5 and the GaN-based semiconductor layer 15. Layer 19 is disposed. The second diffusion prevention layer 19 becomes an underlayer for the regrowth layer 27.
The first diffusion prevention layer 17 can prevent the p-type impurity from entering the regrowth layer 27 via the n-type surface layer 8 and the n-type surface layer 8. The second diffusion prevention layer 19 can block p-type impurities that enter the regrowth layer 27 directly from the end face of the p-type layer 6. If the second diffusion prevention layer 19 is disposed so as to cover the wall surface of the opening 5 and the entire area around it, the p-type impurity can be prevented from entering the regrowth layer 27. However, the penetration of the p-type impurity from the p-type layer 6 to the n-type surface layer 8 cannot be prevented only by the second diffusion prevention layer 19. As a result, the n-type carrier concentration in the n-type surface layer 8 is lowered, and the on-resistance is increased. Therefore, in the present embodiment, both the second diffusion prevention layer 19 and the first diffusion prevention layer 17 are arranged. As a result, diffusion of p-type impurities can be reliably prevented, and a low on-resistance can be stably obtained.
Further, the p-type GaN layer 6 is conductively connected to the source electrode 31 for each opening 5 by a conductive portion 6 s disposed so as to surround the opening 5. The source-grounded p-type GaN layer 6 can exhibit the guard ring effect more stably, and can further stabilize the breakdown voltage performance of the gate electrode end.

As shown in FIG. 2, the opening 5 and the gate electrode 11 are hexagonal, and the periphery of the gate wiring 12 is covered with the source electrode 31 so as to avoid the gate wiring 12, and fine packing (honeycomb structure) is used. The gate electrode can have a long peripheral length, that is, the on-resistance can be lowered. The current flows through the path of the source electrode 31 → the regrowth layer 27 → the n-type drift layer 4 → the drain electrode 39. The source wiring is provided on the interlayer insulating film 32 so that the source electrode 31 and its wiring and the gate structure composed of the gate electrode 11, the gate wiring 12 and the gate pad 13 do not interfere with each other (see FIG. 3). As shown in FIG. 3, a via hole 32 h is provided in the interlayer insulating film 32, and the source electrode 31 including the plug conductive portion is conductively connected to the source conductive layer 33 on the interlayer insulating film 32. With such a structure, the source structure including the source electrode 31 can have a low electric resistance and a high mobility suitable for a high-power element.
The above hexagonal honeycomb structure can be formed in a bowl shape, and even by arranging the bowl-shaped openings densely, the opening perimeter per area can be increased, and as a result, the current density can be improved. it can.

<Wall surface of opening 5>
Next, FIG. 4 shows an enlarged cross-sectional view of the end surface of the n-type GaN surface layer 8 constituting the wall surface of the opening 5. As shown in FIG. 4, the wall surface of the opening 5 includes a plurality of surfaces S ₁ that are substantially perpendicular to the substrate surface and inclined surfaces S ₃ that are formed so as to complement each other between the surfaces S _1. They are formed in a mixed manner in the direction of inclination of the wall surface of the portion 5 (inclination angle θ).
In the vertical FET 10, in the case of the GaN substrate 1 whose main surface is the {0001} plane, the hexagonal GaN layer and the AlGaN layer are epitaxially grown with the {0001} plane (hereinafter referred to as C plane) as the growth plane. Yes. Therefore, the vertical plane S1 in the n-type GaN surface layer 8 is a {1-100} plane (hereinafter referred to as m plane). Unlike the C plane, the m plane is a nonpolar plane. For this reason, the GaN electron transit layer 22 and the AlGaN electron supply layer 26 are regrown using the m-plane as a growth surface, so that no piezo electric charge is generated at the heterointerface of the AlGaN 26 / GaN 22. For this reason, the electric field of the direction which reduces the minimum energy of a channel does not arise. Therefore, the vertical FET 10 contributes to the realization of normally-off.

  As the inclination angle θ of the side surface of the opening 5 in FIG. 4 is closer to 90 degrees, the proportion of the surface S1 on the side surface increases. Therefore, in order to realize normally-off in the vertical FET 10, the inclination angle θ is preferably close to 90 degrees, for example, 60 degrees or more.

<P-type layer 6>
The p-type barrier layer 6 can shift the threshold voltage in the positive direction by the back gate effect, and can contribute to the realization of normally-off. As shown in FIG. 4, the side surface of the opening 28 in the p-type GaN layer 6 is the same as the n-type GaN surface layer 8, has an m-plane, and includes a nonpolar plane.
The p-type GaN layer 6 can also prevent the breakdown voltage performance from becoming unstable at the end of the gate structure such as the gate electrode 11. The breakdown voltage performance of the gate electrode 11 can be further improved by the conductive connection of the p-type GaN layer 6 with the source electrode 31.

<Regrown layer 27>
The regrowth layer 27 may not include anything between the GaN electron transit layer 22 and the electron supply layer 26, but an AlN intermediate layer may be disposed therebetween. Here, no impurities are added to the GaN electron transit layer 22. On the other hand, an n-type impurity is added to the AlGaN electron supply layer 26. The AlGaN electron supply layer 26 has a larger band gap than the GaN electron transit layer 22. As a result, the two-dimensional electron gas is formed at the interface between the GaN electron transit layer 22 and the AlGaN electron supply layer 26, whereby the on-resistance can be further reduced.
When the AlN intermediate layer is provided, the AlN intermediate layer suppresses scattering of electrons at the interface between the GaN electron transit layer 22 and the AlGaN electron supply layer 26. Thereby, the electron mobility in the regrowth layer 27 can be improved. As a result, the on-resistance of the vertical FET 10 can be reduced.
The electron transit layer 22 and the electron supply layer 26 are, as GaN-based semiconductors, provided that the band gap energy of the electron supply layer 26 is larger than that of the electron transit layer 22, for example, from at least one of GaN, AlN, or InN. A crystal or a mixed crystal may be used. In particular, by using GaN or InGaN for the GaN electron transit layer 22 and using AlGaN for the electron supply layer 26, high mobility can be ensured.

  The diffusion of p-type impurities into the AlGaN electron supply layer 26 and the interface between the electron supply layer 26 and the electron transit layer 22 has a very serious adverse effect on the channel. Such a risk can be avoided by disposing the second diffusion preventing layer 19 in the entire range of the regrowth layer 27 so as to be the underlayer. In other words, the regrowth layer 27 is preferably provided with the second diffusion preventing layer 19 as a base in any region.

<Manufacturing method>
Next, a method for manufacturing the semiconductor device 10 in the present embodiment will be described. First, as shown in FIG. 5A, the buffer layer 2 / n-type GaN drift layer 4 / p-type GaN layer 6 / first AlGaN diffusion prevention layer 17 / n are formed on the GaN substrate 1 having the above meaning. A GaN-based laminate 15 of the type GaN surface layer 8 is epitaxially grown. For example, MOCVD (metal organic chemical vapor deposition) is used to form these layers. Alternatively, the MBE (molecular beam epitaxial) method may be used instead of the MOCVD method. Thereby, a GaN-based semiconductor layer with good crystallinity can be formed. The film thickness and carrier concentration of each layer are as follows.
Buffer layer 2: thickness 0.5 μm, carrier concentration 1.0 × 10 ¹⁷ cm ⁻³ ,
n-type GaN drift layer 4: thickness 5.0 μm, carrier concentration 5.0 × 10 ¹⁵ cm ⁻³
p-type GaN layer 6: thickness 0.5 μm, carrier concentration 7.0 × 10 ¹⁷ cm ⁻³
First AlGaN diffusion prevention layer 17: thickness 5 nm
n-type GaN surface layer 8: thickness 0.3 μm, carrier concentration 2.0 × 10 ¹⁸ cm ⁻³

Next, as shown in FIG. 5B, a resist mask pattern M1 is formed on the n-type GaN surface layer 8 in a predetermined region using a normal exposure technique. The resist mask pattern M1 formed here has a hexagonal plane shape and a trapezoidal (mesa type) cross-sectional shape of the opening. Although not described here, when the opening is formed in a bowl shape, the planar shape of the opening may be a strip shape and the cross-sectional shape may be a mesa shape.
Thereafter, as shown in FIG. 6A, the n-type GaN surface layer 8 is formed by RIE (Reactive Ion Etching) using high-density plasma generated by using inductively coupled plasma. The p-type GaN barrier layer 6 and a part of the n-type GaN drift layer 4 are etched to form the opening 5. As a result, the end surfaces of the n-type GaN surface layer 8, the p-type GaN barrier layer 6, and the n-type GaN drift layer 4 are exposed to the opening 5 to form the wall surface of the opening. At this time, etching damage has occurred on the side surface of the opening 5 over a depth of several nm (about 1 nm to 20 nm). The wall surface of the opening 5 is an inclined surface of about 10 ° to 90 ° with respect to the substrate surface. The angle of the inclined surface with respect to the substrate surface can be controlled by the gas pressure of chlorine gas used in the RIE method and the flow rate ratio with other gases. When RIE ends, organic cleaning is performed, and the resist mask M1 is removed by ashing or the like.

Subsequently, using any one of basic solutions such as aqueous potassium hydroxide (KOH), aqueous ammonia (NH ₄ OH), and aqueous TMAH (tetramethylammonium hydroxide) as an etchant, the difference in the opening interface is different. By performing anisotropic wet etching, it is preferable to remove etching damage generated on the boundary surface of the opening by RIE using high-density plasma. Further, the etching damage can be removed not by wet etching but also by low-rate or mild dry etching with an etching rate of 10 nm / min or less in dry etching. It is recommended to use an appropriate etching method according to the situation. At the same time, the m-planes are exposed at part of the end faces of the n-type GaN surface layer 8 and the p-type GaN barrier layer 6.

  The depth of etching damage varies depending on RIE processing conditions. Further, the ratio of the m-plane to the wall surface of the opening 5 varies depending on the specifications of the vertical FET 10 to be manufactured. Therefore, in consideration of these conditions, the etching may be performed under the etching conditions that can remove the etching damage and obtain a predetermined specification. Note that the etchant for performing anisotropic wet etching is not limited to the above etchant. An appropriate etchant may be used depending on the material of the substrate.

  The plan view in the state of FIG. 6B is roughly similar to the state of FIG. 2 except for the second AlGaN diffusion prevention layer 17, the regrowth layer 27, and the gate electrode 11. The opening 5 has a hexagonal planar shape. The wall surface of the opening 5 is constituted by the end surfaces of the n-type GaN surface layer 8 and the p-type GaN layer 6. The bottom surface of the opening 5 is constituted by the n-type GaN drift layer 4.

  A second AlGaN diffusion preventing layer 19 is grown so as to be in contact with and cover these. The growth conditions are as follows. An AlGaN diffusion prevention layer 19 to which no impurities are added is formed using MOCVD. The growth temperature of MOCVD is 1080 ° C. The Al composition ratio is 25% and the film thickness is 5 nm. From the viewpoint of preventing Mg diffusion, the Al composition ratio and the film thickness are not limited to these values, and it is sufficient that the lattice constant is smaller than that of GaN (condition (1)). It is assumed that the above condition (2) is satisfied. For example, AlN having a thickness of 5 nm can function as a diffusion preventing layer.

Next, the regrowth layer 27 is grown using the second AlGaN diffusion prevention layer 19 as a base layer. The regrowth layer 27 includes a GaN electron transit layer 22 and an AlGaN electron supply layer 26 (see FIG. 7). An AlN intermediate layer may be inserted between the GaN electron transit layer 22 and the AlGaN electron supply layer 26. In the growth of the regrowth layer 27, first, the GaN electron transit layer 22 to which no impurities are added is formed using MOCVD. The growth temperature in MOCVD is 1020 ° C. When inserting the AlN intermediate layer, the AlN intermediate layer and the AlGaN electron supply layer 26 are formed at a growth temperature of 1080 ° C. As a result, a regrowth layer 27 including the electron transit layer 22, the AlN intermediate layer, and the electron supply layer 26 is formed along the surface of the opening 28. As an example, the thicknesses of the GaN electron transit layer 22, the AlN intermediate layer, and the AlGaN electron supply layer 26 to be formed are 100 nm, 1 nm, and 24 nm, respectively, and the Al composition ratio of the AlGaN electron supply layer 26 is 25%.
The regrowth is preferably formed at a temperature lower than the growth temperature of the GaN-based semiconductor layer 15 and at a high V / III ratio in order to avoid a decrease in the growth rate on the wall surface of the opening 5. Furthermore, when the growth temperature is raised in order to form the intermediate layer and the electron supply layer 26 from the formation of the electron transit layer 22, the temperature is preferably raised in a short time in order to reduce damage to the crystal surface. For example, it is preferable to raise the temperature in a time of 20 minutes or less. Note that the MBE method may be used instead of the MOCVD method.

Thereafter, a pattern of the conductive portion 6s is formed using a resist in the same manner as the method of forming the opening 28, and a hole reaching the p-type GaN layer 6 is provided by dry etching using the resist pattern as a mask. Then, after removing the resist pattern, a new resist pattern is formed, an electrode metal is formed by vapor deposition, and a conductive portion 6s is formed by lift-off (see FIG. 7A). Thereafter, alloying annealing is performed to obtain ohmic contact with the p-type GaN layer. The conductive portion 6s follows the substantially hexagonal shape except for the portion of the gate wiring 12, following the source electrode in plan view.
Next, the source electrode 31 is formed. In forming the source electrode 31, first, a resist mask pattern having an opening at the position of the source electrode 31 including the top surface of the conductive portion 6s is formed using a normal exposure technique. Next, a source electrode 31 of a Ti / Al film is formed on the surfaces of the conductive portion 6s and the regrowth layer 27 (see FIG. 7B). Thereafter, heat treatment is performed in a nitrogen atmosphere at a temperature of 800 ° C. for 30 seconds. This heat treatment may be omitted and replaced by a heat treatment in the drain electrode forming step described later. By this heat treatment, an alloy layer is formed at the interface between the Ti / Al film and the n-type GaN surface layer 8. As a result, the source electrode 31 having a good ohmic contact with an ohmic contact resistance of about 0.4 Ωmm can be formed. The source electrode 31 may be any metal that is in ohmic contact with the regrown layer 27 other than Ti / Al. In addition, before depositing Ti / Al as the source electrode S, it is preferable to remove the AlGaN electron supply layer 26 and the AlN intermediate layer by etching by RIE using a chlorine-based gas. In this case, there is no electron barrier by the intermediate layer, and the resistance in the ohmic contact can be reduced to 0.2 Ωmm.
In forming the drain electrode 39, first, the wafer surface is protected with a photoresist. A Ti / Al film is formed on the back surface of the GaN substrate 1 by vapor deposition. The photoresist on the wafer surface is removed. Heat treatment is performed at a temperature of 850 ° C. for 30 seconds so that the metal of the substrate 1 having the GaN layer and the drain electrode 39 forms an alloy so that the GaN substrate 1 and the drain electrode 39 are in ohmic contact (see FIG. 7B). .

In forming the gate electrode 11, first, a photoresist having a predetermined opening is formed using a normal exposure technique. Next, a Ni / Au film is formed along the regrowth layer 27 formed in the opening 5 by using a vapor deposition method and a lift-off method (see FIG. 7B). The gate wiring 12 and the gate pad 13 shown in FIG. 2 are preferably formed at the same time. In addition to the Ni / Au film, the gate electrode 11 may be a metal that forms a Schottky junction with a GaN-based semiconductor such as Pt / Au, Pd / Au, and Mo / Au. Further, before forming the gate electrode 11, for example, an insulating film (not shown) of a silicon film is formed to a thickness of 10 nm along the regrowth layer 27 in the opening 5 by using a CVD method or a sputtering method. Also good. Thereby, it can also be set as the vertical FET which has a MIS-HFET structure. As the insulating film, a silicon nitride film or an aluminum oxide film may be used in addition to the silicon oxide film.

Thereafter, as shown in FIG. 8A, an interlayer insulating film 32 is deposited in order to change the gate electrode 11 and the layer and to connect to the source electrode 31. Next, a via hole 32h is formed in the interlayer insulating film 32 on the source electrode 31, and the source conductive layer 33 is formed on the interlayer insulating film 32 as shown in FIG. 8B while filling the via hole 32h.
Thus, the vertical FET 10 shown in FIG. 1 is completed.

  Although the drain electrode 39 is formed on the back surface of the GaN substrate 1, the drain electrode 39 may be formed on the surface of the n-type GaN drift layer 4 facing the source electrode 31. For example, an n-type GaN contact layer can be provided between the n-type GaN drift layer 4 and the GaN substrate 1, and a drain electrode connected to the contact layer from the surface side can be formed.

(Embodiment 2)
FIG. 9 shows a semiconductor device 10 according to the second embodiment of the present invention. A feature of the semiconductor device of the present embodiment is that only the second diffusion prevention layer 19 is formed as a p-type impurity diffusion prevention layer, and this second diffusion prevention layer 19 extends over the entire range of the regrowth layer 27. It is in the point arrange | positioned as a base layer. The first diffusion preventing layer 17 is not disposed.
As shown in FIG. 12, the concentration distribution of Mg in the n-type surface layer 108 is inclined. For this reason, at the surface portion of the n-type surface layer 8, the n-type carrier has an initially set concentration. For this reason, since the second diffusion preventing layer 19 is always disposed as a base layer over the entire area of the regrowth layer 27, adverse effects on the channel can be avoided. That is, the second diffusion prevention layer 19 is disposed over the entire range of the GaN-based semiconductor layer through the source electrode 31 on the n-type surface layer 8 while being recessed in the opening 5. As a result, the on-resistance in the channel can be reliably kept low. Even if the first diffusion prevention layer 17 is not necessary, a serious adverse effect on the channel can be avoided.

(Embodiment 3)
FIG. 10 shows a semiconductor device 10 according to the third embodiment of the present invention. The semiconductor device of the present embodiment is characterized in that only the first diffusion preventing layer 17 is formed as a p-type impurity diffusion preventing layer. The first diffusion prevention layer 17 is opened for each opening 5 and disposed over the range of the GaN-based semiconductor layer 15. The amount of the p-type impurity that diffuses directly from the end face of the p-type layer 6 into the regrowth layer 27 is not so large, and it may be considered that the channel does not have a great adverse effect. In such a case, the diffusion of the p-type impurity can be effectively prevented with only a small process change by disposing the first diffusion prevention layer 17.

  The structures of the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  According to the present invention, the regrowth layer including the channel is provided on the side surface of the opening, the gate electrode is disposed on the channel, and the gate electrode is terminated on the p-type barrier layer, thereby improving the breakdown voltage performance of the gate electrode. be able to. As a result, it is possible to obtain a semiconductor device for large current with low on-resistance and normally off while obtaining high withstand voltage performance.

1 GaN substrate, 2 buffer layer, 4 n-type GaN drift layer, 5 opening, 6 p-type GaN layer, 6s conductive part, 8 n-type GaN surface layer, 10 vertical GaNFET, 11 gate electrode, 12 gate wiring, 13 gate Pad, 15 GaN-based semiconductor layer, 17 first diffusion prevention layer, 19 second diffusion prevention layer, 22 GaN electron transit layer, 26 AlGaN electron supply layer, 27 regrowth layer, 31 source electrode, 32 interlayer insulation film, 32h Via hole of interlayer insulating film, 33 source conductive layer, 39 drain electrode, M1 resist pattern.

Claims (9)

A GaN-based semiconductor device formed in a GaN-based stacked body including an n-type drift layer, a p-type layer located on the n-type drift layer, and an n-type surface layer located on the p-type layer,
The GaN-based laminate is provided with an opening that reaches the n-type drift layer,
A regrowth layer including a channel positioned to cover the opening;
A gate electrode located on the regrowth layer;
A source electrode located on the GaN-based laminate and in contact with the regrown layer;
A drain electrode located so as to sandwich the source electrode and the n-type drift layer;
The regrowth layer includes an electron transit layer and an electron supply layer, and the channel is a two-dimensional electron gas formed at an interface of the electron transit layer with the electron supply layer,
An epitaxial layer having a lattice constant smaller than that of GaN is inserted between at least one of the p-type layer and the n-type surface layer and between the end face of the GaN-based stacked body surrounding the opening and the regrowth layer. A semiconductor device, wherein   A first epitaxial layer having a lattice constant smaller than that of GaN is inserted between the p-type layer and the n-type surface layer, and between the GaN-based stacked body surrounding the opening and the regrowth layer. 2. The semiconductor device according to claim 1, further comprising a second epitaxial layer having a lattice constant smaller than that of GaN.   The semiconductor device according to claim 1, wherein the regrowth layer has no region where the second epitaxial layer is not a base layer.   One chip formed in the range of the GaN-based semiconductor layer, wherein a plurality of the openings are provided, and the first epitaxial layer is opened for each of the openings to form the GaN-based semiconductor layer. The second epitaxial layer is located over a range and is located over the range of the GaN-based semiconductor layer through the source electrode on the n-type surface layer while being recessed in the opening. The semiconductor device according to claim 2.   An interlayer insulating film is located so as to cover the gate electrode and the source electrode, and the source electrode is connected to a conductive layer on the interlayer insulating film through a via hole provided in the interlayer insulating film, The semiconductor device according to claim 4.   The semiconductor device according to claim 1, wherein the p-type layer and the source electrode are connected by a conductive portion.   The semiconductor device according to claim 1, wherein the opening is located in a honeycomb shape or a hook shape. A method for manufacturing a GaN-based semiconductor device using a GaN-based stack,
forming an n-type drift layer and a p-type layer located on the n-type drift layer;
Forming a first epitaxial layer having a lattice constant smaller than that of GaN on the p-type layer;
Forming an n-type surface layer on the first epitaxial layer. A method for manufacturing a semiconductor device, comprising: A method for manufacturing a GaN-based semiconductor device using a GaN-based stack,
forming an n-type drift layer, a p-type layer located on the n-type drift layer, and an n-type surface layer on the p-type layer;
Opening an opening reaching the n-type drift layer by etching in the n-type drift layer, p-type layer and n-type surface layer;
Forming a second epitaxial layer having a lattice constant smaller than that of GaN so as to cover the opening;
Forming a regrowth layer for generating a two-dimensional electron gas on the second epitaxial layer along the opening.

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