WO2013137267A1 - Nitride compound semiconductor element - Google Patents

Nitride compound semiconductor element Download PDF

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WO2013137267A1
WO2013137267A1 PCT/JP2013/056846 JP2013056846W WO2013137267A1 WO 2013137267 A1 WO2013137267 A1 WO 2013137267A1 JP 2013056846 W JP2013056846 W JP 2013056846W WO 2013137267 A1 WO2013137267 A1 WO 2013137267A1
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nitride
layer
electrode
compound semiconductor
semiconductor device
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PCT/JP2013/056846
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French (fr)
Japanese (ja)
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池田　成明
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次世代パワーデバイス技術研究組合
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a nitride compound semiconductor device, and more particularly to a nitride compound semiconductor device having a two-dimensional electron gas layer and a two-dimensional hole gas layer.
  • a GaN-based electronic device which is a nitride-based compound semiconductor element, has a larger band gap energy than a GaAs-based material, and has a high heat resistance and excellent high-temperature operation. For this reason, development of heterojunction field effect transistors (HFETs) using these materials, particularly GaN / AlGaN semiconductors, is being advanced in nitride compound semiconductor devices.
  • HFETs heterojunction field effect transistors
  • a structure in which an HFET structure epilayer is effectively used and an insulating film is formed by etching only in the vicinity of the gate to form a normally-off type has been proposed (see, for example, US Pat. No. 7,038,253). This structure is called a hybrid MOSHFET structure.
  • FIG. 11 shows an example of the structure of such a nitride compound semiconductor device.
  • the conventional nitride-based compound semiconductor element shown in FIG. 11 has a so-called lateral element structure in which current flows in parallel with the main surface.
  • a two-dimensional hole gas is formed on the cap layer 122 side by increasing the Al composition ratio and film thickness of the barrier layer 120. It has been announced that the breakdown voltage of nitride compound semiconductors and the current collapse can be improved by using these. (For example, see Nakajima et al., In Proc. ISPSD, 2011, pp.280-283.)
  • the p-type layer has a low activation rate, so that it is difficult to make an ohmic contact on the growth surface using a particularly fine p-type electrode. Due to this, the structure has a problem because the two-dimensional hole gas cannot be effectively discharged.
  • An object of the present invention is to provide a nitride-based compound semiconductor device that can effectively discharge holes of a two-dimensional hole gas.
  • 1st aspect of this invention is a nitride type compound semiconductor element, Comprising: The two-dimensional electron gas layer formed in the interface of an electron transit layer, an electron supply layer, this electron transit layer, and this electron supply layer A first nitride-based semiconductor layer comprising: a second nitride-based semiconductor layer formed on the first nitride-based semiconductor layer and having a two-dimensional hole gas layer formed at a polarization junction interface; A base electrode formed in contact with the second nitride-based semiconductor layer and in electrical contact with the two-dimensional hole gas layer in which a surface having an orientation different from that of at least one epitaxial growth surface is exposed; Is provided.
  • the second nitride semiconductor layer has an opening contacting the two-dimensional hole gas layer.
  • the opening reaches the surface of the electron supply layer of the first nitride-based semiconductor layer.
  • an angle formed between a side surface and a bottom surface of the opening is 45 ° or more and 175 ° or less, and the base electrode is the opening. It is formed so as to cover the part.
  • an angle formed between a side surface and a bottom surface of the opening is 90 ° or more and 150 ° or less, and the base electrode defines the opening. It is formed to cover.
  • the gate electrode, the drain electrode, the source electrode, and the region between the gate electrode and the drain electrode are arranged in the region.
  • a field effect transistor including a second nitride-based semiconductor layer and performing a normally-off operation.
  • the gate electrode, the drain electrode, the source electrode, and the region between the gate electrode and the drain electrode are arranged in the region.
  • a field effect transistor including a second nitride-based semiconductor layer and having a normally-on operation.
  • an average concentration of the two-dimensional hole gas layer in the electric field relaxation layer decreases from the gate electrode toward the drain electrode. It is going.
  • the electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and the first electrode is directed from the gate electrode toward the drain electrode. It arrange
  • the second nitride may be disposed in an anode electrode, a cathode electrode, and a region between the anode electrode and the cathode electrode.
  • a field relaxation layer including a semiconductor layer.
  • the electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and the first electrode is directed from the anode electrode toward the cathode electrode. It arrange
  • the source electrode or the gate electrode and the base electrode have the same potential.
  • the anode electrode and the base electrode have the same potential.
  • the gate electrode is formed so as to cover at least a part of the base electrode.
  • the anode electrode is formed so as to cover at least a part of the base electrode.
  • FIG. 3C is a sectional view taken along the line CC of the plan view (3). It is explanatory drawing for demonstrating the 1st manufacturing process of the field effect transistor of a 1st Example. It is explanatory drawing for demonstrating the 2nd manufacturing process of the field effect transistor of a 1st Example. It is explanatory drawing for demonstrating the 3rd manufacturing process of the field effect transistor of a 1st Example.
  • FIG. 3 shows a cross-sectional view (3) along the line CC of FIG.
  • FIG. 10 is a schematic block diagram which shows an example of schematic structure of the diode of 4th Example, The schematic top view (1) seen from the upper surface, BB sectional drawing (2) of a top view, and C of a top view -C sectional view (3) is shown.
  • FIG. 10 is a schematic configuration diagram illustrating an example of a schematic configuration of a normally-on type field effect transistor according to a fifth embodiment, which is a schematic plan view as viewed from above (1), and a cross-sectional view along line BB of the plan view (2). And a sectional view taken along line CC of the plan view (3) is shown.
  • It is sectional drawing which shows an example of schematic structure of the conventional nitride type compound semiconductor element.
  • nitride compound semiconductor device of the present embodiment will be described in detail with reference to the drawings.
  • This embodiment is an example of the nitride compound semiconductor element of the present invention, and the present invention is not limited to this embodiment.
  • FIG. 1 is a schematic configuration diagram showing an example of a schematic configuration of the field effect transistor of the present embodiment.
  • FIG. 1 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3).
  • the field effect transistor 10 shown in FIG. 1 is a normally-off GaN-based field effect transistor.
  • the field effect transistor 10 includes a substrate 12, a buffer layer 14, a high resistance layer 16, a channel layer 18, a barrier layer 20, an undoped cap layer 22, a p-type cap layer 24, a dielectric film 26, a source electrode 30, a drain electrode 32, A base electrode 34 and a gate electrode 36 are provided.
  • the substrate 12 is a substrate made of silicon (Si) having a (111) plane as a main surface.
  • the buffer layer 14 formed on the substrate 12 is a buffer layer having a stacked structure in which, for example, an AlN layer and a GaN layer are stacked.
  • the high resistance layer 16 formed on the buffer layer 14 has a higher electrical resistance than the channel layer 18 and is, for example, a GaN layer (GaN: C layer) to which C is added.
  • the channel layer 18 formed on the high resistance layer 16 is an undoped GaN (uid-GaN) layer.
  • the channel layer 18 functions as an electron transit layer of the field effect transistor.
  • the barrier layer 20 formed on the channel layer 18 is an undoped AlGaN layer (barrier layer).
  • the barrier layer 20 functions as an electron supply layer.
  • a barrier layer (undoped AlGaN layer) 20 is heterojunction with the surface of the channel layer (undoped GaN layer) 18 corresponding to the channel length L. Therefore, a two-dimensional electron gas (2DEG) is generated at the interface of the heterojunction portion, and a 2DEG layer is formed.
  • a dielectric film 26, which is a MOS gate insulating film, is formed below the gate electrode 36.
  • the field effect transistor 10 has a structure in which a channel is formed by partially removing the barrier layer 20 by etching under the field effect transistor 10.
  • the two-dimensional electron gas plays a role of reducing the access resistance, and thus exhibits a low on-resistance.
  • the undoped cap layer 22 and the p-type cap layer 24 are disposed between the gate electrode 36 and the drain electrode 32.
  • the undoped cap layer 22 and the p-type cap layer 24 function as an electric field relaxation layer.
  • the undoped cap layer 22 is composed of an undoped In X Ga 1-X N (0 ⁇ X ⁇ 1) layer.
  • the p-type cap layer 24 is composed of a p-In X Ga 1-X N (0 ⁇ X ⁇ 1) layer doped with an impurity such as Mg. Since the undoped cap layer 22 and the p-type cap layer 24 are polarization-bonded, two-dimensional hole gas (2DHG) is generated at the interface of the bonded portions to form a 2DHG layer. Further, the undoped cap layer 22 and the p-type cap layer 24 of the present embodiment have an opening 40 (details will be described later).
  • the base electrode 34 is formed on the p-type cap layer 24 so as to cover the opening 40.
  • the source electrode 30 and the drain electrode 32 are formed in the order of Ti, an alloy of Al and Si, and W from the region closest to the barrier layer 20.
  • a growth apparatus was an MOCVD (Metal Organic Chemical Deposition) apparatus, and the substrate 12 was silicon (111).
  • MOCVD Metal Organic Chemical Deposition
  • the silicon (111) substrate 12 is introduced into the MOCVD apparatus, and the vacuum degree in the MOCVD apparatus is reduced to 1 ⁇ 10 ⁇ 6 hPa or less with a turbo pump, and then the degree of vacuum is set to 100 hPa.
  • the substrate 12 is heated to 1050 ° C.
  • the substrate 12 is rotated at 900 rpm, trimethylaluminum (TMA) as a raw material is introduced into the surface of the substrate 12 at a flow rate of 100 cm 3 / min, and ammonia is 12 liters / min.
  • TMA trimethylaluminum
  • a part of the AlN layer is epitaxially grown. The growth time is 4 min, and the thickness of the AlN layer 2 is about 50 nm.
  • the first step 20 to 80 layers of a laminated film in which, for example, a GaN layer with a thickness of 5 to 100 nm and an AlN layer with a thickness of 1 to 10 nm are laminated are stacked on the AlN layer.
  • a buffer layer is formed.
  • the buffer layer 14 is not limited to this configuration, and may be variously modified depending on the material such as the channel layer 18 and other conditions.
  • the high resistance layer 16 is epitaxially grown on the buffer layer 14 using TMG as a raw material, and C is doped.
  • TMG trimethylgallium
  • ammonia is 12 liters / min
  • the channel layer 18 made of a GaN layer is epitaxially grown.
  • the channel layer 18 functions as an electron transit layer.
  • the growth time of the channel layer 18 was 200 sec, and the film thickness of the channel layer 18 was 300 nm.
  • TMA and 50 cm 3 / min, TMG and 100 cm 3 / min, and ammonia was introduced at a flow rate 12 liter / min, a barrier layer 20 made of Al 0.3 Ga 0.7 N layer Epitaxial growth was performed.
  • the barrier layer 20 functions as an electron supply layer.
  • the growth time of the barrier layer 20 is 40 sec, and the thickness of the barrier layer 20 is 30 nm.
  • TMG is introduced onto the barrier layer 20 at a flow rate of 300 cm 3 / min and ammonia is 12 liter / min to epitaxially grow the undoped cap layer 22 made of a GaN layer.
  • the growth time of the undoped cap layer 22 is 40 sec, and the film thickness of the undoped cap layer 22 is 30 nm.
  • a p-type cap layer 24 made of a p-GaN layer is introduced by introducing TMG at a flow rate of 300 cm 3 / min, ammonia at 12 liters / min, and biscyclopentadienyl magnesium at a flow rate of 300 cm 3 / min. Is epitaxially grown.
  • the growth time of the p-type cap layer 24 is 40 sec, and the film thickness of the p-type cap layer 24 is 20 nm.
  • annealing is performed at 800 ° C. for about 5 minutes in a nitrogen atmosphere.
  • an isolation mesa is formed for element isolation using chlorine gas or the like.
  • the p-type cap layer 24 and the undoped cap layer 22 are masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed.
  • element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas.
  • the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time.
  • the opening 40 is formed in a stripe shape in parallel with the direction of current flow (lateral direction) in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future. .
  • the opening 40 is shown for convenience of explanation.
  • the p-type cap layer 24 is removed by etching in the recess etching portion, preferably the undoped cap layer 22 is removed, and more preferably at least the surface of the barrier layer 20 is removed by etching. Further, even if the etching proceeds more than the surface of the barrier layer 20, it is desirable because the cap layer 22 (2DHG layer) is exposed to obtain a lower contact specific resistance. If the barrier layer 20 is completely removed, the base electrode 34 to be formed later and the channel layer 18 (2DEG layer) are in contact with each other. Therefore, better electrical characteristics can be obtained than in the case of no contact. It will disappear. Therefore, it is desirable not to completely remove the barrier layer 20.
  • the opening width W of the stripe-shaped opening 40 may be at least 0.1 ⁇ m or more, and if there is at least one opening 40, the effect of the present invention is exhibited.
  • the barrier layer 20 is removed by etching only in the region where the gate electrode 36 is formed using chlorine gas or the like.
  • 40 nm of SiO 2 is formed as the dielectric film 26 which is a gate insulating film.
  • the dielectric film 26 of SiO 2 is formed by PCVD or the like using SiH 4 gas and N 2 O gas.
  • the method may be PECVD or APCVD.
  • a region where the source electrode 30 and the drain electrode 32 are to be formed is opened using a resist or the like to expose the surface of the barrier layer 20. In the exposed region, Ti, Al and Si alloy film, and W are sequentially deposited to form the source electrode 30 and the drain electrode 32 by a lift-off method or the like.
  • patterning is performed by using a resist or the like, patterning is performed by providing an opening using a resist or the like in a region where the base electrode 34 is to be formed, and Ni / Au (60 nm / 40 nm) is deposited.
  • the base electrode 34 was formed.
  • the base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.
  • the base electrode 34 is formed so as to cover the opening 40. Since the surface different from the epitaxial growth surface of the 2DHG layer is exposed on the side surface of the opening 40, the base electrode 34 and the 2DHG layer are electrically connected by forming the base electrode 34 in this way.
  • the relationship between the shape of the opening 40 (the recess etching portion of the undoped cap layer 22 and the p-type cap layer 24) and the base electrode 34 will be described with reference to FIGS. 6A, 6B, and 6C.
  • 6A, 6B, and 6C the angle between the side surface 40A of the opening 40 and the bottom surface 40B will be described as ⁇ .
  • 6A, 6B, and 6C the angle ⁇ is illustrated on the base electrode 34 formed so as to cover the opening 40.
  • the angle ⁇ is substantially the same, no problem occurs.
  • the angle ⁇ of the opening 40 is preferably 45 ° or more and 175 ° or less, and more preferably 90 ° or more and 150 ° or less.
  • the fifth step patterning is performed using a resist or the like, patterning is performed in which an opening is formed using a resist or the like in a region where the gate electrode 36 is to be formed, and Ni or Ti or the like is evaporated to form a gate electrode. 36 was formed.
  • the gate electrode 36 may be made of polysilicon or the like. As a result, the field effect transistor 10 shown in FIG. 1 is manufactured.
  • FIG. 7 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the second embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
  • the shapes (upper surface) of the p-type cap layer 24 and the undoped cap layer 22 are shown. The shape seen from) is different.
  • the undoped cap layer 22 and the p-type cap layer 24 are formed so that the area in contact with the barrier layer 20 decreases from the gate electrode 36 side to the drain electrode 32 side.
  • the portion where the p-type cap layer 24 is left (the tip portion where the area is reduced) may be separated from the drain electrode 32 by 0.1 ⁇ m or more, and preferably 1/3 or more between the gate electrode 36 and the drain electrode 32. It is desirable that there is an interval.
  • the portion where the p-type cap layer 24 is left may be at least about 4 ⁇ m if the distance between the gate electrode 36 and the drain electrode 32 is 12 ⁇ m.
  • the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
  • isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like.
  • the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed.
  • element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas.
  • the area to be etched is relatively increased from the gate electrode 36 toward the drain electrode 32 inside the portion left as an island as a layer for forming the base electrode 34. Then, a recess etching portion (opening 40) that comes into contact with the base electrode 34 is formed in the future.
  • the portion where the p-type cap layer 24 is left only needs to be separated from the drain electrode 32 by 0.1 ⁇ m or more, and preferably a space of 1/3 or more between the gate electrode 36 and the drain electrode 32 is left. Is desirable.
  • the portion where the p-type cap layer 24 is left may be at least about 4 ⁇ m if the distance between the gate electrode 36 and the drain electrode 32 is 12 ⁇ m.
  • the gate recess etching, the source electrode 30, the drain electrode 32, the base electrode 34, and the gate electrode 36 are formed, respectively.
  • the illustrated field effect transistor 10 is manufactured.
  • the area of the p-type cap layer 24 and the undoped cap layer 22 is gradually reduced from the gate electrode 36 toward the drain electrode 32 side, so that the average two-dimensional hole gas is reduced.
  • the concentration can be reduced little by little.
  • the electric field concentration at the end of the p-type cap layer 24 and the undoped cap layer 22 on the drain electrode 32 side can be suppressed. Compared with this, leakage current and breakdown voltage can be improved. Further, in the field effect transistor 10 of the present embodiment, the current collapse can be effectively suppressed.
  • FIG. 8 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the third embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
  • the field effect transistor 10 of the present embodiment is such that the base electrode 34 and the gate electrode 36 have the same potential as shown in the sectional view (2) of FIG. That is, it is formed so as to be short-circuited.
  • the base electrode 34 and the gate electrode 36 By short-circuiting the base electrode 34 and the gate electrode 36 in this way, the on-resistance similar to that of the first embodiment can be obtained as the on-characteristic.
  • the drain current conductivity modulation occurs when holes are injected through the p-type layer, so that a drain current that is about 20% larger than that of the first embodiment can be obtained.
  • the off characteristics since the electric field relaxation effect can be obtained as in the first embodiment, the same breakdown voltage and leakage current can be obtained.
  • the base electrode 34 and the gate electrode 36 are short-circuited, they behave as one electrode, so that electrical control can be performed with three terminals of a source, a gate, and a drain.
  • the field effect transistor 10 of the present embodiment it is not necessary to take a terminal called a base electrode, so that the element size can be made more compact.
  • the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
  • isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like.
  • the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed.
  • element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas.
  • the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time.
  • the openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.
  • the gate recess etching, the source electrode 30, the drain electrode 32, and the base electrode 34 are formed in the manner up to the third step and the fourth step of the first embodiment, respectively.
  • the gate electrode 36 is formed by patterning so as to straddle the base electrode 34. Thereby, the field effect transistor 10 shown in FIG. 8 is manufactured.
  • FIG. 9 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the fourth embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
  • the nitride compound semiconductor device of this embodiment is configured as a diode 60 having a cathode electrode 62 and an anode electrode 64 instead of the source electrode 30, the drain electrode 32, and the gate electrode 36 of the first embodiment. .
  • the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
  • isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like.
  • the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed.
  • element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas.
  • the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time.
  • the openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.
  • a region where the cathode electrode 62 is to be formed is opened using a resist or the like to expose the surface of the barrier layer 20.
  • Ti, an alloy film of Al and Si, and W are sequentially deposited, and the cathode electrode 62 is formed by a lift-off method or the like.
  • the fourth step of the present embodiment for forming the base electrode 34 patterning is performed using a resist or the like, and patterning is performed in which an opening is formed using a resist or the like in a region where the base electrode 34 is to be formed. Then, Ni / Au (60 nm / 40 nm) is deposited to form the base electrode 34.
  • the base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.
  • patterning is performed using a resist or the like, patterning is performed by providing an opening using a resist or the like in a region where the anode electrode 64 is to be formed, and Ni or Pd is deposited.
  • the anode electrode A is formed.
  • the anode electrode 64 may be made of polysilicon or the like. As a result, the diode shown in FIG. 9 is manufactured.
  • FIG. 10 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the fifth embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
  • the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
  • isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like.
  • a region for forming the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed.
  • element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas.
  • the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time.
  • the openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.
  • the source electrode 30 and the drain electrode 32 are formed in the same manner as the third step of the first embodiment. Since the field effect transistor 70 of this embodiment is normally on, a gate recess is not formed unlike the first embodiment.
  • the fourth step of the present embodiment for forming the base electrode 34 patterning is performed using a resist or the like, and patterning is performed by providing an opening using a resist or the like at a position where the base electrode 34 is to be formed.
  • Ni / Au 60 nm / 40 nm
  • the base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.
  • the third step patterning is performed using a resist or the like, patterning is performed in which an opening is formed using a resist or the like in a region where the gate electrode 36 is to be formed, and Ni or Ti or the like is evaporated to form the gate electrode 36.
  • the gate electrode 36 may be made of polysilicon or the like.
  • a part of the dielectric film 26 in a region where the gate electrode 36 is formed can be removed to form a gate portion for Schottky junction. As a result, the field effect transistor 70 shown in FIG. 10 is manufactured.
  • the undoped cap layer 22 and the p-type cap layer 24 having the 2DHG layer are partially recessed by etching.
  • the base electrode 34 is formed so as to cover the opening 40 where the surface different from the epitaxial growth surface of the 2DHG layer is exposed. Therefore, the nitride-based compound semiconductor device according to the present invention can easily make ohmic contact with the base electrode 34. In the nitride-based compound semiconductor device according to the present invention, 2DHG holes can be effectively discharged by this configuration.
  • the channel layer 18 is an undoped layer, so that current collapse can be suppressed and the short-circuit tolerance can be maintained while maintaining forward characteristics and reverse characteristics.
  • the increase rate of the on-resistance as a current collapse deteriorated to 1.5 times or more at 600 V. It was confirmed that the field effect transistor 10 of this example was improved to 1.1 times or less. Further, since the discharge of holes can be improved, the load short-circuit withstand capability is also improved, and the conventional nitride-based compound semiconductor device shown in FIG. Then, the withstand voltage at 100 A / cm 2 and 600 V was improved to 700 mJ.
  • a hybrid MOSHFET structure is desirable.
  • 2DEG carriers under the gate electrode 36 can be removed by recess etching of the gate electrode 36.
  • This etching and design conditions have the effect that they can be designed independently without affecting the design parameters of 2DHG.
  • the present invention can also be applied to a method of forming the dielectric film 26, which is a gate insulating film, without removing the barrier layer 20 and leaving several nm.
  • the nitride-based compound semiconductor device according to the present invention can be applied to a high voltage inverter or converter. From the above, it is possible to realize a GaN field effect transistor having a high breakdown voltage and high reliability.
  • the shape of the opening 40 shown in each of the above embodiments is a specific example, and is not limited to this.
  • the opening 40 may have other shapes such as a circular shape instead of the stripe shape.
  • the opening 40 is formed so that the areas of the undoped cap layer 22 and the p-type cap layer 24 are reduced from the gate electrode 36 side toward the drain electrode 32 side. Absent.
  • the opening 40 may be formed to have the same area (alphabet “E” shape) toward the drain side.
  • the undoped cap layer 22 and the p-type cap layer 24 may be formed in stripes with a plurality of intervals (corresponding to the opening 40).
  • the substrate 12 is a silicon substrate
  • any substrate capable of crystal growth of GaN such as a SiC substrate other than a silicon substrate, a sapphire substrate, a GaN substrate, an MgO substrate, and a ZnO substrate can be used. Needless to say, the elements on the substrate also hold true.

Abstract

The present invention is a nitride compound semiconductor element that is capable of effectively discharging a two-dimensional hole gas hole. In other words, a partially recessed structure (an opening part) is made by etching an undoped cap layer and a p-type cap layer that have a 2DHG layer, and is configured so as to easily make Ohmic contact with a base electrode. This configuration enables the effective discharge of a 2DHG hole. Also, making the channel layer an undoped layer enables the suppression of current collapses while maintaining forward characteristics and backward characteristics, and enables short circuit resistance.

Description

窒化物系化合物半導体素子Nitride compound semiconductor device
　本発明は、窒化物系化合物半導体素子、特に二次元電子ガス層及び二次元ホールガス層を有する窒化物系化合物半導体素子に関するものである。 The present invention relates to a nitride compound semiconductor device, and more particularly to a nitride compound semiconductor device having a two-dimensional electron gas layer and a two-dimensional hole gas layer.
　窒化物系化合物半導体素子であるＧａＮ系電子デバイスは、ＧａＡｓ系の材料に比べてそのバンドギャップエネルギーが大きく、しかも耐熱度が高く高温動作に優れている。そのため、窒化物系化合物半導体素子では、これらの材料、特にＧａＮ／ＡｌＧａＮ系半導体を用いたヘテロ接合電界効果トランジスタ（Hetero-structure Field Effect Transistor：ＨＦＥＴ）の開発が進められている。近年、ＨＦＥＴ構造エピ層を有効に活用し、ゲート付近のみをエッチングして絶縁膜を形成し、ノーマリオフ型にする構造が提案されている（例えば、米国特許第7,038,253号明細書参照）。この構造は、ハイブリッドＭＯＳＨＦＥＴ構造と呼ばれている。 A GaN-based electronic device, which is a nitride-based compound semiconductor element, has a larger band gap energy than a GaAs-based material, and has a high heat resistance and excellent high-temperature operation. For this reason, development of heterojunction field effect transistors (HFETs) using these materials, particularly GaN / AlGaN semiconductors, is being advanced in nitride compound semiconductor devices. In recent years, a structure in which an HFET structure epilayer is effectively used and an insulating film is formed by etching only in the vicinity of the gate to form a normally-off type has been proposed (see, for example, US Pat. No. 7,038,253). This structure is called a hybrid MOSHFET structure.
　一方、近年、ＡｌＧａＮ／ＧａＮの分極接合（ＰＪ：Polarization Junction）の界面に形成される二次元ホールガスを利用した窒化物系化合物半導体素子が提案されている（例えば、特開２０１１－８２３３１号公報参照）。図１１には、このような窒化物系化合物半導体素子の構造の一例を示す。図１１に示した従来の窒化物系化合物半導体素子は、主面と並行に電流が流れるいわゆる横型素子構造をとっている。当該構造によれば、基板１１２側からチャネル層１１８（ＧａＮ）／バリア層１２０（ＡｌＧａＮ）／キャップ層１２２（ＧａＮ）／ｐ型キャップ層１２４（ＧａＮ）において、従来のチャネル層１１８／バリア層１２０のチャネル層１１８側に形成される二次元電子ガス層に加えて、バリア層１２０のＡｌ組成比や膜厚をあげることによって、キャップ層１２２側に二次元ホールガスが形成される。これらを利用することで、窒化物系化合物半導体の破壊電圧の向上、電流コラプスの改善ができるとの発表がされている。（例えば、Nakajima et al., in Proc. ISPSD, 2011, pp.280-283.参照） On the other hand, in recent years, a nitride-based compound semiconductor device using a two-dimensional hole gas formed at the interface of AlGaN / GaN polarization junction (PJ: Polarization Junction) has been proposed (for example, JP-A-2011-82331). reference). FIG. 11 shows an example of the structure of such a nitride compound semiconductor device. The conventional nitride-based compound semiconductor element shown in FIG. 11 has a so-called lateral element structure in which current flows in parallel with the main surface. According to this structure, the conventional channel layer 118 / barrier layer 120 in the channel layer 118 (GaN) / barrier layer 120 (AlGaN) / cap layer 122 (GaN) / p-type cap layer 124 (GaN) from the substrate 112 side. In addition to the two-dimensional electron gas layer formed on the channel layer 118 side, a two-dimensional hole gas is formed on the cap layer 122 side by increasing the Al composition ratio and film thickness of the barrier layer 120. It has been announced that the breakdown voltage of nitride compound semiconductors and the current collapse can be improved by using these. (For example, see Nakajima et al., In Proc. ISPSD, 2011, pp.280-283.)
　しかしながら、上記図１１に例示した窒化物系化合物半導体素子の構造には問題があった。すなわち、当該構造では、ｐ型層は活性化率が低いことに起因して、特に微細なｐ型電極を用いて成長面上にオーミックコンタクトをとることが難しい構成である。このことに起因し、当該構造では、２次元ホールガスの排出が効果的に行えないため問題が発生した。 However, there is a problem with the structure of the nitride compound semiconductor device illustrated in FIG. That is, in this structure, the p-type layer has a low activation rate, so that it is difficult to make an ohmic contact on the growth surface using a particularly fine p-type electrode. Due to this, the structure has a problem because the two-dimensional hole gas cannot be effectively discharged.
　本発明は、二次元ホールガスのホールの排出を効果的に行わせることができる、窒化物系化合物半導体素子を提供することを目的とする。 An object of the present invention is to provide a nitride-based compound semiconductor device that can effectively discharge holes of a two-dimensional hole gas.
　本発明の第１の態様は、窒化物系化合物半導体素子であって、電子走行層と、電子供給層と、該電子走行層と該電子供給層との界面に形成される二次元電子ガス層を有する第１窒化物系半導体層と、前記第１窒化物系半導体層上に形成されており、分極接合の界面に形成される二次元ホールガス層を有する第２窒化物系半導体層と、前記第２窒化物系半導体層に接して形成されており、少なくとも１箇所のエピタキシャル成長面と異なる方位をもつ面が露出された前記二次元ホールガス層に電気的に接触しているベース電極と、を備える。 1st aspect of this invention is a nitride type compound semiconductor element, Comprising: The two-dimensional electron gas layer formed in the interface of an electron transit layer, an electron supply layer, this electron transit layer, and this electron supply layer A first nitride-based semiconductor layer comprising: a second nitride-based semiconductor layer formed on the first nitride-based semiconductor layer and having a two-dimensional hole gas layer formed at a polarization junction interface; A base electrode formed in contact with the second nitride-based semiconductor layer and in electrical contact with the two-dimensional hole gas layer in which a surface having an orientation different from that of at least one epitaxial growth surface is exposed; Is provided.
　本発明の第２の態様は、上記第１の態様において、前記第２窒化物系半導体層が、前記二次元ホールガス層に接触する開口部を有している。 In a second aspect of the present invention, in the first aspect, the second nitride semiconductor layer has an opening contacting the two-dimensional hole gas layer.
　本発明の第３の態様は、上記第２の態様において、前記開口部が、前記第１窒化物系半導体層の前記電子供給層の表面に至っている。 According to a third aspect of the present invention, in the second aspect, the opening reaches the surface of the electron supply layer of the first nitride-based semiconductor layer.
　本発明の第４の態様は、上記第２の態様または第３の態様において、前記開口部の側面と、底面とのなす角度が４５°以上、１７５°以下であり、前記ベース電極が前記開口部を覆うように形成されている。 According to a fourth aspect of the present invention, in the second aspect or the third aspect, an angle formed between a side surface and a bottom surface of the opening is 45 ° or more and 175 ° or less, and the base electrode is the opening. It is formed so as to cover the part.
　本発明の第５態様は、上記第２の態様または第３の態様において前記開口部の側面と、底面とのなす角度が９０°以上、１５０°以下であり、前記ベース電極が前記開口部を覆うように形成されている。 According to a fifth aspect of the present invention, in the second or third aspect, an angle formed between a side surface and a bottom surface of the opening is 90 ° or more and 150 ° or less, and the base electrode defines the opening. It is formed to cover.
　本発明の第６の態様は、上記第１の態様から第５の態様のいずれかにおいて、ゲート電極と、ドレイン電極と、ソース電極と、前記ゲート電極と前記ドレイン電極との間の領域に前記第２窒化物系半導体層を含む電界緩和層と、を備え、ノーマリオフ動作をする電界効果トランジスタである。 According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the gate electrode, the drain electrode, the source electrode, and the region between the gate electrode and the drain electrode are arranged in the region. A field effect transistor including a second nitride-based semiconductor layer and performing a normally-off operation.
　本発明の第７の態様は、上記第１の態様から第５の態様のいずれかにおいて、ゲート電極と、ドレイン電極と、ソース電極と、前記ゲート電極と前記ドレイン電極との間の領域に前記第２窒化物系半導体層を含む電界緩和層と、を備え、ノーマリオン動作をする電界効果トランジスタである。 According to a seventh aspect of the present invention, in any one of the first to fifth aspects, the gate electrode, the drain electrode, the source electrode, and the region between the gate electrode and the drain electrode are arranged in the region. A field effect transistor including a second nitride-based semiconductor layer and having a normally-on operation.
　本発明の第８の態様は、上記第６の態様または第７の態様において、前記電界緩和層における前記二次元ホールガス層の平均濃度が、前記ゲート電極から前記ドレイン電極に向かって減少していくものである。 According to an eighth aspect of the present invention, in the sixth aspect or the seventh aspect, an average concentration of the two-dimensional hole gas layer in the electric field relaxation layer decreases from the gate electrode toward the drain electrode. It is going.
　本発明の第９の態様は、上記第８の態様において、前記電界緩和層が、ｐ型キャリアを有する窒化物系半導体層を有しており、前記ゲート電極から前記ドレイン電極に向かって前記第１窒化物系半導体層に接する面積を低減させていくよう配置されている。 According to a ninth aspect of the present invention, in the eighth aspect, the electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and the first electrode is directed from the gate electrode toward the drain electrode. It arrange | positions so that the area which touches 1 nitride type semiconductor layer may be reduced.
　本発明の第１０の態様は、上記第１の態様から第５の態様のいずれかにおいて、アノード電極と、カソード電極と、前記アノード電極と前記カソード電極との間の領域に前記第２窒化物系半導体層を含む電界緩和層と、を備えたダイオードである。 According to a tenth aspect of the present invention, in any one of the first to fifth aspects, the second nitride may be disposed in an anode electrode, a cathode electrode, and a region between the anode electrode and the cathode electrode. And a field relaxation layer including a semiconductor layer.
　本発明の第１１の態様は、上記第１０の態様において、前記電界緩和層が、ｐ型キャリアを有する窒化物系半導体層を有しており、前記アノード電極から前記カソード電極に向かって前記第１窒化物系半導体層に接する面積を低減させていくよう配置されている。 According to an eleventh aspect of the present invention, in the tenth aspect, the electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and the first electrode is directed from the anode electrode toward the cathode electrode. It arrange | positions so that the area which touches 1 nitride type semiconductor layer may be reduced.
　本発明の第１２の態様は、上記第６の態様から第９の態様のいずれかにおいて、前記ソース電極または前記ゲート電極と、前記ベース電極と、が同一の電位をもつ。 In a twelfth aspect of the present invention, in any one of the sixth to ninth aspects, the source electrode or the gate electrode and the base electrode have the same potential.
　本発明の第１３の態様は、上記第１０の態様または第１１の態様において、前記アノード電極と、前記ベース電極と、が同一の電位をもつ。 In a thirteenth aspect of the present invention, in the tenth aspect or the eleventh aspect, the anode electrode and the base electrode have the same potential.
　本発明の第１４の態様は、上記第１２の態様において、前記ゲート電極が、前記ベース電極の少なくとも一部を覆うように形成されている。 According to a fourteenth aspect of the present invention, in the twelfth aspect, the gate electrode is formed so as to cover at least a part of the base electrode.
　本発明の第１５の態様は、上記第１３の態様において、前記アノード電極が、前記ベース電極の少なくとも一部を覆うように形成されている。 According to a fifteenth aspect of the present invention, in the thirteenth aspect, the anode electrode is formed so as to cover at least a part of the base electrode.
　本発明の上記態様によれば、二次元ホールガスのホールの排出を効果的に行わせることができる、という効果を奏する。 According to the above aspect of the present invention, there is an effect that holes of the two-dimensional hole gas can be effectively discharged.
第１の実施例のノーマリオフ型の電界効果トランジスタの概略構成の一例を示す概略構成図であり、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram which shows an example of schematic structure of the normally-off type field effect transistor of 1st Example, The schematic top view (1) seen from the upper surface, BB sectional drawing (2) of a top view, FIG. 3C is a sectional view taken along the line CC of the plan view (3). 第１の実施例の電界効果トランジスタの第１の製造工程を説明するための説明図である。It is explanatory drawing for demonstrating the 1st manufacturing process of the field effect transistor of a 1st Example. 第１の実施例の電界効果トランジスタの第２の製造工程を説明するための説明図である。It is explanatory drawing for demonstrating the 2nd manufacturing process of the field effect transistor of a 1st Example. 第１の実施例の電界効果トランジスタの第３の製造工程を説明するための説明図である。It is explanatory drawing for demonstrating the 3rd manufacturing process of the field effect transistor of a 1st Example. 第１の実施例の電界効果トランジスタの第４の製造工程を説明するための説明図である。It is explanatory drawing for demonstrating the 4th manufacturing process of the field effect transistor of a 1st Example. アンドープキャップ層及びｐ型キャップ層の開口部における、側面と底面との角度θについて説明するための説明図であり、角度θが略９０°である場合を示している。It is explanatory drawing for demonstrating angle (theta) of the side surface and bottom face in the opening part of an undoped cap layer and a p-type cap layer, and has shown the case where angle (theta) is about 90 degrees. アンドープキャップ層及びｐ型キャップ層の開口部における、側面と底面との角度θについて説明するための説明図であり、角度θが９０°未満である場合を示している。It is explanatory drawing for demonstrating angle (theta) of the side surface and bottom face in the opening part of an undoped cap layer and a p-type cap layer, and has shown the case where angle (theta) is less than 90 degrees. アンドープキャップ層及びｐ型キャップ層の開口部における、側面と底面との角度θについて説明するための説明図であり、角度θが９０°を越える場合を示している。It is explanatory drawing for demonstrating angle (theta) of the side surface and bottom face in the opening part of an undoped cap layer and a p-type cap layer, and has shown the case where angle (theta) exceeds 90 degrees. 第２の実施例の電界効果トランジスタの概略構成の一例を示す概略構成図であり、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。It is a schematic block diagram which shows an example of schematic structure of the field effect transistor of 2nd Example, the schematic top view (1) seen from the upper surface, the BB sectional drawing (2) of a top view, and a top view FIG. 3 shows a cross-sectional view (3) along the line CC of FIG. 第３の実施例の電界効果トランジスタの概略構成の一例を示す概略構成図であり、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。It is a schematic block diagram which shows an example of schematic structure of the field effect transistor of 3rd Example, The schematic top view (1) seen from the upper surface, BB sectional drawing (2) of a top view, and a top view FIG. 3 shows a cross-sectional view (3) along the line CC of FIG. 第４の実施例のダイオードの概略構成の一例を示す概略構成図であり、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。It is a schematic block diagram which shows an example of schematic structure of the diode of 4th Example, The schematic top view (1) seen from the upper surface, BB sectional drawing (2) of a top view, and C of a top view -C sectional view (3) is shown. 第５の実施例のノーマリオン型の電界効果トランジスタの概略構成の一例を示す概略構成図であり、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。FIG. 10 is a schematic configuration diagram illustrating an example of a schematic configuration of a normally-on type field effect transistor according to a fifth embodiment, which is a schematic plan view as viewed from above (1), and a cross-sectional view along line BB of the plan view (2). And a sectional view taken along line CC of the plan view (3) is shown. 従来の窒化物系化合物半導体素子の概略構成の一例を示す断面図である。It is sectional drawing which shows an example of schematic structure of the conventional nitride type compound semiconductor element.
　図面を参照して本実施の形態の窒化物系化合物半導体素子について詳細に説明する。なお、本実施の形態は本発明の窒化物系化合物半導体素子の一例であり、本実施の形態により本発明が限定されるものではない。 The nitride compound semiconductor device of the present embodiment will be described in detail with reference to the drawings. This embodiment is an example of the nitride compound semiconductor element of the present invention, and the present invention is not limited to this embodiment.
　［第１の実施例］
　第１の実施例では、本発明の窒化物系化合物半導体素子がノーマリオフ型の電界効果トランジスタである場合について説明する。 [First embodiment]
In the first embodiment, the case where the nitride compound semiconductor element of the present invention is a normally-off field effect transistor will be described.
　まず、電界効果トランジスタの構成について説明する。図１には、本実施例の電界効果トランジスタの概略構成の一例を示す概略構成図を示す。図１には、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。 First, the structure of the field effect transistor will be described. FIG. 1 is a schematic configuration diagram showing an example of a schematic configuration of the field effect transistor of the present embodiment. FIG. 1 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3).
　図１に示した電界効果トランジスタ１０は、ノーマリオフ型ＧａＮ系電界効果トランジスタである。電界効果トランジスタ１０は、基板１２、バッファ層１４、高抵抗層１６、チャネル層１８、バリア層２０、アンドープキャップ層２２、ｐ型キャップ層２４、誘電体膜２６、ソース電極３０、ドレイン電極３２、ベース電極３４、及びゲート電極３６を備えている。 The field effect transistor 10 shown in FIG. 1 is a normally-off GaN-based field effect transistor. The field effect transistor 10 includes a substrate 12, a buffer layer 14, a high resistance layer 16, a channel layer 18, a barrier layer 20, an undoped cap layer 22, a p-type cap layer 24, a dielectric film 26, a source electrode 30, a drain electrode 32, A base electrode 34 and a gate electrode 36 are provided.
　基板１２は、（１１１）面を主表面とするシリコン（Ｓｉ）からなる基板である。基板１２上に形成されたバッファ層１４は、例えばＡｌＮ層とＧａＮ層とが積層された積層構造のバッファ層である。バッファ層１４上に形成された高抵抗層１６は、チャネル層１８よりも電気抵抗が高く、例えば、Ｃが添加されたＧａＮ層（ＧａＮ：Ｃ層）である。 The substrate 12 is a substrate made of silicon (Si) having a (111) plane as a main surface. The buffer layer 14 formed on the substrate 12 is a buffer layer having a stacked structure in which, for example, an AlN layer and a GaN layer are stacked. The high resistance layer 16 formed on the buffer layer 14 has a higher electrical resistance than the channel layer 18 and is, for example, a GaN layer (GaN: C layer) to which C is added.
　高抵抗層１６上に形成されたチャネル層１８は、アンドープＧａＮ(ｕｉｄ－ＧａＮ)層である。チャネル層１８は、電界効果トランジスタの電子走行層として機能する。また、チャネル層１８上に形成されたバリア層２０は、アンドープＡｌＧａＮ層（バリア層）である。バリア層２０は、電子供給層として機能する。ここで、チャネルの長さＬに相当するチャネル層（アンドープＧａＮ層）１８の表面には、バリア層（アンドープＡｌＧａＮ層）２０がヘテロ接合している。そのため、ヘテロ接合している部分の界面には２次元電子ガス（２ＤＥＧ）が発生し、２ＤＥＧ層を形成する。ゲート電極３６下部にはＭＯＳのゲート絶縁膜である誘電体膜２６が形成される。電界効果トランジスタ１０では、その下をエッチングによってバリア層２０を部分的に除去し、チャネルを形成した構造になっている。また、電界効果トランジスタ１０では、２次元電子ガスがアクセス抵抗を低減する役割をするため、低オン抵抗を示すようになる。 The channel layer 18 formed on the high resistance layer 16 is an undoped GaN (uid-GaN) layer. The channel layer 18 functions as an electron transit layer of the field effect transistor. The barrier layer 20 formed on the channel layer 18 is an undoped AlGaN layer (barrier layer). The barrier layer 20 functions as an electron supply layer. Here, a barrier layer (undoped AlGaN layer) 20 is heterojunction with the surface of the channel layer (undoped GaN layer) 18 corresponding to the channel length L. Therefore, a two-dimensional electron gas (2DEG) is generated at the interface of the heterojunction portion, and a 2DEG layer is formed. A dielectric film 26, which is a MOS gate insulating film, is formed below the gate electrode 36. The field effect transistor 10 has a structure in which a channel is formed by partially removing the barrier layer 20 by etching under the field effect transistor 10. In the field effect transistor 10, the two-dimensional electron gas plays a role of reducing the access resistance, and thus exhibits a low on-resistance.
　さらに、アンドープキャップ層２２及びｐ型キャップ層２４がゲート電極３６とドレイン電極３２との間に配置されている。アンドープキャップ層２２及びｐ型キャップ層２４は、電界緩和層として機能する。アンドープキャップ層２２は、アンドープＩｎＸＧａ１－ＸＮ (０≦Ｘ＜１）層からなる。ｐ型キャップ層２４は、Ｍｇなどの不純物をドーピングしたｐ－ＩｎＸＧａ１－ＸＮ（０≦Ｘ＜１）層からなる。アンドープキャップ層２２とｐ型キャップ層２４とは、分極接合しているため、接合している部分の界面には、２次元ホールガス（２ＤＨＧ）が発生し、２ＤＨＧ層を形成する。また、本実施例のアンドープキャップ層２２及びｐ型キャップ層２４は、開口部４０（詳細後述）を有している。 Further, the undoped cap layer 22 and the p-type cap layer 24 are disposed between the gate electrode 36 and the drain electrode 32. The undoped cap layer 22 and the p-type cap layer 24 function as an electric field relaxation layer. The undoped cap layer 22 is composed of an undoped In X Ga 1-X N (0 ≦ X <1) layer. The p-type cap layer 24 is composed of a p-In X Ga 1-X N (0 ≦ X <1) layer doped with an impurity such as Mg. Since the undoped cap layer 22 and the p-type cap layer 24 are polarization-bonded, two-dimensional hole gas (2DHG) is generated at the interface of the bonded portions to form a 2DHG layer. Further, the undoped cap layer 22 and the p-type cap layer 24 of the present embodiment have an opening 40 (details will be described later).
　ベース電極３４は、ｐ型キャップ層２４上に、開口部４０を覆うように形成されている。また、ソース電極３０およびドレイン電極３２はバリア層２０に最も近接した領域からＴｉ、ＡｌとＳｉの合金、及びＷの順に形成されている。 The base electrode 34 is formed on the p-type cap layer 24 so as to cover the opening 40. The source electrode 30 and the drain electrode 32 are formed in the order of Ti, an alloy of Al and Si, and W from the region closest to the barrier layer 20.
　次に、本実施例の電界効果トランジスタ１０の製造方法の一例について説明する。なお、電界効果トランジスタ１０の製造にあたり、成長装置はＭＯＣＶＤ（Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）装置を用い、基板１２はシリコン（１１１）を用いた。 Next, an example of a method for manufacturing the field effect transistor 10 of this embodiment will be described. In manufacturing the field effect transistor 10, a growth apparatus was an MOCVD (Metal Organic Chemical Deposition) apparatus, and the substrate 12 was silicon (111).
　１）エピタキシャル基板を製造する第１工程について図２を参照して説明する。 1) A first step of manufacturing an epitaxial substrate will be described with reference to FIG.
　まず、第１工程では、シリコン（１１１）基板１２をＭＯＣＶＤ装置内に導入し、ターボポンプでＭＯＣＶＤ装置内の真空度を１×１０－６ｈＰａ以下になるまで真空引きした後、真空度を１００ｈＰａとし基板１２を１０５０℃に昇温する。温度が安定したところで、基板１２を９００ｒｐｍで回転させ、原料となるトリメチルアルミニウム（ＴＭＡ）を１００ｃｍ３／ｍｉｎ、及びアンモニアを１２リットル／ｍｉｎの流量で基板１２の表面に導入し、バッファ層１４の一部であるＡｌＮ層をエピタキシャル成長させる。成長時間は、４ｍｉｎで当該ＡｌＮ層２の膜厚は５０ｎｍ程度である。 First, in the first step, the silicon (111) substrate 12 is introduced into the MOCVD apparatus, and the vacuum degree in the MOCVD apparatus is reduced to 1 × 10 −6 hPa or less with a turbo pump, and then the degree of vacuum is set to 100 hPa. The substrate 12 is heated to 1050 ° C. When the temperature is stabilized, the substrate 12 is rotated at 900 rpm, trimethylaluminum (TMA) as a raw material is introduced into the surface of the substrate 12 at a flow rate of 100 cm 3 / min, and ammonia is 12 liters / min. A part of the AlN layer is epitaxially grown. The growth time is 4 min, and the thickness of the AlN layer 2 is about 50 nm.
　その後、第１工程では、当該ＡｌＮ層上に、例えば、膜厚が５～１００ｎｍのＧａＮ層と、膜厚が１～１０ｎｍのＡｌＮ層とが積層された積層膜を、２０～８０層重ねて、バッファ層を形成する。なお、バッファ層１４は、この構成に限定されず、チャネル層１８などの材料や、その他の条件によって種々変形されてよい。さらに、第１工程では、バッファ層１４上に、ＴＭＧを原料として、高抵抗層１６をエピタキシャル成長させ、Ｃをドープさせる。 Thereafter, in the first step, 20 to 80 layers of a laminated film in which, for example, a GaN layer with a thickness of 5 to 100 nm and an AlN layer with a thickness of 1 to 10 nm are laminated are stacked on the AlN layer. A buffer layer is formed. The buffer layer 14 is not limited to this configuration, and may be variously modified depending on the material such as the channel layer 18 and other conditions. Further, in the first step, the high resistance layer 16 is epitaxially grown on the buffer layer 14 using TMG as a raw material, and C is doped.
　次に、第１工程では、トリメチルガリウム（ＴＭＧ）を３００ｃｍ３／ｍｉｎ、アンモニアを１２リットル／ｍｉｎの流量で高抵抗層１６の上に導入して、ＧａＮ層からなるチャネル層１８をエピタキシャル成長させる。チャネル層１８は、電子走行層として機能する。チャネル層１８の成長時間は２００ｓｅｃであり、チャネル層１８の膜厚は３００ｎｍであった。 Next, in the first step, trimethylgallium (TMG) is introduced onto the high resistance layer 16 at a flow rate of 300 cm 3 / min and ammonia is 12 liters / min, and the channel layer 18 made of a GaN layer is epitaxially grown. The channel layer 18 functions as an electron transit layer. The growth time of the channel layer 18 was 200 sec, and the film thickness of the channel layer 18 was 300 nm.
　次に、第１工程では、ＴＭＡを５０ｃｍ３／ｍｉｎ、ＴＭＧを１００ｃｍ３／ｍｉｎ、及びアンモニアを１２リットル／ｍｉｎの流量で導入し、Ａｌ０．３Ｇａ０．７Ｎ層からなるバリア層２０のエピタキシャル成長を行った。バリア層２０は、電子供給層として機能する。バリア層２０の成長時間は４０ｓｅｃであり、バリア層２０の膜厚は３０ｎｍである。 Next, in the first step, TMA and 50 cm 3 / min, TMG and 100 cm 3 / min, and ammonia was introduced at a flow rate 12 liter / min, a barrier layer 20 made of Al 0.3 Ga 0.7 N layer Epitaxial growth was performed. The barrier layer 20 functions as an electron supply layer. The growth time of the barrier layer 20 is 40 sec, and the thickness of the barrier layer 20 is 30 nm.
　次に、第１工程では、ＴＭＧを３００ｃｍ３／ｍｉｎ、アンモニアを１２リットル／ｍｉｎの流量でバリア層２０の上に導入してＧａＮ層からなるアンドープキャップ層２２をエピタキシャル成長させる。アンドープキャップ層２２の成長時間は４０ｓｅｃであり、アンドープキャップ層２２の膜厚は３０ｎｍである。 Next, in the first step, TMG is introduced onto the barrier layer 20 at a flow rate of 300 cm 3 / min and ammonia is 12 liter / min to epitaxially grow the undoped cap layer 22 made of a GaN layer. The growth time of the undoped cap layer 22 is 40 sec, and the film thickness of the undoped cap layer 22 is 30 nm.
　さらに、第１工程では、ＴＭＧを３００ｃｍ３／ｍｉｎ、アンモニアを１２リットル／ｍｉｎ、及びビスシクロペンタジエニルマグネシウムを３００ｃｍ３／ｍｉｎの流量で導入してｐ－ＧａＮ層からなるｐ型キャップ層２４をエピタキシャル成長させる。ｐ型キャップ層２４の成長時間は４０ｓｅｃであり、ｐ型キャップ層２４の膜厚は２０ｎｍである。第工程では、その後、ｐ層の活性化アニールをするため、窒素雰囲気、８００℃で５分程度アニールを実施する。 Further, in the first step, a p-type cap layer 24 made of a p-GaN layer is introduced by introducing TMG at a flow rate of 300 cm 3 / min, ammonia at 12 liters / min, and biscyclopentadienyl magnesium at a flow rate of 300 cm 3 / min. Is epitaxially grown. The growth time of the p-type cap layer 24 is 40 sec, and the film thickness of the p-type cap layer 24 is 20 nm. In the second step, in order to perform activation annealing of the p layer, annealing is performed at 800 ° C. for about 5 minutes in a nitrogen atmosphere.
　２）第２工程について図３を参照して説明する。 2) The second step will be described with reference to FIG.
　次に、第２工程では、塩素ガスなどを用いて素子分離のためのアイソレーションメサ形成を実施する。その後、ｐ型キャップ層２４及びアンドープキャップ層２２をレジストなどでマスクし、バリア層２０の表面が露出するまで塩素ガスなどを用いて、ドライエッチングを行う。このとき、フッ素系のガスを混合する、あるいは酸素系のガスを混合するなどして、選択的にエッチングを行うことで、良好な再現性・歩留まりの素子形成が実現できる。第２工程では、その際に、ベース電極３４を形成するための層として島状に残した部分の内側に開口部４０を同時に形成する。開口部４０は、ｐ型キャップ層２４及びアンドープキャップ層２２に電流の流れる方向（横方向）と並行にストライプ状に形成しておき、将来的にベース電極３４と接触するリセスエッチング部を形成する。なお、図３では説明の便宜上、開口部４０を図示している。 Next, in the second step, an isolation mesa is formed for element isolation using chlorine gas or the like. Thereafter, the p-type cap layer 24 and the undoped cap layer 22 are masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The opening 40 is formed in a stripe shape in parallel with the direction of current flow (lateral direction) in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future. . In FIG. 3, the opening 40 is shown for convenience of explanation.
　リセスエッチング部は少なくともｐ型キャップ層２４がエッチング除去されていれば良く、望ましくはアンドープキャップ層２２を除去し、さらに望ましくは少なくともバリア層２０の表面までエッチング除去されていることが求められる。また、仮にバリア層２０の表面よりもエッチングが進んでいてもキャップ層２２（２ＤＨＧ層）が露出されることによって、より低接触比抵抗が得られるため、望ましい。なお、バリア層２０を完全に除去してしまうと後に形成するベース電極３４とチャネル層１８（２ＤＥＧ層）とが接触することになるため、接触しない場合と比べると、良好な電気特性が得られなくなってしまう。よって、バリア層２０は完全に除去しないことが望ましい。 It is sufficient that at least the p-type cap layer 24 is removed by etching in the recess etching portion, preferably the undoped cap layer 22 is removed, and more preferably at least the surface of the barrier layer 20 is removed by etching. Further, even if the etching proceeds more than the surface of the barrier layer 20, it is desirable because the cap layer 22 (2DHG layer) is exposed to obtain a lower contact specific resistance. If the barrier layer 20 is completely removed, the base electrode 34 to be formed later and the channel layer 18 (2DEG layer) are in contact with each other. Therefore, better electrical characteristics can be obtained than in the case of no contact. It will disappear. Therefore, it is desirable not to completely remove the barrier layer 20.
　またストライプ状の開口部４０の開口幅Ｗは少なくとも０．１μｍ以上あればよく、また少なくとも１箇所でも開口部４０があれば、本発明の効果が発揮される。 The opening width W of the stripe-shaped opening 40 may be at least 0.1 μm or more, and if there is at least one opening 40, the effect of the present invention is exhibited.
　３）ソース電極３０及びドレイン電極３２を形成する第３工程について図４を参照して説明する。 3) A third step of forming the source electrode 30 and the drain electrode 32 will be described with reference to FIG.
　次に、第３工程では、塩素ガスなどを用いてゲート電極３６を形成する領域のみバリア層２０をエッチングにより除去する。その後、第３工程では、ゲート絶縁膜である誘電体膜２６としてＳｉＯ２を４０ｎｍ形成する。ＳｉＯ２の誘電体膜２６は、ＳｉＨ４ガスとＮ２Ｏガスを用いてＰＣＶＤなどにより形成する。手法はＰＥＣＶＤでもよいし、ＡＰＣＶＤでもよい。その後、第３工程では、レジストなどを用いてソース電極３０とドレイン電極３２を形成すべき領域を開口してバリア層２０の表面を表出させる。表出させた領域には、Ｔｉ、ＡｌとＳｉの合金膜、及びＷを順次蒸着してソース電極３０とドレイン電極３２をリフトオフ法などにより、形成する。 Next, in the third step, the barrier layer 20 is removed by etching only in the region where the gate electrode 36 is formed using chlorine gas or the like. Thereafter, in a third step, 40 nm of SiO 2 is formed as the dielectric film 26 which is a gate insulating film. The dielectric film 26 of SiO 2 is formed by PCVD or the like using SiH 4 gas and N 2 O gas. The method may be PECVD or APCVD. Thereafter, in a third step, a region where the source electrode 30 and the drain electrode 32 are to be formed is opened using a resist or the like to expose the surface of the barrier layer 20. In the exposed region, Ti, Al and Si alloy film, and W are sequentially deposited to form the source electrode 30 and the drain electrode 32 by a lift-off method or the like.
　４）ベース電極３４を形成する第４工程について図５を参照して説明する。 4) A fourth step of forming the base electrode 34 will be described with reference to FIG.
　次に、第４工程では、レジストなどによりパターニングを行って、ベース電極３４を形成すべき領域に、レジストなどを用いて開口を設けたパターニングをし、Ｎｉ／Ａｕ（６０ｎｍ／４０ｎｍ）を蒸着してベース電極３４を形成した。ベース電極３４は、さらに酸素雰囲気あるいは、酸素－窒素混合雰囲気において、５００℃～６００℃でアニールし、形成する。 Next, in the fourth step, patterning is performed by using a resist or the like, patterning is performed by providing an opening using a resist or the like in a region where the base electrode 34 is to be formed, and Ni / Au (60 nm / 40 nm) is deposited. Thus, the base electrode 34 was formed. The base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.
　ベース電極３４は、開口部４０を覆うように形成される。開口部４０の側面では、２ＤＨＧ層のエピタキシャル成長面と異なる面が露出されているため、このようにベース電極３４を形成することによりベース電極３４と２ＤＨＧ層とが電気的に接続される。 The base electrode 34 is formed so as to cover the opening 40. Since the surface different from the epitaxial growth surface of the 2DHG layer is exposed on the side surface of the opening 40, the base electrode 34 and the 2DHG layer are electrically connected by forming the base electrode 34 in this way.
　ここで、開口部４０（アンドープキャップ層２２及びｐ型キャップ層２４のリセスエッチング部）の形状と、ベース電極３４との関係について図６Ａ、図６Ｂ、及び図６Ｃを参照して説明する。図６Ａ、図６Ｂ、及び図６Ｃでは、開口部４０の側面４０Ａと、底面４０Ｂとの角度をθとして、説明する。なお、図６Ａ、図６Ｂ、及び図６Ｃでは、開口部４０を覆うように形成されたベース電極３４上に角度θを図示しているが、略同様であるため問題は生じない。 Here, the relationship between the shape of the opening 40 (the recess etching portion of the undoped cap layer 22 and the p-type cap layer 24) and the base electrode 34 will be described with reference to FIGS. 6A, 6B, and 6C. 6A, 6B, and 6C, the angle between the side surface 40A of the opening 40 and the bottom surface 40B will be described as θ. 6A, 6B, and 6C, the angle θ is illustrated on the base electrode 34 formed so as to cover the opening 40. However, since the angle θ is substantially the same, no problem occurs.
　図６Ａに示すように、角度θが９０°程度の場合は、ベース電極３４の密着性が良好になる。一方、図６Ｂに示すように、角度θが９０°よりも小さい場合は、側面４０Ａでは、形成されるベース電極３４が他に比べて薄くなることがある。そのため、角度θが９０°よりも大幅に小さい場合等、側面４０Ａでは、ベース電極３４が途切れてしまう懸念が生じる。また、図６Ｃに示すように、角度θが９０°よりも大きい場合、ベース電極３４の密着性は良好になるが、２ＤＨＧが薄まる懸念が生じる。このような観点から、開口部４０の角度θは、４５°以上、かつ１７５°以下が好ましく、より好ましくは、９０°以上、かつ１５０°以下である。 As shown in FIG. 6A, when the angle θ is about 90 °, the adhesion of the base electrode 34 is improved. On the other hand, as shown in FIG. 6B, when the angle θ is smaller than 90 °, the base electrode 34 formed on the side surface 40A may be thinner than others. Therefore, there is a concern that the base electrode 34 is interrupted on the side surface 40A, such as when the angle θ is significantly smaller than 90 °. Further, as shown in FIG. 6C, when the angle θ is larger than 90 °, the adhesion of the base electrode 34 is improved, but there is a concern that 2DHG may be thinned. From such a viewpoint, the angle θ of the opening 40 is preferably 45 ° or more and 175 ° or less, and more preferably 90 ° or more and 150 ° or less.
　５）ゲート電極３６を形成する第５工程について説明する。 5) A fifth step for forming the gate electrode 36 will be described.
　次に、第５工程では、レジストなどによりパターニングを行って、ゲート電極３６を形成すべき領域に、レジストなどを用いて開口部を設けたパターニングをし、ＮｉあるいはＴｉなどを蒸着してゲート電極３６を形成した。なお、ゲート電極３６はポリシリコンなどを用いてもよい。その結果、図１に示した電界効果トランジスタ１０が製造される。 Next, in the fifth step, patterning is performed using a resist or the like, patterning is performed in which an opening is formed using a resist or the like in a region where the gate electrode 36 is to be formed, and Ni or Ti or the like is evaporated to form a gate electrode. 36 was formed. The gate electrode 36 may be made of polysilicon or the like. As a result, the field effect transistor 10 shown in FIG. 1 is manufactured.
　［第２の実施例］
　図７には、本実施例の概略構成の一例を示す概略構成図を示す。図７には、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。なお、第２の実施例は、第１の実施例と略同様の構成、及び工程を有するため、略同一部分には同一符号を付し、詳細な説明を省略する。 [Second Embodiment]
In FIG. 7, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 7 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the second embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
　本実施例の電界効果トランジスタ１０と、第１の実施例の電界効果トランジスタ１０とでは、図７の平面図（１）に示すように、ｐ型キャップ層２４及びアンドープキャップ層２２の形状（上面からみた形状）が異なっている。 In the field effect transistor 10 of this example and the field effect transistor 10 of the first example, as shown in the plan view (1) of FIG. 7, the shapes (upper surface) of the p-type cap layer 24 and the undoped cap layer 22 are shown. The shape seen from) is different.
　本実施例の電界効果トランジスタ１０では、アンドープキャップ層２２及びｐ型キャップ層２４がゲート電極３６側からドレイン電極３２側に向けて、バリア層２０と接する面積が小さくなるように形成されている。ｐ型キャップ層２４を残す部分（面積が小さくなった先端部）は、ドレイン電極３２と０．１μｍ以上隔絶されていればよく、望ましくはゲート電極３６－ドレイン電極３２間の１／３以上の間隔が空いていることが望ましい。例えば、ｐ型キャップ層２４を残す部分は、ゲート電極３６－ドレイン電極３２間隔が１２μｍであれば、少なくとも４μｍ程度であればよい。 In the field effect transistor 10 of this example, the undoped cap layer 22 and the p-type cap layer 24 are formed so that the area in contact with the barrier layer 20 decreases from the gate electrode 36 side to the drain electrode 32 side. The portion where the p-type cap layer 24 is left (the tip portion where the area is reduced) may be separated from the drain electrode 32 by 0.1 μm or more, and preferably 1/3 or more between the gate electrode 36 and the drain electrode 32. It is desirable that there is an interval. For example, the portion where the p-type cap layer 24 is left may be at least about 4 μm if the distance between the gate electrode 36 and the drain electrode 32 is 12 μm.
　次に、本実施例の電界効果トランジスタ１０の製造方法の一例について説明する。 Next, an example of a method for manufacturing the field effect transistor 10 of this embodiment will be described.
　まず、本実施例の第１工程では、第１の実施例の第１工程の要領でエピ基板（基板１２、バッファ層１４、高抵抗層１６、チャネル層１８、バリア層２０、キャップ層２２、及びキャップ層２４が積層された基板）を準備する。 First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
　その後、本実施例の第２工程では、準備したエピ基板に、塩素ガスなどを用いて素子分離のためのアイソレーションメサ形成を実施する。その後、第２工程では、ベース電極３４部分をレジストなどでマスクし、バリア層２０の表面が露出するまで塩素ガスなどを用いて、ドライエッチングを行う。このとき、フッ素系のガスを混合する、あるいは酸素系のガスを混合するなどして、選択的にエッチングを行うことで、良好な再現性・歩留まりの素子形成が実現できる。その際に、第２工程では、ベース電極３４を形成するための層として島状に残した部分の内側にゲート電極３６からドレイン電極３２側に向かって、エッチングする面積が相対的に大きくなるようなパターン（上記参照）にしておき、将来的にベース電極３４と接触するリセスエッチング部（開口部４０）を形成する。 Thereafter, in the second step of this embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. At that time, in the second step, the area to be etched is relatively increased from the gate electrode 36 toward the drain electrode 32 inside the portion left as an island as a layer for forming the base electrode 34. Then, a recess etching portion (opening 40) that comes into contact with the base electrode 34 is formed in the future.
　ここで、ｐ型キャップ層２４を残す部分は、ドレイン電極３２と０．１μｍ以上隔絶されていればよく、望ましくはゲート電極３６－ドレイン電極３２間の１／３以上の間隔が空いていることが望ましい。例えば、ｐ型キャップ層２４を残す部分は、ゲート電極３６－ドレイン電極３２間隔が１２μｍであれば、少なくとも４μｍ程度であればよい。 Here, the portion where the p-type cap layer 24 is left only needs to be separated from the drain electrode 32 by 0.1 μm or more, and preferably a space of 1/3 or more between the gate electrode 36 and the drain electrode 32 is left. Is desirable. For example, the portion where the p-type cap layer 24 is left may be at least about 4 μm if the distance between the gate electrode 36 and the drain electrode 32 is 12 μm.
　その後、第１の実施例の第３工程～第５工程までの要領で、それぞれゲートリセスエッチング、ソース電極３０、ドレイン電極３２、ベース電極３４、及びゲート電極３６を形成することにより、図７に示した電界効果トランジスタ１０が製造される。 Thereafter, in the manner from the third step to the fifth step of the first embodiment, the gate recess etching, the source electrode 30, the drain electrode 32, the base electrode 34, and the gate electrode 36 are formed, respectively. The illustrated field effect transistor 10 is manufactured.
　本実施例の電界効果トランジスタ１０では、ゲート電極３６からドレイン電極３２側に向かって、徐々にｐ型キャップ層２４及びアンドープキャップ層２２の面積を低減させることで、平均的な二次元ホールガスの濃度を少しずつ低減させられる。このことにより、本実施例の電界効果トランジスタ１０では、ｐ型キャップ層２４及びアンドープキャップ層２２のドレイン電極３２側端部への電界集中を抑えることができるため、以下の第３の実施例に比べて、よりリーク電流や耐圧を改善できる。また、本実施例の電界効果トランジスタ１０では、電流コラプスについても効果的に抑制が可能である。 In the field effect transistor 10 of the present embodiment, the area of the p-type cap layer 24 and the undoped cap layer 22 is gradually reduced from the gate electrode 36 toward the drain electrode 32 side, so that the average two-dimensional hole gas is reduced. The concentration can be reduced little by little. As a result, in the field effect transistor 10 of this embodiment, the electric field concentration at the end of the p-type cap layer 24 and the undoped cap layer 22 on the drain electrode 32 side can be suppressed. Compared with this, leakage current and breakdown voltage can be improved. Further, in the field effect transistor 10 of the present embodiment, the current collapse can be effectively suppressed.
　［第３の実施例］
　図８には、本実施例の概略構成の一例を示す概略構成図を示す。図８には、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。なお、第３の実施例は、第１の実施例と略同様の構成、及び工程を有するため、略同一部分には同一符号を付し、詳細な説明を省略する。 [Third embodiment]
In FIG. 8, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 8 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the third embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
　本実施例の電界効果トランジスタ１０は、第１の実施例の電界効果トランジスタ１０と異なり、図８の断面図（２）に示すように、ベース電極３４とゲート電極３６とが同電位になるように、すなわち短絡するように形成されている。 Unlike the field effect transistor 10 of the first embodiment, the field effect transistor 10 of the present embodiment is such that the base electrode 34 and the gate electrode 36 have the same potential as shown in the sectional view (2) of FIG. That is, it is formed so as to be short-circuited.
　このようにベース電極３４とゲート電極３６とを短絡させることで、オン特性としては、第１の実施例と同様のオン抵抗が得られる。また、ドレイン電流については、ｐ型層を通してホール注入されることによって、電導度変調が起きるため、第１の実施例に比べて２０％程度大きなドレイン電流が得られる。また、オフ特性としては、第１の実施例と同じく電界緩和効果が得られるため、同程度の耐圧とリーク電流を得ることができる。作製上は、ベース電極３４とゲート電極３６とを短絡させられれば、一つの電極として振る舞うため、電気的な制御はソース、ゲート、及びドレインの３端子で行える。本実施例の電界効果トランジスタ１０では、ベース電極という端子を取る必要がなくなるため、素子サイズをよりコンパクトにできる。 By short-circuiting the base electrode 34 and the gate electrode 36 in this way, the on-resistance similar to that of the first embodiment can be obtained as the on-characteristic. As for the drain current, conductivity modulation occurs when holes are injected through the p-type layer, so that a drain current that is about 20% larger than that of the first embodiment can be obtained. Further, as the off characteristics, since the electric field relaxation effect can be obtained as in the first embodiment, the same breakdown voltage and leakage current can be obtained. In manufacturing, if the base electrode 34 and the gate electrode 36 are short-circuited, they behave as one electrode, so that electrical control can be performed with three terminals of a source, a gate, and a drain. In the field effect transistor 10 of the present embodiment, it is not necessary to take a terminal called a base electrode, so that the element size can be made more compact.
　本実施例の電界効果トランジスタ１０の製造方法の一例について説明する。 An example of a method for manufacturing the field effect transistor 10 of this embodiment will be described.
　まず、本実施例の第１工程では、第１の実施例の第１工程の要領でエピ基板（基板１２、バッファ層１４、高抵抗層１６、チャネル層１８、バリア層２０、キャップ層２２、及びキャップ層２４が積層された基板）を準備する。 First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
　その後、本実施例の第２工程は、準備したエピ基板に、塩素ガスなどを用いて素子分離のためのアイソレーションメサ形成を実施する。その後、第２工程では、ベース電極３４部分をレジストなどでマスクし、バリア層２０の表面が露出するまで塩素ガスなどを用いて、ドライエッチングを行う。このとき、フッ素系のガスを混合する、あるいは酸素系のガスを混合するなどして、選択的にエッチングを行うことで、良好な再現性・歩留まりの素子形成が実現できる。第２工程では、その際に、ベース電極３４を形成するための層として島状に残した部分の内側に開口部４０を同時に形成する。開口部４０は、ｐ型キャップ層２４およびアンドープキャップ層２２に電流の流れる方向と並行にストライプ状に形成しておき、将来的にベース電極３４と接触するリセスエッチング部を形成する。 Thereafter, in the second step of the present embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.
　その後、第１の実施例の第３工程、及び第４工程までの要領で、それぞれゲートリセスエッチング、ソース電極３０、ドレイン電極３２、及びベース電極３４を形成する。 Thereafter, the gate recess etching, the source electrode 30, the drain electrode 32, and the base electrode 34 are formed in the manner up to the third step and the fourth step of the first embodiment, respectively.
　その後、本実施例の第５工程では、ベース電極３４をまたぐようにゲート電極３６をパターニングによって形成する。これにより、図８に示した電界効果トランジスタ１０が製造される。 Thereafter, in the fifth step of this embodiment, the gate electrode 36 is formed by patterning so as to straddle the base electrode 34. Thereby, the field effect transistor 10 shown in FIG. 8 is manufactured.
　［第４の実施例］
　図９には、本実施例の概略構成の一例を示す概略構成図を示す。図９には、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。なお、第４の実施例は、第１の実施例と略同様の構成、及び工程を有するため、略同一部分には同一符号を付し、詳細な説明を省略する。 [Fourth embodiment]
In FIG. 9, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 9 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the fourth embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
　本実施例の窒化物系化合物半導体素子は、第１の実施例のソース電極３０、ドレイン電極３２、及びゲート電極３６に替わり、カソード電極６２及びアノード電極６４を備えたダイオード６０として構成されている。 The nitride compound semiconductor device of this embodiment is configured as a diode 60 having a cathode electrode 62 and an anode electrode 64 instead of the source electrode 30, the drain electrode 32, and the gate electrode 36 of the first embodiment. .
　本実施例のダイオード６０の製造方法の一例について説明する。 An example of a manufacturing method of the diode 60 of this embodiment will be described.
　まず、本実施例の第１工程では、第１の実施例の第１工程の要領でエピ基板（基板１２、バッファ層１４、高抵抗層１６、チャネル層１８、バリア層２０、キャップ層２２、及びキャップ層２４が積層された基板）を準備する。 First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
　その後、本実施例の第２工程は、準備したエピ基板に、塩素ガスなどを用いて素子分離のためのアイソレーションメサ形成を実施する。その後、第２工程では、ベース電極３４部分をレジストなどでマスクし、バリア層２０の表面が露出するまで塩素ガスなどを用いて、ドライエッチングを行う。このとき、フッ素系のガスを混合する、あるいは酸素系のガスを混合するなどして、選択的にエッチングを行うことで、良好な再現性・歩留まりの素子形成が実現できる。第２工程では、その際に、ベース電極３４を形成するための層として島状に残した部分の内側に開口部４０を同時に形成する。開口部４０は、ｐ型キャップ層２４およびアンドープキャップ層２２に電流の流れる方向と並行にストライプ状に形成しておき、将来的にベース電極３４と接触するリセスエッチング部を形成する。 Thereafter, in the second step of the present embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.
　その後、本実施例の第３工程では、レジストなどを用いてカソード電極６２を形成すべき領域を開口してバリア層２０の表面を表出させる。表出させた領域には、Ｔｉ、ＡｌとＳｉの合金膜、及びＷを順次蒸着してカソード電極６２をリフトオフ法などにより、形成する。 Thereafter, in the third step of this embodiment, a region where the cathode electrode 62 is to be formed is opened using a resist or the like to expose the surface of the barrier layer 20. In the exposed region, Ti, an alloy film of Al and Si, and W are sequentially deposited, and the cathode electrode 62 is formed by a lift-off method or the like.
　次に、ベース電極３４を形成するための本実施例の第４工程では、レジストなどによりパターニングを行って、ベース電極３４を形成すべき領域に、レジストなどを用いて開口部を設けたパターニングをし、Ｎｉ／Ａｕ（６０ｎｍ／４０ｎｍ）を蒸着してベース電極３４を形成する。ベース電極３４は、さらに酸素雰囲気あるいは、酸素－窒素混合雰囲気で５００℃～６００℃でアニールし、形成する。 Next, in the fourth step of the present embodiment for forming the base electrode 34, patterning is performed using a resist or the like, and patterning is performed in which an opening is formed using a resist or the like in a region where the base electrode 34 is to be formed. Then, Ni / Au (60 nm / 40 nm) is deposited to form the base electrode 34. The base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.
　その後、本実施例の第５工程では、レジストなどによりパターニングを行って、アノード電極６４を形成すべき領域に、レジストなどを用いて開口部を設けたパターニングをし、ＮｉあるいはＰｄなどを蒸着してアノード電極Ａを形成する。なお、アノード電極６４はポリシリコンなどを用いてもよい。その結果、図９に示したダイオードが製造される。 Thereafter, in the fifth step of the present embodiment, patterning is performed using a resist or the like, patterning is performed by providing an opening using a resist or the like in a region where the anode electrode 64 is to be formed, and Ni or Pd is deposited. Thus, the anode electrode A is formed. The anode electrode 64 may be made of polysilicon or the like. As a result, the diode shown in FIG. 9 is manufactured.
　［第５の実施例］
　図１０には、本実施例の概略構成の一例を示す概略構成図を示す。図１０には、上面から見た概略の平面図（１）、平面図のＢ－Ｂ線断面図（２）、及び平面図のＣ－Ｃ線断面図（３）を示す。なお、第５の実施例は、第１の実施例と略同様の構成、及び工程を有するため、略同一部分には同一符号を付し、詳細な説明を省略する。 [Fifth embodiment]
In FIG. 10, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 10 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the fifth embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.
　本実施例では、第１の実施例の電界効果トランジスタ１０と異なり、本発明の窒化物系化合物半導体素子をノーマリオン型の電界効果トランジスタとして構成した場合について説明する。 In this embodiment, unlike the field effect transistor 10 of the first embodiment, a case where the nitride compound semiconductor element of the present invention is configured as a normally-on type field effect transistor will be described.
　本実施例の電界効果トランジスタ７０の製造方法の一例について説明する。 An example of a method for manufacturing the field effect transistor 70 of this embodiment will be described.
　まず、本実施例の第１工程では、第１の実施例の第１工程の要領でエピ基板（基板１２、バッファ層１４、高抵抗層１６、チャネル層１８、バリア層２０、キャップ層２２、及びキャップ層２４が積層された基板）を準備する。 First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).
　その後、本実施例の第２工程は、準備したエピ基板に、塩素ガスなどを用いて素子分離のためのアイソレーションメサ形成を実施する。その後、第２工程では、ベース電極３４を形成するための領域をレジストなどでマスクし、バリア層２０の表面が露出するまで塩素ガスなどを用いて、ドライエッチングを行う。このとき、フッ素系のガスを混合する、あるいは酸素系のガスを混合するなどして、選択的にエッチングを行うことで、良好な再現性・歩留まりの素子形成が実現できる。第２工程では、その際に、ベース電極３４を形成するための層として島状に残した部分の内側に開口部４０を同時に形成する。開口部４０は、ｐ型キャップ層２４およびアンドープキャップ層２２に電流の流れる方向と並行にストライプ状に形成しておき、将来的にベース電極３４と接触するリセスエッチング部を形成する。 Thereafter, in the second step of the present embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, a region for forming the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.
　次に、本実施例の第３工程では、第１の実施例の第３工程の要領で、ソース電極３０及びドレイン電極３２を形成する。なお、本実施例の電界効果トランジスタ７０は、ノーマリオンであるため、第１の実施例と異なり、ゲートリセス部は形成しない。 Next, in the third step of the present embodiment, the source electrode 30 and the drain electrode 32 are formed in the same manner as the third step of the first embodiment. Since the field effect transistor 70 of this embodiment is normally on, a gate recess is not formed unlike the first embodiment.
　次に、ベース電極３４を形成する本実施例の第４工程では、レジストなどによりパターニングを行って、ベース電極３４を形成すべき箇所に、レジストなどを用いて開口部を設けたパターニングをし、Ｎｉ／Ａｕ（６０ｎｍ／４０ｎｍ）を蒸着してベース電極３４を形成する。ベース電極３４は、さらに酸素雰囲気あるいは、酸素－窒素混合雰囲気において、５００℃～６００℃でアニールし、形成する。 Next, in the fourth step of the present embodiment for forming the base electrode 34, patterning is performed using a resist or the like, and patterning is performed by providing an opening using a resist or the like at a position where the base electrode 34 is to be formed. Ni / Au (60 nm / 40 nm) is deposited to form the base electrode 34. The base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.
　さらに、第３工程では、レジストなどによりパターニングを行って、ゲート電極３６を形成すべき領域に、レジストなどを用いて開口部を設けたパターニングをし、ＮｉあるいはＴｉなどを蒸着してゲート電極３６を形成する。なお、ゲート電極３６はポリシリコンなどを用いてもよい。また、ゲート電極３６の形成される領域の一部の誘電体膜２６を除去して、ショットキー接合するゲート部も形成することができる。その結果、図１０に示した電界効果トランジスタ７０が製造される。 Further, in the third step, patterning is performed using a resist or the like, patterning is performed in which an opening is formed using a resist or the like in a region where the gate electrode 36 is to be formed, and Ni or Ti or the like is evaporated to form the gate electrode 36. Form. The gate electrode 36 may be made of polysilicon or the like. In addition, a part of the dielectric film 26 in a region where the gate electrode 36 is formed can be removed to form a gate portion for Schottky junction. As a result, the field effect transistor 70 shown in FIG. 10 is manufactured.
　以上、上述の各実施例で説明したように、本発明による窒化物系化合物半導体素子では、２ＤＨＧ層を有する、アンドープキャップ層２２及びｐ型キャップ層２４にエッチングによって部分的にリセス構造（開口部４０）をつくりこみ、２ＤＨＧ層のエピタキシャル成長面と異なる面が露出された開口部４０を覆うようにベース電極３４が形成されている。そのため、本発明による窒化物系化合物半導体素子では、ベース電極３４とオーミックコンタクトがとりやすくなる。本発明による窒化物系化合物半導体素子では、当該構成により、２ＤＨＧのホールを効果的に排出できるようになる。また、本発明による窒化物系化合物半導体素子では、チャネル層１８をアンドープ層とすることで、順方向特性や逆方向特性を維持しながら電流コラプスを抑制し、短絡耐量を維持できる。 As described above, in the nitride-based compound semiconductor device according to the present invention as described in the above embodiments, the undoped cap layer 22 and the p-type cap layer 24 having the 2DHG layer are partially recessed by etching. The base electrode 34 is formed so as to cover the opening 40 where the surface different from the epitaxial growth surface of the 2DHG layer is exposed. Therefore, the nitride-based compound semiconductor device according to the present invention can easily make ohmic contact with the base electrode 34. In the nitride-based compound semiconductor device according to the present invention, 2DHG holes can be effectively discharged by this configuration. In the nitride-based compound semiconductor device according to the present invention, the channel layer 18 is an undoped layer, so that current collapse can be suppressed and the short-circuit tolerance can be maintained while maintaining forward characteristics and reverse characteristics.
　例えば、図１１に示した従来の窒化物系化合物半導体素子ではオン抵抗が５ｍΩｃｍ２の素子において、電流コラプスとしてオン抵抗の増大率が６００Ｖで１．５倍以上に悪化してしまったものが、本実施例の電界効果トランジスタ１０では、１．１倍以下まで改善することが確認できた。また、ホールの排出を改善できたことで、負荷短絡耐量も向上し、図１１に示した従来の窒化物系化合物半導体素子では、ほとんど耐量がなかったものが、本実施例の電界効果トランジスタ１０では、１００Ａ／ｃｍ２、６００Ｖでの耐量が７００ｍＪまで改善できた。 For example, in the conventional nitride-based compound semiconductor device shown in FIG. 11, in the device having an on-resistance of 5 mΩcm 2 , the increase rate of the on-resistance as a current collapse deteriorated to 1.5 times or more at 600 V. It was confirmed that the field effect transistor 10 of this example was improved to 1.1 times or less. Further, since the discharge of holes can be improved, the load short-circuit withstand capability is also improved, and the conventional nitride-based compound semiconductor device shown in FIG. Then, the withstand voltage at 100 A / cm 2 and 600 V was improved to 700 mJ.
　また、ノーマリオフ型の素子としては、ハイブリッドＭＯＳＨＦＥＴ構造が望ましい。この構造では、ゲート電極３６のリセスエッチングによってゲート電極３６下の２ＤＥＧキャリアを除去することができる。このエッチングおよび設計条件は２ＤＨＧの設計パラメータに影響を与えずに独立に設計することが出来るという効果がある。もちろん、バリア層２０を完全除去せずに、数ｎｍ残してゲート絶縁膜である誘電体膜２６を形成する方式にも適用できることはいうまでもないことである。 Also, as a normally-off type element, a hybrid MOSHFET structure is desirable. In this structure, 2DEG carriers under the gate electrode 36 can be removed by recess etching of the gate electrode 36. This etching and design conditions have the effect that they can be designed independently without affecting the design parameters of 2DHG. Of course, it is needless to say that the present invention can also be applied to a method of forming the dielectric film 26, which is a gate insulating film, without removing the barrier layer 20 and leaving several nm.
　そのため、本発明による窒化物系化合物半導体素子は、高耐圧のインバータやコンバータなどへの応用が可能になる。以上のことより、高耐圧で、かつ高い信頼性をもつＧａＮ系電界効果トランジスタの実現が可能である。 Therefore, the nitride-based compound semiconductor device according to the present invention can be applied to a high voltage inverter or converter. From the above, it is possible to realize a GaN field effect transistor having a high breakdown voltage and high reliability.
　なお、上記各実施例で示した開口部４０の形状等は具体的一例であり、これに限定されるものではない。上述したように、本発明による窒化物系化合物半導体素子では、少なくとも１箇所でも開口部を備えていれば、備えていない場合に比べて、オーミックコンタクトがとりやすくなるため、ホールを効果的に排出することができるという効果が得られる。例えば、開口部４０は、ストライプ状ではなく、円形状等の他の形状であってもよい。また第２の実施例では、ゲート電極３６側からドレイン電極３２側に向けてアンドープキャップ層２２およびｐ型キャップ層２４の面積が小さくなるように開口部４０を形成しているが、これに限らない。例えば、開口部４０は、ドレイン側に向けて当該面積が同じ（アルファベットの「Ｅ」形状）ように形成してもよい。また、アンドープキャップ層２２及びｐ型キャップ層２４は、複数、間隔（開口部４０に相当）を開けてストライプ状に形成してもよい。本発明の主旨を逸脱しない限り、このように、種々の変形が可能であることはいうまでもない。 It should be noted that the shape of the opening 40 shown in each of the above embodiments is a specific example, and is not limited to this. As described above, in the nitride-based compound semiconductor device according to the present invention, if at least one opening is provided, ohmic contact can be easily obtained compared to the case where no opening is provided. The effect that it can do is acquired. For example, the opening 40 may have other shapes such as a circular shape instead of the stripe shape. In the second embodiment, the opening 40 is formed so that the areas of the undoped cap layer 22 and the p-type cap layer 24 are reduced from the gate electrode 36 side toward the drain electrode 32 side. Absent. For example, the opening 40 may be formed to have the same area (alphabet “E” shape) toward the drain side. Further, the undoped cap layer 22 and the p-type cap layer 24 may be formed in stripes with a plurality of intervals (corresponding to the opening 40). Needless to say, various modifications can be made without departing from the gist of the present invention.
　なお、上記各実施例では、基板１２をシリコン基板とした場合について例示したが、シリコン基板以外のＳｉＣ基板、サファイア基板、ＧａＮ基板、ＭｇＯ基板、及びＺｎＯ基板上など、ＧａＮが結晶成長可能なあらゆる基板上の素子についても成り立つことは言うまでも無い。 In each of the above embodiments, the case where the substrate 12 is a silicon substrate has been exemplified. However, any substrate capable of crystal growth of GaN such as a SiC substrate other than a silicon substrate, a sapphire substrate, a GaN substrate, an MgO substrate, and a ZnO substrate can be used. Needless to say, the elements on the substrate also hold true.
　また、上述の各実施の形態で説明した窒化物系化合物半導体素子の構成、及び製造方法などは一例であり、本発明の主旨を逸脱しない範囲内において状況に応じて変更可能であることはいうまでもない。 In addition, the configuration and manufacturing method of the nitride-based compound semiconductor device described in each of the above-described embodiments are examples, and it can be changed according to the situation without departing from the gist of the present invention. Not too long.
　日本出願２０１２－０５４９８５の開示は、その全体が参照により本明細書に取り込まれる。 The entire disclosure of the Japanese application 2012-054985 is incorporated herein by reference.
　本明細書に記載された全ての文献、特許出願、及び技術規格は、個々の文献、特許出願、及び技術規格が参照により取り込まれることが具体的かつ個々に記された場合と同程度に、本明細書中に参照により取り込まれる。 All documents, patent applications, and technical standards mentioned in this specification are to the same extent as if each individual document, patent application, and technical standard were specifically and individually stated to be incorporated by reference, Incorporated herein by reference.

Claims (15)

  1. 　電子走行層と、電子供給層と、該電子走行層と該電子供給層との界面に形成される二次元電子ガス層を有する第１窒化物系半導体層と、
    　前記第１窒化物系半導体層上に形成されており、分極接合の界面に形成される二次元ホールガス層を有する第２窒化物系半導体層と、
    　前記第２窒化物系半導体層に接して形成されており、少なくとも１箇所のエピタキシャル成長面と異なる方位をもつ面が露出された前記二次元ホールガス層に電気的に接触しているベース電極と、
    　を備えた窒化物系化合物半導体素子。     A first nitride-based semiconductor layer having an electron transit layer, an electron supply layer, and a two-dimensional electron gas layer formed at an interface between the electron transit layer and the electron supply layer;
    A second nitride based semiconductor layer formed on the first nitride based semiconductor layer and having a two-dimensional hole gas layer formed at the interface of the polarization junction;
    A base electrode formed in contact with the second nitride-based semiconductor layer and in electrical contact with the two-dimensional hole gas layer in which a surface having an orientation different from that of at least one epitaxial growth surface is exposed;
    A nitride compound semiconductor device comprising:
  2. 　前記第２窒化物系半導体層は、前記二次元ホールガス層に接触する開口部を有している、請求項１に記載の窒化物系化合物半導体素子。 The nitride-based compound semiconductor element according to claim 1, wherein the second nitride-based semiconductor layer has an opening that contacts the two-dimensional hole gas layer.
  3. 　前記開口部は、前記第１窒化物系半導体層の前記電子供給層の表面に至る、請求項２に記載の窒化物系化合物半導体素子。 The nitride-based compound semiconductor device according to claim 2, wherein the opening reaches a surface of the electron supply layer of the first nitride-based semiconductor layer.
  4. 　前記開口部の側面と、底面とのなす角度が４５°以上、１７５°以下であり、前記ベース電極が前記開口部を覆うように形成されている。請求項２または請求項３に記載の窒化物系化合物半導体素子。 The angle formed between the side surface and the bottom surface of the opening is 45 ° or more and 175 ° or less, and the base electrode is formed to cover the opening. The nitride-based compound semiconductor device according to claim 2 or 3.
  5. 　前記開口部の側面と、底面とのなす角度が９０°以上、１５０°以下であり、前記ベース電極が前記開口部を覆うように形成されている。請求項２または請求項３に記載の窒化物系化合物半導体素子。 The angle formed between the side surface and the bottom surface of the opening is 90 ° or more and 150 ° or less, and the base electrode is formed to cover the opening. The nitride-based compound semiconductor device according to claim 2 or 3.
  6. 　ゲート電極と、
    　ドレイン電極と、
    　ソース電極と、
    　前記ゲート電極と前記ドレイン電極との間の領域に前記第２窒化物系半導体層を含む電界緩和層と、
    　を備え、ノーマリオフ動作をする電界効果トランジスタである、請求項１から請求項５のいずれか１項に記載の窒化物系化合物半導体素子。     A gate electrode;
    A drain electrode;
    A source electrode;
    An electric field relaxation layer including the second nitride-based semiconductor layer in a region between the gate electrode and the drain electrode;
    The nitride-based compound semiconductor device according to claim 1, wherein the nitride-based compound semiconductor device is a field effect transistor that normally operates.
  7. 　ゲート電極と、
    　ドレイン電極と、
    　ソース電極と、
    　前記ゲート電極と前記ドレイン電極との間の領域に前記第２窒化物系半導体層を含む電界緩和層と、
    　を備え、ノーマリオン動作をする電界効果トランジスタである、請求項１から請求項５のいずれか１項に記載の窒化物系化合物半導体素子。     A gate electrode;
    A drain electrode;
    A source electrode;
    An electric field relaxation layer including the second nitride-based semiconductor layer in a region between the gate electrode and the drain electrode;
    The nitride-based compound semiconductor device according to claim 1, wherein the nitride-based compound semiconductor device is a field effect transistor that normally operates.
  8. 　前記電界緩和層における前記二次元ホールガス層の平均濃度が、前記ゲート電極から前記ドレイン電極に向かって減少していく、請求項６または請求項７に記載の窒化物系化合物半導体素子。 The nitride compound semiconductor element according to claim 6 or 7, wherein an average concentration of the two-dimensional hole gas layer in the electric field relaxation layer decreases from the gate electrode toward the drain electrode.
  9. 　前記電界緩和層が、ｐ型キャリアを有する窒化物系半導体層を有しており、前記ゲート電極から前記ドレイン電極に向かって前記第１窒化物系半導体層に接する面積を低減させていくよう配置された、請求項８に記載の窒化物系化合物半導体素子。 The electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and is arranged so as to reduce an area in contact with the first nitride-based semiconductor layer from the gate electrode toward the drain electrode. The nitride compound semiconductor device according to claim 8.
  10. 　アノード電極と、
    　カソード電極と、
    　前記アノード電極と前記カソード電極との間の領域に前記第２窒化物系半導体層を含む電界緩和層と、
    　を備えたダイオードである、請求項１から請求項５のいずれか１項に記載の窒化物系化合物半導体素子。     An anode electrode;
    A cathode electrode;
    An electric field relaxation layer including the second nitride-based semiconductor layer in a region between the anode electrode and the cathode electrode;
    The nitride-based compound semiconductor device according to claim 1, wherein the nitride-based compound semiconductor device is a diode comprising:
  11. 　前記電界緩和層が、ｐ型キャリアを有する窒化物系半導体層を有しており、前記アノード電極から前記カソード電極に向かって前記第１窒化物系半導体層に接する面積を低減させていくよう配置された、請求項１０に記載の窒化物系化合物半導体素子。 The electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and is arranged so as to reduce an area in contact with the first nitride-based semiconductor layer from the anode electrode toward the cathode electrode. The nitride compound semiconductor device according to claim 10.
  12. 　前記ソース電極または前記ゲート電極と、前記ベース電極と、が同一の電位をもつ、請求項６から請求項９のいずれか１項に記載の窒化物系化合物半導体素子。 The nitride compound semiconductor element according to any one of claims 6 to 9, wherein the source electrode or the gate electrode and the base electrode have the same potential.
  13. 　前記アノード電極と、前記ベース電極と、が同一の電位をもつ、請求項１０または請求項１１に記載の窒化物系化合物半導体素子。 The nitride compound semiconductor device according to claim 10 or 11, wherein the anode electrode and the base electrode have the same potential.
  14. 　前記ゲート電極が、前記ベース電極の少なくとも一部を覆うように形成されている、請求項１２に記載の窒化物系化合物半導体素子。 The nitride-based compound semiconductor device according to claim 12, wherein the gate electrode is formed so as to cover at least a part of the base electrode.
  15. 　前記アノード電極が、前記ベース電極の少なくとも一部を覆うように形成されている、請求項１３に記載の窒化物系化合物半導体素子。 The nitride-based compound semiconductor element according to claim 13, wherein the anode electrode is formed so as to cover at least a part of the base electrode.
PCT/JP2013/056846 2012-03-12 2013-03-12 Nitride compound semiconductor element WO2013137267A1 (en)

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