JP2023133798A - nitride semiconductor device - Google Patents

Abstract

To provide a nitride semiconductor device capable of improving the off characteristics.SOLUTION: A nitride semiconductor device 1 includes: a substrate 10; a drift layer 12; a first base layer 14; a second base layer 16; a gate opening 20; a semiconductor multilayer film 21 a portion of which is placed along the inner surface of the gate opening 20, the other part of which is placed above the second base layer 16 and which has a channel area; a threshold adjustment layer 28; a gate electrode 34; a source electrode 32; a drain electrode 36; a groove portion 40 provided at the terminal end portion 3 that penetrates the first base layer 14 and reaches at least the drift layer 12; an interlayer insulating film 42 placed above the gate electrode 34; and source wiring 44 that penetrates the interlayer insulating film 42 and reaches the source electrode 32. The end of the interlayer insulating film 42 coincides with the end of the groove 40 in plan view, and in a range inside the end of the groove 40, is located outside the outermost part of the source electrode 32.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to nitride semiconductor devices.

Nitride semiconductors, represented by GaN (gallium nitride), are wide-gap semiconductors with a large band gap, a large dielectric breakdown electric field, and a saturated electron drift velocity that is higher than that of compound semiconductors such as GaAs (gallium arsenide) or Si (silicon). ) It has the advantage of being larger than semiconductors. For example, the band gaps of GaN and AlN (aluminum nitride) are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development are being carried out on power transistors using nitride semiconductors, which are advantageous for increasing output power and increasing voltage resistance.

For example, Patent Document 1 discloses a vertical FET (Field Effect Transistor) including a GaN-based semiconductor layer.

Patent No. 6107430

However, there is room for improvement in the off-state characteristics of the conventional semiconductor device.

The present disclosure provides a nitride semiconductor device with improved off-characteristics.

A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, and a first semiconductor layer disposed above the first semiconductor layer. a second semiconductor layer of a second conductivity type; a third semiconductor layer disposed above the second semiconductor layer; a first opening reaching the first semiconductor layer, a portion of which is disposed along the inner surface of the first opening, and another portion of which is disposed above the third semiconductor layer; a semiconductor multilayer film having a channel region of a first conductivity type; a fourth semiconductor layer of the second conductivity type disposed along the upper surface of the semiconductor multilayer film; and a semiconductor multilayer film having a channel region of a first conductivity type; a gate electrode arranged, a source electrode arranged apart from the gate electrode, a drain electrode arranged on the lower surface side of the substrate, and the second electrode arranged at the terminal end of the nitride semiconductor device. a trench that penetrates the semiconductor layer and reaches at least the first semiconductor layer; an interlayer insulating film disposed above the gate electrode; a source wiring that penetrates the interlayer insulating film and reaches the source electrode; Equipped with The end of the interlayer insulating film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. is also located on the outside.

A nitride semiconductor device according to another aspect of the present disclosure includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, and a first semiconductor layer disposed above the first semiconductor layer. a second semiconductor layer of a second conductivity type; a fifth semiconductor layer disposed above the second semiconductor layer; and a sixth semiconductor layer disposed above the fifth semiconductor layer. a second opening penetrating the sixth semiconductor layer, the fifth semiconductor layer and the second semiconductor layer to reach the first semiconductor layer; and an inner surface of the second opening. a gate insulating film disposed along the sixth semiconductor layer and with another portion disposed above the sixth semiconductor layer; a gate electrode disposed along the upper surface of the gate insulating film; and a gate electrode spaced apart from the gate electrode. a source electrode disposed as a base electrode, a drain electrode disposed on the lower surface side of the substrate, and at least the first semiconductor layer provided at the terminal end of the nitride semiconductor device. The semiconductor device includes a groove portion reaching the semiconductor layer, an interlayer insulating film disposed above the gate electrode, and a source wiring penetrating the interlayer insulating film and reaching the source electrode. The end of the interlayer insulating film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. is also located on the outside.

According to the present disclosure, a nitride semiconductor device with improved off-characteristics can be provided.

FIG. 1 is a cross-sectional view of a nitride semiconductor device according to a first embodiment. FIG. 2 is a plan view of the nitride semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a second embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a first modification of the second embodiment. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a second modification of the second embodiment. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to Embodiment 3. FIG. 7 is a cross-sectional view of a nitride semiconductor device according to Embodiment 4. FIG. 8 is a cross-sectional view of a nitride semiconductor device according to Embodiment 5. FIG. 9 is a cross-sectional view of a nitride semiconductor device according to a sixth embodiment.

(Findings that formed the basis of this disclosure)
The present inventors have found that the following problem occurs with the conventional semiconductor device described in the "Background Art" section.

Patent Document 1 discloses a semiconductor device that is a vertical trench gate MOSFET (Metal Oxide Semiconductor). A step portion is provided on the outer periphery of the semiconductor device to expose the pn junction interface. The semiconductor device includes a protective film that covers the side and bottom surfaces of the stepped portion, and a field plate electrode that covers the side and bottom surfaces of the stepped portion via the protective film.

In the semiconductor device disclosed in Patent Document 1, the pn junction interface deteriorates due to process damage when forming a protective film covering the step portion, and leakage current increases during off-time. That is, the semiconductor device disclosed in Patent Document 1 has a problem in that off-leak characteristics deteriorate.

Therefore, in order to solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, and a first semiconductor layer of a first conductivity type disposed above the substrate. a second semiconductor layer of a second conductivity type disposed above the semiconductor layer; a third semiconductor layer disposed above the second semiconductor layer; a first opening that penetrates the second semiconductor layer and reaches the first semiconductor layer; and a first opening that is partially disposed along the inner surface of the first opening and above the third semiconductor layer. a semiconductor multilayer film having a channel region of the first conductivity type and a fourth semiconductor layer of the second conductivity type disposed along the upper surface of the semiconductor multilayer film; , a gate electrode disposed above the fourth semiconductor layer, a source electrode disposed apart from the gate electrode, a drain electrode disposed on the lower surface side of the substrate, and a gate electrode disposed above the fourth semiconductor layer; a groove provided at a termination portion that penetrates the second semiconductor layer and reaches at least the first semiconductor layer; an interlayer insulating film disposed above the gate electrode; and a trench that penetrates the interlayer insulating film. and a source wiring that reaches the source electrode. The end of the interlayer insulating film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. is also located on the outside.

As a result, no interlayer insulating film is formed in the groove provided at the end of the nitride semiconductor device, thereby eliminating process damage to the pn junction interface. Therefore, off-leak characteristics can be improved.

Further, for example, a nitride semiconductor device according to one aspect of the present disclosure includes a surface protection film disposed above the source wiring. The end of the surface protective film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. may also be located outside.

Thereby, adhesion of dirt, dust, etc. to the surface of the nitride semiconductor device can be suppressed. Furthermore, since the surface protective film can suppress moisture from entering, the reliability of the nitride semiconductor device can be improved.

Further, for example, the angle between the side wall of the groove and the upper surface of the second semiconductor layer may be less than 90 degrees.

This makes it possible to alleviate the concentration of electric field at the terminal end of the nitride semiconductor device, thereby improving off-leak characteristics.

Further, for example, the depth of the groove may be 1 μm or more, or the groove may reach as far as the substrate.

As a result, the groove becomes deeper, so that the distance between the surface of the nitride semiconductor device and the groove can be increased. Therefore, concentration of electric field at the terminal end of the nitride semiconductor device can be alleviated, and off-leak characteristics can be improved.

Further, for example, the interlayer insulating film may be one single layer or multilayer film selected from the group consisting of SiN, SiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , AlN, HfON, and ZrON. .

Thereby, an interlayer insulating film with low hygroscopicity and good film quality can be formed. Therefore, the intrusion of moisture can be suppressed, and the reliability of the nitride semiconductor device can be improved.

Further, for example, a high resistance layer may be provided between the first semiconductor layer and the second semiconductor layer.

If a transistor part of a nitride semiconductor device without a high-resistance layer is operated in reverse conduction mode, the withstand voltage will decrease when current flows through the second semiconductor layer from the source electrode to the drain electrode. There is a risk. This deterioration of off-characteristics due to a decrease in breakdown voltage is sometimes referred to as reverse conduction deterioration. In the nitride semiconductor device according to this aspect, by providing the high resistance layer, it is possible to suppress the current flowing through the second semiconductor layer during reverse conduction operation. Therefore, reverse conduction deterioration can be suppressed.

Note that the reverse conduction operation is to cause the transistor portion to operate as a diode by short-circuiting the source electrode and the gate electrode. In this case, the source electrode becomes the anode electrode, and the drain electrode becomes the cathode electrode.

Further, for example, the high resistance layer may contain C or Fe.

Thereby, the electrical resistance of the high-resistance layer can be increased, and reverse conduction deterioration can be further suppressed.

Further, a nitride semiconductor device according to another aspect of the present disclosure includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, and a first semiconductor layer disposed above the first semiconductor layer. a second semiconductor layer of a second conductivity type disposed, a fifth semiconductor layer disposed above the second semiconductor layer, and a sixth semiconductor layer disposed above the fifth semiconductor layer. a semiconductor layer, a second opening that penetrates the sixth semiconductor layer, the fifth semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer; a gate insulating film disposed along the inner surface and another portion of which is disposed above the sixth semiconductor layer; a gate electrode disposed along the upper surface of the gate insulating film; and the gate electrode. a source electrode arranged at a distance from the substrate, a drain electrode arranged on the lower surface side of the substrate, and at least the second semiconductor layer provided at the terminal end of the nitride semiconductor device. The semiconductor device includes a groove portion reaching one semiconductor layer, an interlayer insulating film disposed above the gate electrode, and a source wiring penetrating the interlayer insulating film and reaching the source electrode. The end of the interlayer insulating film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. is also located on the outside.

As a result, no interlayer insulating film is formed in the groove provided at the end of the nitride semiconductor device, thereby eliminating process damage to the pn junction interface. Therefore, off-leak characteristics can be improved.

Hereinafter, embodiments will be specifically described with reference to the drawings.

Note that the embodiments described below are all inclusive or specific examples. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, steps, order of steps, etc. shown in the following embodiments are examples, and do not limit the present disclosure. Further, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims will be described as arbitrary constituent elements.

Furthermore, each figure is a schematic diagram and is not necessarily strictly illustrated. Therefore, for example, the scales and the like in each figure do not necessarily match. Further, in each figure, substantially the same configurations are denoted by the same reference numerals, and overlapping explanations will be omitted or simplified.

In addition, in this specification, terms that indicate relationships between elements such as parallel or orthogonal, terms that indicate the shape of elements such as rectangle or trapezoid, and numerical ranges are not expressions that express only strict meanings. , is an expression meaning that it includes a substantially equivalent range, for example, a difference of several percent.

Furthermore, in this specification and the drawings, the x-axis, y-axis, and z-axis indicate three axes of a three-dimensional orthogonal coordinate system. When the planar view shape of the substrate is rectangular, the x-axis and the y-axis are directions parallel to the first side of the rectangle and the second side perpendicular to the first side, respectively. The z-axis is the thickness direction of the substrate. Note that in this specification, the "thickness direction" of the substrate refers to a direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also described as the "vertical direction." Further, a direction parallel to the main surface of the substrate may be referred to as a "lateral direction".

Also, the side on which the gate electrode and source electrode are provided with respect to the substrate (the positive side of the z-axis) is regarded as the "upper" or "upper side", and the side on which the drain electrode is provided with respect to the substrate (the negative side of the z-axis) side) is considered to be ``downward'' or ``lower side''.

Note that in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upward) and the lower direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacked structure. Used as a term defined by the relative positional relationship. Additionally, the terms "above" and "below" are used not only when two components are spaced apart and there is another component between them; This also applies when two components are placed in close contact with each other.

In addition, in this specification, "planar view" refers to when viewed from a direction perpendicular to the main surface of the substrate of a nitride semiconductor device, that is, when the main surface of the substrate is viewed from the front. .

In addition, in this specification, ordinal numbers such as "first" and "second" do not mean the number or order of components, unless otherwise specified, and do not mean the number or order of components. It is used for the purpose of

Furthermore, in this specification, AlGaN refers to a ternary mixed crystal Al _x Ga _1-x N (0<x<1). Hereinafter, multi-component mixed crystals will be abbreviated by the arrangement of their respective constituent element symbols, such as AlInN, GaInN, etc. For example, Al _x Ga _1-xy In _y N (0<x<1, 0<y<1, and 0<x+y<1), which is an example of a nitride semiconductor, is abbreviated as AlGaInN.

(Embodiment 1)
[overview]
First, an overview of the nitride semiconductor device according to Embodiment 1 will be explained using FIGS. 1 and 2.

FIG. 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment. FIG. 2 is a plan view of the nitride semiconductor device 1 according to this embodiment. FIG. 1 shows a cross section taken along line II in FIG. Note that in FIG. 1, the transistor section 2 and the termination section 3 are schematically shown separated.

As shown in FIG. 1, the nitride semiconductor device 1 includes a transistor section 2 and a termination section 3. Specifically, the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a first base layer 14, a second base layer 16, a gate opening 20, a semiconductor multilayer film 21, and a threshold value. It includes an adjustment layer 28, a source opening 30, a source electrode 32, a gate electrode 34, a drain electrode 36, an interlayer insulating film 42, and a source wiring 44. The semiconductor multilayer film 21 is a laminate of an electron transit layer 22 and an electron supply layer 24, and includes a two-dimensional electron gas (2DEG) 26 as a channel region. Further, the nitride semiconductor device 1 includes a groove portion 40 provided in the termination portion 3 .

Transistor section 2 is a region including an FET, and, as shown in FIG. 2, is a region including the center of nitride semiconductor device 1. Specifically, the transistor section 2 is a region in which a second base layer 16, a gate opening 20, a semiconductor multilayer film 21, a threshold adjustment layer 28, a source electrode 32, and a gate electrode 34 are arranged in a plan view. .

Note that in FIG. 2, illustration of each component arranged in the transistor section 2 is omitted. As an example, a plurality of source electrodes 32 whose planar view is long in one direction are arranged in a stripe pattern, and a gate electrode 34, a threshold adjustment layer 28, and a gate opening 20 are arranged between adjacent source electrodes 32. ing. Alternatively, a plurality of source electrodes 32 having a hexagonal shape in plan view may be arranged so as to be filled in a plane while leaving gaps between them.

The termination portion 3 is a region other than the transistor portion 2 and is provided in a ring shape surrounding the transistor portion 2. In the termination portion 3, the second base layer 16, the gate opening 20, the semiconductor multilayer film 21, the threshold adjustment layer 28, the source electrode 32, and the gate electrode 34 are not arranged. Note that the second base layer 16, the semiconductor multilayer film 21, and the threshold adjustment layer 28 may be arranged in the termination portion 3 as long as they are electrically isolated from the source electrode 32. Also in this case, the groove portion 40 reaches at least the drift layer 12.

In this embodiment, nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, nitride semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film.

In the heterostructure of the AlGaN film and the GaN film, a highly concentrated two-dimensional electron gas 26 is generated at the hetero interface due to spontaneous polarization or piezo polarization on the (0001) plane. Therefore, even in an undoped state, the interface has the characteristic that a sheet carrier concentration of 1×10 ¹³ cm ⁻² or more can be obtained.

The nitride semiconductor device 1 according to the present embodiment is a field effect transistor (FET) that uses a two-dimensional electron gas 26 generated at the AlGaN/GaN hetero interface as a channel. Specifically, nitride semiconductor device 1 is a so-called vertical FET.

The nitride semiconductor device 1 according to this embodiment is a normally-off type FET. In the nitride semiconductor device 1, for example, the source electrode 32 is grounded (that is, the potential is 0V), and the drain electrode 36 is given a positive potential. The potential applied to the drain electrode 36 is, for example, 100V or more and 1200V or less, but is not limited thereto. When the nitride semiconductor device 1 is in the off state, 0V or a negative potential (for example, −5V) is applied to the gate electrode 34. When the nitride semiconductor device 1 is in the on state, a positive potential (for example, +5V) is applied to the gate electrode 34. Note that the nitride semiconductor device 1 may be a normally-on type FET.

[composition]
Below, details of each component included in the nitride semiconductor device 1 will be explained.

The substrate 10 is a substrate made of a nitride semiconductor, and, as shown in FIG. 1, has a first main surface 10a and a second main surface 10b facing away from each other. The first main surface 10a is the main surface (upper surface) on the side where the drift layer 12 is formed. Specifically, the first main surface 10a substantially coincides with the c-plane. The second main surface 10b is the main surface (lower surface) on the side where the drain electrode 36 is formed. The shape of the substrate 10 in plan view is, for example, rectangular, but is not limited to this.

The substrate 10 is, for example, a substrate made of n ⁺ type GaN with a thickness of 300 μm and a carrier concentration of 1×10 ¹⁸ cm ⁻³ . Note that n-type and p-type indicate conductivity types of semiconductors. The n ⁺ type represents a state in which an n-type dopant is added to the semiconductor at a high concentration, so-called heavy doping. Further, n ^- type refers to a state in which an n-type dopant is added to a semiconductor at a low concentration, so-called light doping. The same applies to p ⁺ type and p ⁻ type. N-type, n ⁺ -type, and n ^- type are examples of first conductivity types. P type, p ⁺ type, and p ^- type are examples of the second conductivity type. The second conductivity type is of opposite polarity to the first conductivity type.

Note that the substrate 10 does not need to be a nitride semiconductor substrate. For example, the substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, or the like.

The drift layer 12 is an example of a first nitride semiconductor layer of a first conductivity type disposed above the substrate 10. The drift layer 12 is, for example, a film made of n ^- type GaN and has a thickness of 8 μm. The donor concentration of the drift layer 12 is, for example, in a range of 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ^{−3 or} less, and is 1×10 ¹⁶ cm ⁻³ as an example. Further, the carbon concentration (C concentration) of the drift layer 12 is in the range of 1×10 ¹⁵ cm ⁻³ or more and 2×10 ¹⁷ cm ^{−3 or} less.

The drift layer 12 is provided, for example, in contact with the first main surface 10a of the substrate 10. The drift layer 12 is formed on the first main surface 10a of the substrate 10 by, for example, crystal growth such as metal organic vapor phase epitaxial growth (MOVPE).

The first base layer 14 is an example of a second nitride semiconductor layer of the second conductivity type disposed above the drift layer 12. The first base layer 14 is, for example, a p-type GaN film having a thickness of 400 nm and a carrier concentration of 1×10 ¹⁷ cm ⁻³ . The first base layer 14 is provided in contact with the upper surface of the drift layer 12 . The first base layer 14 is formed on the drift layer 12 by, for example, crystal growth such as the MOVPE method. Note that the first base layer 14 may be formed by implanting magnesium (Mg) into the formed undoped GaN film. Undoping will be explained later.

The first base layer 14 suppresses leakage current between the source electrode 32 and the drain electrode 36. For example, when a reverse voltage is applied to the pn junction formed by the first base layer 14 and the drift layer 12, specifically, the drain electrode 36 has a higher potential than the source electrode 32. In this case, a depletion layer extends in the drift layer 12. This allows the nitride semiconductor device 1 to have a high breakdown voltage. In this embodiment, the drain electrode 36 has a higher potential than the source electrode 32 in both the off state and the on state, except in the case of reverse conduction operation. Therefore, a high breakdown voltage of the nitride semiconductor device 1 is realized.

In this embodiment, the first base layer 14 is in contact with the source electrode 32, as shown in FIG. Therefore, the first base layer 14 is fixed at the same potential as the source electrode 32.

The second base layer 16 is an example of a third nitride semiconductor layer disposed above the first base layer 14. The second base layer 16 is a high resistance layer having a higher resistance than the first base layer 14. The second base layer 16 is formed from an insulating or semi-insulating nitride semiconductor. The second base layer 16 is, for example, a film made of undoped GaN with a thickness of 200 nm. The second base layer 16 is provided in contact with the first base layer 14. The second base layer 16 is formed on the first base layer 14 by, for example, crystal growth such as MOVPE.

Note that "undoped" herein means that a dopant such as Si or Mg that changes the polarity of GaN to n-type or p-type is not doped. In this embodiment, the second base layer 16 is doped with carbon (C). Specifically, the carbon concentration of the second base layer 16 is higher than the carbon concentration of the first base layer 14.

Further, the second base layer 16 may contain silicon (Si) or oxygen (O) mixed during film formation. In this case, the carbon concentration of the second underlayer 16 is higher than the silicon concentration (Si concentration) or the oxygen concentration (O concentration). For example, the carbon concentration of the second base layer 16 is, for example, 3×10 ¹⁷ cm ⁻³ or more, but may be 1×10 ¹⁸ cm ⁻³ or more. The silicon concentration or oxygen concentration of the second base layer 16 is, for example, 5×10 ¹⁶ cm ⁻³ or less, but may be 2×10 ¹⁶ cm ⁻³ or less.

Note that the second base layer 16 may be formed by ion implantation of magnesium (Mg), iron (Fe), boron (B), or the like other than carbon. Other ion species may be used as long as they can realize high resistance of GaN.

Here, if the nitride semiconductor device 1 does not include the second base layer 16, the electron transport layer 22 and the p-type first base layer 14 are provided between the source electrode 32 and the drain electrode 36. A parasitic npn structure called the n-type drift layer 12, that is, a parasitic bipolar transistor exists. Therefore, when the nitride semiconductor device 1 is in the off state, when current flows through the p-type first base layer 14, the parasitic bipolar transistor is turned on and the breakdown voltage of the nitride semiconductor device 1 is reduced. There is a risk of deterioration. In this case, malfunction of the nitride semiconductor device 1 is likely to occur. In this embodiment, by providing the high-resistance second base layer 16, formation of a parasitic npn structure can be suppressed, and malfunction of the nitride semiconductor device 1 can be suppressed.

Note that a layer for suppressing diffusion of p-type impurities such as Mg from the first base layer 14 may be provided on the upper surface of the second base layer 16. For example, an AlGaN layer with a thickness of 20 nm may be provided on the second base layer 16.

The gate opening 20 is an example of a first opening that penetrates the second base layer 16 and the first base layer 14 to reach the drift layer 12. Gate opening 20 penetrates both second underlayer 16 and first underlayer 14 . The bottom 20a of the gate opening 20 is part of the top surface of the drift layer 12. As shown in FIG. 1, the bottom portion 20a is located below the lower surface of the first base layer 14. Note that the lower surface of the first base layer 14 corresponds to the interface between the first base layer 14 and the drift layer 12. The bottom portion 20a is, for example, parallel to the first main surface 10a of the substrate 10.

In this embodiment, the gate opening 20 is formed so that the further away from the substrate 10 the larger the opening area becomes. Specifically, the side wall 20b of the gate opening 20 is obliquely inclined. As shown in FIG. 1, the cross-sectional shape of the gate opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

The angle of inclination of the side wall 20b with respect to the bottom portion 20a is, for example, in a range of 30° or more and 45° or less. The smaller the inclination angle, the closer the sidewall 20b is to the c-plane, so that the quality of the film such as the electron transit layer 22 formed along the sidewall 20b by crystal regrowth can be improved. On the other hand, the larger the inclination angle, the more the gate opening 20 is prevented from becoming too large, and the nitride semiconductor device 1 can be made smaller.

The gate opening 20 is formed by forming the drift layer 12, the first base layer 14, and the second base layer 16 in this order on the first main surface 10a of the substrate 10 by continuous film formation, and then partially It is formed by removing a portion of each of the second base layer 16 and the first base layer 14 so as to expose the drift layer 12 . At this time, by removing a predetermined thickness of the surface layer portion of the drift layer 12, the bottom portion 20a of the gate opening 20 is formed below the lower surface of the first base layer 14.

Removal of the second base layer 16 and the first base layer 14 is performed by resist application and patterning, and dry etching. Specifically, by patterning the resist and then baking it, the ends of the resist are obliquely inclined. Dry etching is then performed to form a gate opening 20 with an oblique sidewall 20b so that the shape of the resist is transferred.

A portion of the semiconductor multilayer film 21 is disposed along the inner surface of the gate opening 20, and another portion is disposed above the second base layer 16. The semiconductor multilayer film 21 is a laminated film including an electron transit layer 22 and an electron supply layer 24.

The electron transit layer 22 is an example of a first regrowth layer provided along the inner surface of the gate opening 20. Specifically, part of the electron transport layer 22 is provided along the bottom 20a and sidewall 20b of the gate opening 20, and the other part of the electron transport layer 22 is provided on the upper surface of the second base layer 16. It is provided. The electron transport layer 22 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that the electron transit layer 22 may be made n-type by doping with Si or the like instead of being undoped.

The electron transit layer 22 is in contact with the drift layer 12 at the bottom 20a and sidewalls 20b of the gate opening 20. The electron transit layer 22 is in contact with each end face of the first base layer 14 and the second base layer 16 at the side wall 20b of the gate opening 20. Furthermore, the electron transit layer 22 is in contact with the upper surface of the second base layer 16. The electron transit layer 22 is formed by crystal regrowth after the gate opening 20 is formed.

The electron transit layer 22 has a channel region. Specifically, two-dimensional electron gas 26 is generated near the interface between electron transport layer 22 and electron supply layer 24 . Two-dimensional electron gas 26 functions as a channel for electron transport layer 22 . In FIG. 1, the two-dimensional electron gas 26 is schematically illustrated with broken lines. The two-dimensional electron gas 26 is bent along the interface between the electron transit layer 22 and the electron supply layer 24, that is, along the inner surface of the gate opening 20.

Although not shown in FIG. 1, an AlN film with a thickness of approximately 1 nm may be provided as a second regrowth layer between the electron transit layer 22 and the electron supply layer 24. The AlN film can suppress alloy scattering and improve channel mobility.

The electron supply layer 24 is an example of a third regrowth layer provided along the inner surface of the gate opening 20. The electron transit layer 22 and the electron supply layer 24 are provided in this order from the substrate 10 side. The electron supply layer 24 is formed in a shape along the upper surface of the electron transit layer 22 and has a substantially uniform thickness. The electron supply layer 24 is, for example, a film made of undoped AlGaN with a thickness of 50 nm. The electron supply layer 24 is formed by crystal regrowth subsequent to the step of forming the electron transit layer 22.

The electron supply layer 24 forms an AlGaN/GaN hetero interface with the electron transit layer 22. As a result, a two-dimensional electron gas 26 is generated within the electron transit layer 22. The electron supply layer 24 supplies electrons to the channel region (ie, the two-dimensional electron gas 26) formed in the electron transit layer 22.

The threshold adjustment layer 28 is an example of a fourth nitride semiconductor layer of the second conductivity type disposed along the upper surface of the semiconductor multilayer film 21. Specifically, the threshold adjustment layer 28 is provided between the gate electrode 34 and the electron supply layer 24. The threshold adjustment layer 28 is formed in a shape along the upper surface of the electron supply layer 24 and has a substantially uniform thickness.

The threshold adjustment layer 28 is, for example, a nitride semiconductor layer made of p-type GaN or AlGaN and has a thickness of 100 nm and a carrier concentration of 1×10 ¹⁷ cm ⁻³ . The threshold value adjustment layer 28 is formed by re-growth using the MOVPE method following the step of forming the electron supply layer 24 and patterning.

By providing the threshold adjustment layer 28, the potential at the conduction band edge of the channel portion is raised. Therefore, the threshold voltage of nitride semiconductor device 1 can be increased. Therefore, the nitride semiconductor device 1 can be realized as a normally-off type FET. That is, when a potential of 0 V is applied to the gate electrode 34, the nitride semiconductor device 1 can be turned off.

The source opening 30 is an example of a second opening that penetrates the semiconductor multilayer film 21 and the second base layer 16 and reaches the first base layer 14 at a position away from the gate opening 20 . The source opening 30 is located at a distance from the gate electrode 34 in plan view.

The bottom 30a of the source opening 30 is a part of the upper surface of the first underlayer 14. As shown in FIG. 1, the bottom portion 30a is located below the lower surface of the second base layer 16. Note that the lower surface of the second base layer 16 corresponds to the interface between the second base layer 16 and the first base layer 14. The bottom portion 30a is parallel to the first main surface 10a of the substrate 10, for example.

As shown in FIG. 1, the source opening 30 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the sidewall 30b of the source opening 30 is perpendicular to the bottom 30a. That is, the cross-sectional shape of the source opening 30 is rectangular.

Alternatively, similarly to the gate opening 20, the source opening 30 may be formed such that the opening area increases as the distance from the substrate 10 increases. Specifically, the side wall 30b of the source opening 30 may be obliquely inclined. For example, the cross-sectional shape of the source opening 30 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid. At this time, the angle of inclination of the side wall 30b with respect to the bottom portion 30a may be, for example, in a range of 30° or more and 60° or less. For example, the inclination angle of the sidewall 30b of the source opening 30 may be greater than the inclination angle of the sidewall 20b of the gate opening 20. Since the side wall 30b is obliquely inclined, the contact area between the source electrode 32 and the electron transit layer 22 (two-dimensional electron gas 26) increases, making it easier to establish an ohmic connection. Note that the two-dimensional electron gas 26 is exposed on the side wall 30b of the source opening 30, and is connected to the source electrode 32 at the exposed portion.

For example, the source opening 30 is formed at a threshold value such that the first underlayer 14 is exposed in a region different from the gate opening 20 following the step of forming the threshold adjustment layer 28 (i.e., the crystal regrowth step). It is formed by etching the adjustment layer 28, the electron supply layer 24, the electron transit layer 22, and the second base layer 16. At this time, by also removing the surface layer portion of the first underlayer 14, the bottom 30a of the source opening 30 is formed below the lower surface of the second underlayer 16. The source opening 30 is formed into a predetermined shape by, for example, photolithographic patterning and dry etching.

The source electrode 32 is spaced apart from the gate electrode 34. In this embodiment, the source electrode 32 is provided along the inner surface of the source opening 30. Specifically, the source electrode 32 is connected to each of the electron supply layer 24, the electron transit layer 22, and the first base layer 14. The source electrode 32 is ohmically connected to each of the electron transit layer 22 and the electron supply layer 24 . The source electrode 32 is in direct contact with the two-dimensional electron gas 26 at the sidewall 30b. Thereby, the contact resistance between the source electrode 32 and the two-dimensional electron gas 26 (channel) can be reduced.

The source electrode 32 is formed using a conductive material such as metal. As the material of the source electrode 32, for example, a material such as Ti/Al that can be ohmically connected to the n-type GaN layer by heat treatment can be used. The source electrode 32 is formed, for example, by patterning a conductive film formed by sputtering or vapor deposition.

Gate electrode 34 is placed above threshold adjustment layer 28 . Specifically, the gate electrode 34 is provided in contact with the upper surface of the threshold adjustment layer 28 so as to cover the gate opening 20 . For example, the gate electrode 34 is formed in a shape along the upper surface of the threshold adjustment layer 28 and has a substantially uniform thickness. Alternatively, the gate electrode 34 may be formed to fill a recessed portion on the upper surface of the threshold adjustment layer 28.

The gate electrode 34 is formed using a conductive material such as metal. For example, the gate electrode 34 is formed using palladium (Pd). Note that as the material of the gate electrode 34, a material that is ohmically connected to the p-type GaN layer can be used, such as a nickel (Ni)-based material, tungsten silicide (WSi), gold (Au), etc. Can be used. The gate electrode 34 is formed by patterning a conductive film formed by sputtering or vapor deposition, for example, after the threshold adjustment layer 28 is formed, the source opening 30 is formed, or the source electrode 32 is formed. Ru.

The drain electrode 36 is provided on the lower surface side of the substrate 10, that is, on the opposite side from the drift layer 12. Specifically, the drain electrode 36 is provided in contact with the second main surface 10b of the substrate 10. The drain electrode 36 is formed using a conductive material such as metal. As the material of the drain electrode 36, similarly to the material of the source electrode 32, a material that is ohmically connected to the n-type GaN layer, such as Ti/Al, can be used. The drain electrode 36 is formed, for example, by patterning a conductive film formed by sputtering, vapor deposition, or the like.

[Characteristic configuration]
Next, the main characteristic configuration of the nitride semiconductor device 1 according to this embodiment will be explained. First, the configuration of the termination portion 3 of the nitride semiconductor device 1 will be described.

As shown in FIG. 1, in the present embodiment, the second base layer 16, the semiconductor multilayer film 21, and the threshold adjustment layer 28 are not provided in the termination portion 3. For example, at the same time as the source opening 30 is formed, the second base layer 16, the semiconductor multilayer film 21, and the threshold adjustment layer 28 in the termination portion 3 are removed. In the termination portion 3, the upper surface of the first underlayer 14 is located at the same height as the bottom portion 30a of the source opening 30. Note that "the same height" means that the distance from the first main surface 10a of the substrate 10 is the same.

A groove portion 40 is provided in the terminal end portion 3 . The trench portion 40 is an isolation trench for partitioning and isolating the transistor portion 2 . The groove portion 40 penetrates the first base layer 14 and reaches the drift layer 12 .

The groove portion 40 has a bottom portion 40a and a side wall 40b. In this embodiment, the groove portion 40 is a stepped portion having a sidewall 40b only on the transistor portion 2 side. That is, the bottom 40a of the groove 40 is connected to the end surface of the nitride semiconductor device 1. The groove portion 40 is provided in a ring shape surrounding the transistor portion 2, as shown in FIG.

The bottom 40a of the groove 40 is a part of the upper surface of the drift layer 12. As shown in FIG. 1, the bottom portion 40a is located below the lower surface of the first base layer 14. The bottom portion 40a is, for example, parallel to the first main surface 10a of the substrate 10.

As shown in FIG. 1, the groove portion 40 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the side wall 40b of the groove portion 40 is perpendicular to the bottom portion 40a. That is, the cross-sectional shape of the groove portion 40 is rectangular.

The depth of the groove portion 40 is, for example, 1 μm or more. The depth of the groove 40 is the height of the side wall 40b, and is the distance (length in the z-axis direction) between the top surface of the first base layer 14 at the terminal end 3 and the bottom 40a of the groove 40. As the groove portion 40 becomes deeper, the distance between the surface (upper surface) of the nitride semiconductor device 1 and the bottom portion 40a of the groove portion 40 at the termination portion 3 becomes longer. This makes it possible to alleviate the concentration of electric field at the terminal end 3, and reduce leakage current during off-time.

Note that the groove portion 40 may reach the substrate 10. That is, the bottom 40a of the groove 40 may be the first main surface 10a of the substrate 10. By maximizing the depth of the groove portion 40, leakage current can be further reduced.

The groove portion 40 is formed by forming the interlayer insulating film 42 and then performing dry etching. Alternatively, after forming the source wiring 44, the groove portion 40 may be formed by dry etching.

Interlayer insulating film 42 is placed above gate electrode 34 . Specifically, the interlayer insulating film 42 covers almost the entire region of the transistor section 2, and its end portion is disposed at the termination portion 3. A contact hole 43 for exposing the source electrode 32 is provided in the interlayer insulating film 42 .

The interlayer insulating film 42 is, for example, an insulating film containing an inorganic material as a main component. Specifically, the interlayer insulating film 42 is one single layer or multilayer film selected from the group consisting of SiN, SiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , AlN, HfON, and ZrON.

By using such an inorganic material, the moisture permeability of the interlayer insulating film 42 can be reduced compared to the case where an organic material is used. That is, the interlayer insulating film 42 can more strongly suppress the intrusion of moisture.

For example, the interlayer insulating film 42 is formed by forming an inorganic film on the entire surface by plasma CVD (Chemical Vapor Deposition) or sputtering after forming the gate electrode 34 and the source electrode 32, and then patterning it into a predetermined shape. . Contact holes 43 are formed by patterning. At the same time as the contact hole 43 is formed, the end portion for forming the groove portion 40 in a later step may also be removed at the same time.

As shown in FIG. 1, a source wiring 44 is provided to cover the interlayer insulating film 42. The source wiring 44 penetrates the interlayer insulating film 42 and reaches the source electrode 32. Specifically, the source wiring 44 is provided to fill the contact hole 43 and electrically connects the plurality of source electrodes 32.

The source wiring 44 is formed using a conductive material such as metal. For example, the same material as the source electrode 32 can be used as the material for the source wiring 44.

In this embodiment, the end of the interlayer insulating film 42 is located within the range inside the end of the groove 40 and outside the outermost portion of the source electrode 32 in plan view. ing. As shown in FIG. 1, the distance between the end of the interlayer insulating film 42 and the end of the groove 40 (that is, the upper end of the side wall 40b) is d. Further, the distance between the part of the source electrode 32 closest to the end of the groove 40 and the end of the groove 40 is defined as A. In this case, 0≦d<A is satisfied.

0≦d means that the interlayer insulating film 42 is not provided in the groove portion 40. Specifically, since the groove portion 40 is formed after the interlayer insulating film 42 is formed, 0≦d can be easily satisfied. For example, d=0 can be easily achieved by removing the end of the interlayer insulating film 42 using a mask used for dry etching to form the groove 40. By forming the groove 40 continuously from the removal of the end portion of the interlayer insulating film 42, it is possible to prevent the interlayer insulating film 42 from being formed within the groove 40.

At the side wall 40b of the groove portion 40, the interface between the n-type drift layer 12 and the p-type first base layer 14, that is, the end of the p-n junction interface is exposed. The pn junction interface is exposed when the trench 40 is formed. That is, the pn junction interface is exposed in a step after forming the interlayer insulating film 42.

Plasma CVD and sputtering when forming the interlayer insulating film 42 tend to cause process damage to the underlying layer during film formation. Therefore, when the interlayer insulating film 42 is formed within the trench 40, there is a risk that the pn junction interface exposed on the sidewall 40b may deteriorate due to process damage. According to this embodiment, the groove portion 40 can be formed after the interlayer insulating film 42 is formed, so that process damage during the formation of the interlayer insulating film 42 can be eliminated. Therefore, damage caused during formation of the interlayer insulating film 42 can be suppressed from entering the pn junction interface. Therefore, since deterioration of the pn junction interface is suppressed, an increase in leakage current during off-time can be suppressed.

Furthermore, by satisfying d<A, that is, by providing the interlayer insulating film 42 in the vicinity of the termination portion 3 so that the source electrode 32 is not exposed, short circuits or leakage currents through the source electrode 32 can be prevented. The occurrence can be suppressed. As d approaches 0, that is, as the end of the interlayer insulating film 42 approaches the side wall 40b of the trench 40, the protection range becomes wider, so that the protection function of the transistor section 2 can be enhanced.

(Embodiment 2)
Next, Embodiment 2 will be described.

The second embodiment differs from the first embodiment in that a surface protective film is provided. Below, the explanation will focus on the differences from Embodiment 1, and the explanation of the common points will be omitted or simplified.

FIG. 3 is a cross-sectional view of nitride semiconductor device 101 according to this embodiment. As shown in FIG. 3, nitride semiconductor device 101 further includes a surface protection film 146, compared to nitride semiconductor device 1 shown in FIG.

The surface protection film 146 is arranged above the source wiring 44. Specifically, the surface protection film 146 covers almost the entire area of the transistor section 2, and its end portion is disposed at the termination portion 3. The surface protection film 146 contacts and covers the upper surface of the source wiring 44 and the upper surface of the interlayer insulating film 42 in the portion where the source wiring 44 is not provided.

The surface protection film 146 is, for example, an insulating film containing an organic material as a main component. For example, the surface protective film 146 is formed by forming the source wiring 44, applying an organic material to the entire surface by a coating method, and then patterning it into a predetermined shape. Patterning is performed, for example, before forming the groove portion 40. The surface protection film 146 is formed using, for example, a material with low moisture permeability.

Note that the surface protection film 146 may be an insulating film containing an inorganic material as a main component. For example, the surface protective film 146 may be a single layer or a multilayer film selected from the group consisting of SiN, SiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , AlN, HfON, and ZrON.

In this embodiment, the end of the surface protection film 146 is located in a range inside the end of the groove 40 and outside the outermost portion of the source electrode 32 in plan view. ing. As shown in FIG. 3, the end of the surface protection film 146 coincides with the end of the interlayer insulating film 42 in plan view. For example, by etching the surface protection film 146 and the interlayer insulating film 42 all at once, the ends can be made to coincide. By forming the groove portion 40 after removing each end of the surface protective film 146 and the interlayer insulating film 42, process damage during forming the surface protective film 146 and the interlayer insulating film 42 can be avoided at the pn junction interface of the sidewall 40b. can be prevented from entering. Thereby, leakage current during off-time can be suppressed.

By providing the surface protection film 146, it is possible to suppress moisture from entering the transistor portion 2 (a portion where a transistor operates). Therefore, the reliability of the nitride semiconductor device 101 can be improved.

Note that the end of the surface protection film 146 does not have to coincide with the end of the interlayer insulating film 42. Below, a modification of this embodiment will be described using FIGS. 4 and 5. 4 and 5 are cross-sectional views of nitride semiconductor devices 102 and 103 according to Modifications 1 and 2 of this embodiment, respectively.

In the nitride semiconductor device 102 shown in FIG. 4, the end of the surface protection film 146 is located closer to the groove 40 than the end of the interlayer insulating film 42. That is, the end of the surface protection film 146 is located between the end of the groove 40 (the upper end of the side wall 40b) and the end of the interlayer insulating film 42 in plan view. Such a surface protection film 146 can be formed, for example, after removing the end portion of the interlayer insulating film 42 and before forming the groove portion 40.

Thereby, the end portion of the interlayer insulating film 42 can be covered with the surface protection film 146 so as not to be exposed. By increasing the area covered by the surface protection film 146, the effect of suppressing moisture intrusion can be further enhanced. Therefore, the reliability of the nitride semiconductor device 102 can be further improved.

In the nitride semiconductor device 103 shown in FIG. 5, the end of the surface protection film 146 is located closer to the source electrode 32 than the end of the interlayer insulating film 42. That is, the end of the surface protection film 146 is located between the end of the interlayer insulating film 42 and the outermost portion of the source electrode 32 in plan view. Such a surface protection film 146 can be formed, for example, after removing the end portion of the interlayer insulating film 42 and before forming the groove portion 40. Alternatively, the surface protection film 146 may be formed before the end portion of the interlayer insulating film 42 is removed.

(Embodiment 3)
Next, Embodiment 3 will be described.

In the third embodiment, the shape of the groove is different from that in the second embodiment. Below, the explanation will focus on the differences from Embodiment 2, and the explanation of the common points will be omitted or simplified.

FIG. 6 is a cross-sectional view of nitride semiconductor device 201 according to this embodiment. As shown in FIG. 6, nitride semiconductor device 201 includes a trench 240 instead of trench 40, compared to nitride semiconductor device 101 shown in FIG.

The groove portion 240 has an inclined side wall 240b. The angle θ between the side wall 240b and the upper surface of the first base layer 14 is less than 90 degrees. The inclined sidewall 240b can be formed by using a mask with obliquely inclined ends as a mask used for dry etching. For example, by patterning a resist and then baking it, the edges of the resist become obliquely inclined. After that, by performing dry etching using the resist as a mask, the shape of the resist is transferred to form the groove portion 240 having the oblique sidewall 240b.

Note that in the example shown in FIG. 6, the groove portion 240 does not have a bottom and has a shape obtained by cutting off the end portion of the first base layer 14 diagonally, but the groove portion 240 is not limited to this. The groove portion 240 may have a bottom parallel to the first main surface 10a of the substrate 10, for example.

As described above, since the side wall 240b of the groove portion 240 is obliquely inclined, concentration of the electric field at the terminal end portion 3 can be alleviated. Therefore, leakage current during off-time can be reduced.

Note that in this embodiment, a configuration in which the nitride semiconductor device 101 according to the second embodiment includes the groove portion 240 has been described; It may be included in a physical semiconductor device. Specifically, the nitride semiconductor device 1 or 102 or 103 may include the groove portion 240.

(Embodiment 4)
Next, Embodiment 4 will be described.

In the fourth embodiment, the positions of the ends of the interlayer insulating film and the surface protection film are different from those in the second embodiment. Below, the explanation will focus on the differences from Embodiment 2, and the explanation of the common points will be omitted or simplified.

FIG. 7 is a cross-sectional view of a nitride semiconductor device 301 according to this embodiment. As shown in FIG. 7, in the nitride semiconductor device 301, the end of the interlayer insulating film 42 and the end of the surface protection film 146 are aligned with the end of the groove 40 (the upper end of the side wall 40b) in a plan view. We are doing so. That is, the distance d between the end of the interlayer insulating film 42 and the end of the groove 40 is zero. In this configuration, for example, the end portions of the surface protection film 146 and the interlayer insulating film 42 are removed by etching in this order, and the first base layer 14 and the drift layer 12 are successively etched using the same mask. It is formed by removing the part. In other words, there is no need to change the etching mask, and manufacturing can be performed using a simple process.

Note that the positional relationship between the end of the interlayer insulating film 42, the end of the surface protective film 146, and the end of the groove 40 is not limited to the example shown in FIG. 7, and may be used in other embodiments and modifications. The positional relationship shown in the example may be used.

Further, in the nitride semiconductor device 301 according to the present embodiment, the groove portion 240 according to the third embodiment may be provided instead of the groove portion 40.

(Embodiment 5)
Next, Embodiment 5 will be described.

The fifth embodiment differs from the fourth embodiment in that it includes a high resistance layer. Below, the explanation will focus on the differences from Embodiment 4, and the explanation of the common points will be omitted or simplified.

FIG. 8 is a cross-sectional view of nitride semiconductor device 401 according to this embodiment. As shown in FIG. 8, nitride semiconductor device 401 further includes a high resistance layer 418, compared to nitride semiconductor device 301 shown in FIG.

The high resistance layer 418 is disposed between the drift layer 12 and the first base layer 14, respectively. The high resistance layer 418 is a layer with higher resistance than the drift layer 12. For example, the high resistance layer 418 is a layer having a lower concentration of impurities of the first conductivity type than the drift layer 12. The high resistance layer 418 is made of, for example, an insulating or semi-insulating nitride semiconductor. The impurity concentration (donor concentration) of the high resistance layer 418 is, for example, 1×10 ¹⁶ cm ⁻³ or less. The high resistance layer 418 is, for example, a 200 nm thick film made of undoped GaN.

High resistance layer 418 contains carbon (C) or iron (Fe). The carbon concentration or iron concentration of the high resistance layer 418 is, for example, in a range of 2×10 ¹⁶ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less, and is 1×10 ¹⁸ cm ⁻³ as an example. Note that other elements may be used as long as they can realize high resistance of GaN.

In this embodiment, as shown in FIG. 8, the groove portion 40 penetrates the high resistance layer 418. That is, as in the first embodiment, the bottom 40a of the groove 40 is located in the drift layer 12.

Note that the bottom portion 40a of the groove portion 40 may be a part of the upper surface of the high resistance layer 418. That is, the groove portion 40 does not need to penetrate the high resistance layer 418. This makes it easier for the depletion layer to extend in the lateral direction of the high-resistance layer 418 in the vicinity of the groove 40, making it possible to alleviate electric field concentration. Therefore, the off-state characteristics of the nitride semiconductor device 401 can be improved.

As described above, in the nitride semiconductor device 401 according to the present embodiment, since the high resistance layer 418 is provided, the first base layer 14 and the drift layer 12 are connected to each other during the reverse conduction operation of the transistor section 2. It is possible to make it difficult for current to flow through the pn junction. This suppresses reverse conduction deterioration, so that deterioration of the off-characteristics of the nitride semiconductor device 401 can be suppressed.

Note that in this embodiment, a configuration in which the nitride semiconductor device 301 according to Embodiment 4 includes the high-resistance layer 418 has been described; It may be included in a semiconductor device. That is, the nitride semiconductor device 1, 101 to 103, or 201 may include the high resistance layer 418.

Further, in nitride semiconductor device 401 according to the present embodiment, groove 240 according to Embodiment 3 may be provided instead of groove 40.

(Embodiment 6)
Next, Embodiment 6 will be described.

The sixth embodiment differs from the fourth embodiment mainly in the arrangement of the semiconductor multilayer film. Below, the explanation will focus on the differences from Embodiment 4, and the explanation of the common points will be omitted or simplified.

FIG. 9 is a cross-sectional view of a nitride semiconductor device 501 according to this embodiment. As shown in FIG. 9, compared to the nitride semiconductor device 301 shown in FIG. The difference is that a portion 520, a semiconductor multilayer film 521, and a gate insulating film 528 are provided.

The semiconductor multilayer film 521 includes an electron transport layer 522 and an electron supply layer 524.

The electron transit layer 522 is an example of a fifth nitride semiconductor layer disposed above the first base layer 14. The electron transport layer 522 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that the electron transit layer 522 may be made n-type by doping with Si or the like instead of being undoped. The electron transit layer 522 has the same function as the second base layer 16.

The electron supply layer 524 is an example of a sixth nitride semiconductor layer disposed above the electron transit layer 522. The electron supply layer 524 is, for example, a film made of undoped AlGaN with a thickness of 50 nm. The electron supply layer 524 is formed by crystal growth subsequent to the step of forming the electron transit layer 522.

The electron supply layer 524 forms an AlGaN/GaN hetero interface with the electron transit layer 522. As a result, a two-dimensional electron gas (not shown) is generated within the electron transit layer 522. The electron supply layer 524 supplies electrons to the two-dimensional electron gas formed in the electron transit layer 522.

In this embodiment, the gate opening 520 penetrates the electron supply layer 524, the electron transit layer 522, and the first underlayer 14 to reach the drift layer 12. The bottom 520a of the gate opening 520 is part of the top surface of the drift layer 12. As shown in FIG. 9, the bottom portion 520a is located below the lower surface of the first base layer 14. Note that the lower surface of the first base layer 14 corresponds to the interface between the first base layer 14 and the drift layer 12. The bottom portion 520a is, for example, parallel to the first main surface 10a of the substrate 10.

As shown in FIG. 9, the gate opening 520 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, sidewall 520b of gate opening 520 is perpendicular to bottom 520a. That is, the cross-sectional shape of the gate opening 520 is rectangular.

Alternatively, the gate opening 520 may be formed such that the opening area increases as the distance from the substrate 10 increases, similar to the gate opening 20 of the first embodiment. Specifically, the side wall 520b of the gate opening 520 may be obliquely inclined. For example, the cross-sectional shape of the gate opening 520 may be an inverted trapezoid, more specifically an inverted isosceles trapezoid.

The gate opening 520 is formed by sequentially forming a drift layer 12, a first base layer 14, an electron transit layer 522, and an electron supply layer 524 in this order on the first main surface 10a of the substrate 10. Thereafter, a portion of each of the electron supply layer 524, the electron transit layer 522, and the first base layer 14 is removed so as to partially expose the drift layer 12. At this time, by removing a predetermined thickness of the surface layer portion of the drift layer 12, the bottom portion 520a of the gate opening 520 is formed below the lower surface of the first base layer 14.

The gate insulating film 528 is, for example, an oxide film of SiO ₂ , SiN, Al ₂ O ₃ or the like. In the nitride semiconductor device 501 according to this embodiment, the gate insulating film 528 and the gate electrode 34 are provided in this order along the inner surface of the gate opening 520. Specifically, part of the gate insulating film 528 is provided along the bottom 520a and sidewall 520b of the gate opening 520, and the other part of the gate insulating film 528 is provided on the top surface of the electron supply layer 524. ing. The gate insulating film 528 is in contact with each end face of the first base layer 14, the electron transit layer 522, and the electron supply layer 524 at the side wall 520b of the gate opening 520.

When a predetermined voltage is applied to the gate electrode 34, an inverted region inverted to an n-type is formed near the end surface of the p-type first base layer 14 in contact with the gate insulating film 528. Since the inversion region functions as a channel, the electron transport layer 522 and the drift layer 12 are electrically connected, so that a current flows between the source electrode 32 and the drain electrode 36. In this way, the nitride semiconductor device 501 according to this embodiment can operate equivalent to a so-called MOSFET.

Also in this embodiment, in the termination portion 3, the end of the interlayer insulating film 42 coincides with the end of the groove 40 in plan view. Therefore, similarly to other embodiments, leakage current during off-time can be reduced.

Note that, similarly to other embodiments, the end of the interlayer insulating film 42 is located within the range inside the end of the groove 40 and from the outermost portion of the source electrode 32 in plan view. may also be located outside. Further, the end of the surface protection film 146 does not have to coincide with the end of the interlayer insulating film 42 as in the second embodiment and its modification.

(Other embodiments)
Although the nitride semiconductor device according to one or more aspects has been described above based on the embodiments, the present disclosure is not limited to these embodiments. Unless departing from the spirit of the present disclosure, various modifications that can be thought of by those skilled in the art to this embodiment, and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure. It will be done.

For example, the source opening 30 may not be provided. In this case, the source electrode 32 is provided at a position away from the threshold adjustment layer 28 on the upper surface of the semiconductor multilayer film 21 .

Further, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the first base layer 14 side. Note that the donor concentration may be controlled using Si as a donor, or may be controlled using carbon as an acceptor that compensates for Si. Alternatively, the drift layer 12 may have a stacked structure of a plurality of nitride semiconductor layers having different impurity concentrations.

Further, for example, the termination portion 3 does not need to include the end surface of the nitride semiconductor device 1. The termination section 3 is a section for separating the transistor section 2 from other devices. Other elements may be arranged in an adjacent region across the terminal end 3 of the transistor section 2. For example, the other element is a pn diode that utilizes a pn junction between the drift layer 12 and the first underlayer 14. Nitride semiconductor device 1 may include a transistor section 2, a termination section 3, and a pn diode.

Further, the first conductivity type may be p type, p ⁺ type, or p ^- type, and the second conductivity type may be n type, n ⁺ type, or n ^- type.

Moreover, various changes, substitutions, additions, omissions, etc. can be made to each of the above embodiments within the scope of the claims or equivalents thereof.

The present disclosure can be used as a nitride semiconductor device with improved off-characteristics, and can be used, for example, in power devices such as power transistors used in power supply circuits of consumer devices such as televisions.

1, 101, 102, 103, 201, 301, 401, 501 Nitride semiconductor device 2 Transistor section 3 Termination section 10 Substrate 10a First main surface 10b Second main surface 12 Drift layer 14 First base layer 16 2 base layer 20, 520 Gate opening 20a, 30a, 40a, 520a Bottom 20b, 30b, 40b, 240b, 520b Side wall 21, 521 Semiconductor multilayer film 22, 522 Electron transit layer 24, 524 Electron supply layer 26 Two-dimensional electron Gas 28 Threshold adjustment layer 30 Source opening 32 Source electrode 34 Gate electrode 36 Drain electrode 40, 240 Groove 42 Interlayer insulation film 43 Contact hole 44 Source wiring 146 Surface protection film 418 High resistance layer 528 Gate insulation film

Claims (8)

A nitride semiconductor device,
A substrate and
a first semiconductor layer of a first conductivity type disposed above the substrate;
a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer;
a third semiconductor layer disposed above the second semiconductor layer;
a first opening that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer;
A semiconductor multilayer film having a channel region of the first conductivity type, a part of which is disposed along the inner surface of the first opening, and another part of which is disposed above the third semiconductor layer. and,
a fourth semiconductor layer of the second conductivity type disposed along the upper surface of the semiconductor multilayer film;
a gate electrode disposed above the fourth semiconductor layer;
a source electrode spaced apart from the gate electrode;
a drain electrode disposed on the lower surface side of the substrate;
a groove provided at a terminal end of the nitride semiconductor device that penetrates the second semiconductor layer and reaches at least the first semiconductor layer;
an interlayer insulating film disposed above the gate electrode;
a source wiring that penetrates the interlayer insulating film and reaches the source electrode,
The end of the interlayer insulating film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. is also located on the outside,
Nitride semiconductor device. a surface protection film disposed above the source wiring;
The end of the surface protective film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. is also located on the outside,
The nitride semiconductor device according to claim 1. The angle between the sidewall of the groove and the top surface of the second semiconductor layer is less than 90 degrees.
The nitride semiconductor device according to claim 1 or 2. The depth of the groove is 1 μm or more, or the groove reaches as far as the substrate.
The nitride semiconductor device according to any one of claims 1 to 3. The interlayer insulating film is one single layer or multilayer film selected from the group consisting of SiN, SiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , AlN, HfON, and ZrON.
The nitride semiconductor device according to any one of claims 1 to 4. comprising a high resistance layer disposed between the first semiconductor layer and the second semiconductor layer;
The nitride semiconductor device according to any one of claims 1 to 5. The nitride semiconductor device according to claim 6, wherein the high resistance layer contains C or Fe. A nitride semiconductor device,
A substrate and
a first semiconductor layer of a first conductivity type disposed above the substrate;
a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer;
a fifth semiconductor layer disposed above the second semiconductor layer;
a sixth semiconductor layer disposed above the fifth semiconductor layer;
a second opening that penetrates the sixth semiconductor layer, the fifth semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer;
a gate insulating film disposed along the inner surface of the second opening, and another portion of which is disposed above the sixth semiconductor layer;
a gate electrode disposed along the upper surface of the gate insulating film;
a source electrode spaced apart from the gate electrode;
a drain electrode disposed on the lower surface side of the substrate;
a groove provided at a terminal end of the nitride semiconductor device that penetrates the second semiconductor layer and reaches at least the first semiconductor layer;
an interlayer insulating film disposed above the gate electrode;
a source wiring that penetrates the interlayer insulating film and reaches the source electrode,
The end of the interlayer insulating film coincides with the end of the groove in plan view, or is within the range of the end of the groove and is closer to the outermost portion of the source electrode. is also located on the outside,
Nitride semiconductor device.

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