JP2008021756A - Group iii nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To crystal-grow an n- or i-type group III nitride semiconductor on the surface of a p-type group III nitride semiconductor, and to expose the surface of the p-type group III nitride semiconductor without etching a part of the n- or i-type group III nitride semiconductor. <P>SOLUTION: An impurity diffusion preventing film 36 is provided on a part of the surface of a first group III nitride semiconductor region 28 containing a p-type impurity. An n-type impurity-containing or i-type second group III nitride semiconductor region 44 is provided on a position where it is opposite to the first group III nitride semiconductor region 28 with the interposition of the preventing film 36. Also, a p-type impurity-containing third group III nitride semiconductor region 30 is provided on a position where it is opposite to the first group III nitride semiconductor region 28 without the interposition of the preventing film 36. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a group III nitride semiconductor used for a high voltage device or a high frequency device.

  In a semiconductor device using a group III nitride semiconductor, a surface of a group III nitride semiconductor containing a p-type impurity (hereinafter sometimes referred to as a p-type group III nitride semiconductor) includes an n-type impurity III. Growing a group nitride semiconductor (hereinafter sometimes referred to as an n-type group III nitride semiconductor) or an i-type group III nitride semiconductor, and etching a part of the n-type or i-type group III nitride semiconductor In some cases, a part of the surface of the p-type group III nitride semiconductor is exposed, and a metal electrode is formed on the exposed surface of the p-type group III nitride semiconductor. Such a semiconductor device is disclosed in Patent Document 1. When the metal electrode is formed on the surface of the p-type group III nitride semiconductor, the potential of the p-type group III nitride semiconductor can be stabilized. As a result, a stable depletion layer can be formed between the p-type group III nitride semiconductor and the n-type or i-type group III nitride semiconductor, and a normally-off characteristic can be realized.

JP 2004-260140 A

In the prior art, when a part of the surface of the p-type group III nitride semiconductor is exposed by etching a part of the n-type or i-type group III nitride semiconductor, the n-type or i-type group III The energy for etching the nitride semiconductor may act on the surface of the p-type group III nitride semiconductor, and the conductivity type of the surface of the p-type group III nitride semiconductor may be reversed to n-type. Even if the metal electrode is formed on the surface of the p-type group III nitride semiconductor whose surface is inverted to n-type, good ohmic contact characteristics cannot be obtained between the p-type group III nitride semiconductor and the metal electrode.
Further, since the p-type group III nitride semiconductor is thin, a part of the surface of the p-type group III nitride semiconductor is exposed by etching a part of the n-type or i-type group III nitride semiconductor. In addition, etching may occur until the p-type group III nitride semiconductor is penetrated. It is difficult to stop etching without exposing the surface of the p-type group III nitride semiconductor and penetrating the p-type group III nitride semiconductor.

Therefore, an n-type or i-type group III nitride semiconductor is crystal-grown on the surface of the p-type group III nitride semiconductor, and a part of the n-type or i-type group III nitride semiconductor is etched without etching. There is a need for a technique for exposing the surface of a type III nitride semiconductor.
The present invention realizes a technique for exposing the surface of the p-type group III nitride semiconductor region without etching the n-type or i-type group III nitride semiconductor crystal grown on the surface. Further, a semiconductor device in which the p-type group III nitride semiconductor region and the metal electrode are well connected is realized.

In group III nitride semiconductors, magnesium is often used as a p-type impurity. Magnesium diffuses easily, so magnesium diffuses into a semiconductor region adjacent to a semiconductor region containing magnesium (a semiconductor region that should not contain magnesium originally), and changes the impurity concentration of the semiconductor region that should not contain magnesium. It has been known. When the impurity concentration in the semiconductor region changes, the semiconductor device may not perform a desired operation. In conventional common sense, measures are taken so that impurities contained in a semiconductor region do not diffuse into other semiconductor regions. For example, a technique is used in which an impurity diffusion prevention film is formed between a semiconductor region containing magnesium and a semiconductor region that should not contain magnesium.
However, in the present invention, the phenomenon that the impurities contained in the p-type group III nitride semiconductor change the impurity concentration of the adjacent semiconductor region is positively utilized. That is, among the semiconductor regions adjacent to the p-type group III nitride semiconductor region, p-type impurities are diffused into a desired semiconductor region, and the conductivity type of the semiconductor region is changed to p-type. On the other hand, a desired operation is realized in the semiconductor device without diffusing p-type impurities in an undesired region. In the present invention, the operation of the semiconductor device is stabilized by utilizing the diffusion phenomenon of impurities which has been a cause of making the operation of the semiconductor device unstable in the prior art.
When magnesium is used as the impurity of the p-type group III nitride semiconductor, the problem of impurity diffusion becomes significant. However, similar problems occur when impurities other than magnesium are used. As semiconductor devices are miniaturized, even if impurities other than magnesium are used, the p-type impurities contained in the semiconductor region diffuse into the adjacent semiconductor region and should not contain magnesium. A phenomenon that changes the density occurs.
The diffusion here is not limited to diffusion in a narrow sense. For example, when a semiconductor crystal that does not contain magnesium is grown on a semiconductor crystal that contains magnesium, magnesium may be incorporated into the semiconductor crystal that should not contain magnesium. Here, this phenomenon is also expressed as a diffusion phenomenon.

  In the semiconductor device of the present invention, an impurity diffusion preventing film covering a part of the surface of the first group III nitride semiconductor region containing the p-type impurity is formed. There are a portion covered with the impurity diffusion preventing film and a portion not covered with the impurity diffusion preventing film on the surface of the first group III nitride semiconductor region. Opposite the first group III nitride semiconductor region through an impurity diffusion prevention film, an n-type impurity or i-type second group III nitride semiconductor region is formed. Further, a third group III nitride semiconductor region is formed which faces the first group III nitride semiconductor region without an impurity diffusion preventing film and contains p-type impurities.

  According to the semiconductor device described above, impurities diffuse from the first group III nitride semiconductor region to the third group III nitride semiconductor region. That is, as for the conductivity type of the third group III nitride semiconductor region, impurities diffuse from the first group III nitride semiconductor region even if the conductivity type when forming the semiconductor region is n-type or i-type. It changes to p type. If the conductivity type of the third group III nitride semiconductor region is p-type, a metal electrode for contacting the first group III nitride semiconductor region is formed on the surface of the third group III nitride semiconductor region can do. The first group III nitride semiconductor region and the metal electrode can be contacted without etching the second group III nitride semiconductor region. Since the etching step can be omitted, the manufacturing cost of the semiconductor device can be reduced. In addition, the impurity diffusion preventing film prevents impurities from diffusing from the first group III nitride semiconductor region to the second group III nitride semiconductor region. Since the impurity concentration of the second group III nitride semiconductor region does not change, the operation of the semiconductor device is stabilized.

In the semiconductor device of the present invention, the third group III nitride semiconductor region is preferably p-type in the entire region from the surface to the first group III nitride semiconductor region.
According to the above semiconductor device, good ohmic contact characteristics can be obtained between the third group III nitride semiconductor and the metal electrode.

The present invention can provide a semiconductor device in which the band gap of the second group III nitride semiconductor region is larger than the band gap of the first group III nitride semiconductor region.
According to the above semiconductor device, the first group III nitride semiconductor region and the second group III nitride semiconductor region form a heterojunction. By forming the heterojunction, a two-dimensional electron gas region is formed between the first group III nitride semiconductor region and the second group III nitride semiconductor region. When the two-dimensional electron gas region is formed, electrons can move. Since a semiconductor device having a heterojunction can be realized with a small number of structures, the manufacturing cost of the semiconductor device can be reduced.

In the present invention, the surface of the second group III nitride semiconductor region has a band gap larger than the band gap of the second group III nitride semiconductor region and contains an n-type impurity or an i-type fourth layer. A semiconductor device in which the group III nitride semiconductor region is formed can be provided.
According to the above semiconductor device, the second group III nitride semiconductor region and the fourth group III nitride semiconductor region form a heterojunction. By forming the heterojunction, a two-dimensional electron gas region is formed between the second group III nitride semiconductor region and the fourth group III nitride semiconductor region. Since the two-dimensional electron gas region is formed in the i-type semiconductor region containing n-type impurities, the electron transfer resistance is reduced, and the on-resistance of the semiconductor device can be reduced.

In the semiconductor device of the present invention, the impurity contained in the first group III nitride semiconductor region is preferably magnesium.
Magnesium has a large diffusion rate. Magnesium contained in the first group III nitride semiconductor region is likely to diffuse into the third group III nitride semiconductor region. The conductivity type of the third group III nitride semiconductor region is likely to change to the p-type.

In the semiconductor device of the present invention, the impurity diffusion preventing film is preferably formed of a group III nitride semiconductor containing aluminum as a part of the composition.
A group III nitride semiconductor whose composition is aluminum is highly effective in preventing diffusion of impurities contained in the semiconductor. It is possible to prevent the impurity from diffusing from the first group III nitride semiconductor region to the second group III nitride semiconductor region. The higher the composition ratio of aluminum, the higher the effect of preventing impurity diffusion. In particular, the aluminum composition ratio is preferably 50% or more.

In a specific embodiment of the present invention, the invention can be embodied in a vertical semiconductor device having a heterojunction.
The semiconductor device includes a drain electrode and a high concentration group III nitride semiconductor layer formed on the surface of the drain electrode and containing an n-type impurity at a high concentration. A low concentration group III nitride semiconductor layer containing an n-type impurity at a low concentration is formed on the surface of the high concentration group III nitride semiconductor layer. A first group III nitride semiconductor region containing a p-type impurity is formed in an island shape on the low concentration group III nitride semiconductor layer. An impurity diffusion preventing film is formed on a part of the surface of the first group III nitride semiconductor region. An n-type impurity-containing or i-type second group III nitride semiconductor region is formed on the surface of the low concentration group III nitride semiconductor layer and the surface of the impurity diffusion prevention film. A third group III nitride semiconductor region containing a p-type impurity is formed in a portion of the surface of the first group III nitride semiconductor region where the impurity diffusion prevention film is not formed. A gate insulating film is formed on the surface side of the second group III nitride semiconductor region facing the first group III nitride semiconductor region. A gate electrode is formed on the surface of the gate insulating film. A source electrode is formed on the surface side of the second group III nitride semiconductor region and the surface of the third group III nitride semiconductor region at positions facing the first group III nitride semiconductor region.

In the vertical semiconductor device having the heterojunction described above, when no voltage is applied to the gate electrode, a depletion layer is formed from the first group III nitride semiconductor region toward the second group III nitride semiconductor region. extend. As a result, a normally-off semiconductor device can be realized.
Here, when the band gap of the second group III nitride semiconductor region is made larger than the band gap of the first group III nitride semiconductor region, the first group III nitride semiconductor region and the second group III nitride are obtained. A heterojunction is formed between the physical semiconductor regions. The gate insulating film is formed on the surface of the second group III nitride semiconductor region. The source electrode is formed on the surface of the second group III nitride semiconductor region and the surface of the third group III nitride semiconductor region.
The surface of the second group III nitride semiconductor region has a band gap larger than the band gap of the second group III nitride semiconductor region and contains an n-type impurity or is an i-type fourth group III nitride A physical semiconductor region may be formed. A heterojunction is formed between the second group III nitride semiconductor region and the fourth group III nitride semiconductor region. In this case, the gate insulating film is formed on the surface of the fourth group III nitride semiconductor region. The source electrode is formed on the surface of the fourth group III nitride semiconductor region and the surface of the third group III nitride semiconductor region.
A heterojunction is formed between the first group III nitride semiconductor region and the second group III nitride semiconductor region, or between the second group III nitride semiconductor region and the fourth group III nitride semiconductor region. As a result, a two-dimensional electron gas layer is formed on the heterojunction surface. When the two-dimensional electron gas layer is formed, electrons can move.

In another specific embodiment of the present invention, a lateral semiconductor device having a heterojunction can be realized.
In the semiconductor device, a first group III nitride semiconductor region containing a p-type impurity is formed in an island shape above an n-type group III nitride semiconductor layer containing an n-type impurity. An impurity diffusion preventing film is formed on a part of the surface of the first group III nitride semiconductor region. An n-type impurity-containing or i-type second group III nitride semiconductor layer is formed on the surface of the n-type group III nitride semiconductor layer and the surface of the impurity diffusion prevention film. A third group III nitride semiconductor region containing a p-type impurity is formed in a portion of the surface of the first group III nitride semiconductor region where the impurity diffusion prevention film is not formed. A gate insulating film is formed on the surface side of the second group III nitride semiconductor region facing the first group III nitride semiconductor region. A gate electrode is formed on the surface of the gate insulating film. A source electrode is formed on the surface side of the second group III nitride semiconductor region and the surface of the third group III nitride semiconductor region at positions facing the first group III nitride semiconductor region. A drain electrode is formed on the surface side of the second group III nitride semiconductor region at a position not facing the first group III nitride semiconductor region.

In the lateral semiconductor device having the heterojunction described above, a depletion layer extends from the first group III nitride semiconductor region toward the second group III nitride semiconductor region when no voltage is applied to the gate electrode. . As a result, a normally-off semiconductor device can be realized.
Here, when the band gap of the second group III nitride semiconductor region is made larger than the band gap of the first group III nitride semiconductor region, the first group III nitride semiconductor region and the second group III nitride are obtained. A heterojunction is formed between the physical semiconductor regions. In this case, the gate insulating film is formed on the surface of the second group III nitride semiconductor region. The source electrode is formed on the surface of the second group III nitride semiconductor region and the surface of the third group III nitride semiconductor region. The drain electrode is formed on the surface of the second group III nitride semiconductor region.
The surface of the second group III nitride semiconductor region has a band gap larger than the band gap of the second group III nitride semiconductor region and contains an n-type impurity or is an i-type fourth group III nitride A physical semiconductor region may be formed. A heterojunction is formed between the second group III nitride semiconductor region and the fourth group III nitride semiconductor region. The gate insulating film is formed on the surface of the fourth group III nitride semiconductor region. The source electrode is formed on the surface of the fourth group III nitride semiconductor region and the surface of the third group III nitride semiconductor region. The drain electrode is formed on the surface of the fourth group III nitride semiconductor region.
A heterojunction is formed between the first group III nitride semiconductor region and the second group III nitride semiconductor region, or between the second group III nitride semiconductor region and the fourth group III nitride semiconductor region. As a result, a two-dimensional electron gas layer is formed on the heterojunction surface. When the two-dimensional electron gas layer is formed, electrons can move.

  According to the present invention, it is possible to provide a semiconductor device in which good ohmic characteristics are ensured between the surface of the p-type group III nitride semiconductor region and the metal electrode.

The main features of the examples are listed.
First Embodiment A plurality of p ⁺ -type group III nitride semiconductor regions 28 are formed in an island shape on the surface of an n ⁻ -type group III nitride semiconductor layer 26.
Second Embodiment An n ⁻ type group III nitride semiconductor region 44 is formed at a position facing the p ⁺ type group III nitride semiconductor region 28 via the impurity diffusion prevention film 36.
(Third Embodiment) n ^- on the surface of the mold of the group III nitride semiconductor region 44, n ^- -type i-type group III nitride semiconductor having a larger band gap than the band gap of the III nitride semiconductor region 44 of the Region 38 is formed.
(Fourth Embodiment) n ^- -type III nitride semiconductor region 44 and the n ^- -type III-end portions of the nitride semiconductor region 38 of, n ⁺ -type III nitride semiconductor region 32 is formed .
Fifth Embodiment A source electrode 34 connected to both the n ⁺ type group III nitride semiconductor region 32 and the p type group III semiconductor region 30 is formed.
Sixth Embodiment A gate electrode 40 is formed on the surface of the group III nitride semiconductor region 38 with a gate insulating film 42 interposed therebetween. The gate electrode 40 is formed at a position facing at least the p ⁺ -type group III nitride semiconductor region 28.

Embodiments will be described in detail below with reference to the drawings.
(First embodiment)
FIG. 1 schematically shows a cross-sectional view of an essential part of a vertical group III nitride semiconductor device 10 having a heterojunction. FIG. 1 shows a unit structure of the semiconductor device 10, and this unit structure is actually repeated in the left-right direction on the paper.
A drain electrode 22 in which titanium (Ti) and aluminum (Al) are stacked is formed on the back surface of the semiconductor device 10. On the surface of the drain electrode 22, an n ⁺ -type group III nitride semiconductor layer 24 mainly composed of gallium nitride (GaN) is formed. Silicon (Si) or oxygen (O) is used as an impurity of the group III nitride semiconductor layer 24, and its carrier concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ .
On the surface of the group III nitride semiconductor layer 24, an n ⁻ type low concentration group III nitride semiconductor layer 26 mainly composed of gallium nitride is formed. Silicon is used as an impurity of the group III nitride semiconductor layer 26, and its carrier concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ .
A p ⁺ -type group III nitride semiconductor region (first group III nitride semiconductor region) 28 mainly composed of gallium nitride is formed in an island shape on the group III nitride semiconductor layer 26. Yes. Magnesium (Mg) is used as an impurity in the group III nitride semiconductor region 28, and its carrier concentration is adjusted to about 1 × 10 ¹⁸ cm ⁻³ . A plurality of group III nitride semiconductor regions 28 are formed dispersedly on the group III nitride semiconductor layer 26, and the group III nitride semiconductor layer 26 provides a gap between adjacent group III nitride semiconductor regions 28. It is separated. As shown in FIG. 1, in this embodiment, two group III nitride semiconductor regions 28 are formed on the left and right sides of the paper. When viewed in plan, the group III nitride semiconductor region 28 extends long in the depth direction of the drawing, and a plurality of group III nitride semiconductor regions 28 are arranged in a stripe pattern.

On part of the surface of the group III nitride semiconductor region 28, an impurity diffusion prevention film 36 containing aluminum nitride (AlN) as a main material is formed. As will be described later, the impurity diffusion prevention film 36 is not formed in a portion where the source electrode 34 is in electrical contact with the group III nitride semiconductor region 28 via the p ⁺ type group III nitride semiconductor region 30. In addition to aluminum nitride, a group III nitride semiconductor, silicon nitride (SiN), or silicon oxide (SiO ₂ ) containing aluminum as a part can be used as the impurity diffusion preventing film 36. Furthermore, a composite film of silicon nitride and silicon oxide can be used. The impurity diffusion preventing film 36 may be any material that does not diffuse the p-type impurity contained in the group III nitride semiconductor region 28 into the group III nitride semiconductor region 44 or the group III nitride semiconductor region 38 described later. .
An n ⁻ -type group III nitride semiconductor region (second group III nitride semiconductor region) 44 mainly composed of gallium nitride is formed on the surface of the group III nitride semiconductor layer 26. The group III nitride semiconductor region 44 is also formed on the surface of the impurity diffusion preventing film 36. That is, the group III nitride semiconductor region 44 is formed so as to face the group III nitride semiconductor region 28 with the impurity diffusion prevention film 36 interposed therebetween. Silicon (Si) is used as an impurity in the group III nitride semiconductor region 44, and its carrier concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ .
An i-type group III nitride semiconductor region mainly composed of gallium nitride / aluminum (Al _0.3 Ga _0.7 N) on the group III nitride semiconductor region 44 (fourth group III nitride semiconductor region) 38 is formed. The crystal structure of group III nitride semiconductor region 38 includes aluminum, and group III nitride semiconductor region 38 has a larger band gap than the band gap of group III nitride semiconductor region 44. The group III nitride semiconductor region 44 and the group III nitride semiconductor region 38 form a heterojunction. Impurities are not introduced into the group III nitride semiconductor region 38.

An n ⁺ -type source region 32 containing gallium nitride as a main material is formed at both ends of the group III nitride semiconductor region 44 and the group III nitride semiconductor region 38 in the horizontal direction of the drawing. The source region 32 has a group III nitride semiconductor region 44 and a group III nitride semiconductor in a range where the low concentration group III nitride semiconductor layer 26 is in contact with the group III nitride semiconductor region 44 (center side in the drawing) when viewed in plan. It does not touch the region 38. Silicon is used as an impurity in the source region 32, and its carrier concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ .
A p-type group III nitride semiconductor region (third group III nitride semiconductor region) 30 is formed in a portion of the surface of group III nitride semiconductor region 28 where impurity diffusion prevention film 36 is not formed. The group III nitride semiconductor region 30 has a group III nitride formed by diffusing impurities (magnesium in this embodiment) of the group III nitride semiconductor region 28 into the group III nitride semiconductor region 44 and the group III nitride semiconductor region 38. This is a region in which part of the semiconductor semiconductor region 44 and part of the group III nitride semiconductor region 38 are p-type.

  On the surface of the group III nitride semiconductor region 38, a gate insulating film 42 which is a silicon oxide main material is formed. A gate electrode 40 made mainly of nickel (Ni) is formed on the surface of the gate insulating film 42. In this embodiment, the gate insulating film 42 and the gate electrode 40 are formed so as to face almost the entire range of the group III nitride semiconductor region 44 and the group III nitride semiconductor region 38. The gate electrode 40 only needs to be formed at a position facing the group III nitride semiconductor region 28. In other words, it only needs to be formed at a portion where the central edge of the source region 32 and the central edge of the group III nitride semiconductor region 28 overlap.

  A source electrode 34 made of a laminate of titanium and aluminum is formed on the surface of the source region 32 and the group III nitride semiconductor region 30. The source electrode 34 is electrically connected to the group III nitride semiconductor region 28 via the group III nitride semiconductor region 30.

Next, the operation of the semiconductor device 10 will be described.
The p-type group III nitride semiconductor region 28 is in contact with the n-type group III nitride semiconductor region 44 through the impurity diffusion prevention film 36. In a state where no voltage is applied to the gate electrode 40, a depletion layer is formed up to the region 38 a of the group III nitride semiconductor region 38. That is, the depletion layer extends to the heterojunction surface of the group III nitride semiconductor region 44 and the group III nitride semiconductor region 38. The energy level of the conduction band of the heterojunction surface exists above the Fermi level, and the two-dimensional electron gas layer cannot exist on the heterojunction surface. That is, in a state where no voltage is applied to the gate electrode 40, the traveling of electrons is stopped, and the semiconductor device 10 is turned off. The semiconductor device 10 performs a normally-off operation.

In a state where a positive voltage is applied to the gate electrode 40, the depletion layer formed up to the region 38a of the group III nitride semiconductor region 38 disappears, and the group III nitride semiconductor region 44 and the group III nitride semiconductor region are lost. A two-dimensional electron gas layer is formed on the 38 heterojunction surfaces. Therefore, the energy level of the conduction band of the two-dimensional electron gas layer exists below the Fermi level, and a state in which the two-dimensional electron gas layer exists in the potential well of the heterojunction plane is created. As a result, electrons run in the two-dimensional electron gas layer, and the semiconductor device 10 is turned on.
The electrons that have traveled laterally along the two-dimensional electron gas layer at the heterojunction surface of the group III nitride semiconductor region 44 and the group III nitride semiconductor region 38 from the source region 32 are transferred to the low concentration group III nitride semiconductor layer 26 In the vertical direction (portion where the low concentration group III nitride semiconductor layer 26 is in contact with the group III nitride semiconductor region 44), and the drain electrode via the low concentration group III nitride semiconductor layer 26 and the drain region 24 It flows to 22. The source electrode 34 and the drain electrode 22 are electrically connected.

  As described above, on / off control of the semiconductor device 10 is performed by stacking the group III nitride semiconductor region 28, the impurity diffusion preventing film 36, the group III nitride semiconductor region 44, and the group III nitride semiconductor region 38. It is done in the part. In other words, by controlling the thickness of the depletion layer formed in the group III nitride semiconductor region 44 by the voltage applied to the gate electrode 40, the semiconductor device 10 is controlled to be turned on / off. Since the source electrode 34 and the group III nitride semiconductor region 30 exhibit good ohmic characteristics, the semiconductor device 10 is reliably turned on by applying a predetermined gate voltage that stabilizes the potential of the group III nitride semiconductor region 28. If the gate voltage is not applied, the semiconductor device 10 is reliably turned off.

(Second embodiment)
The present invention can also be embodied in a horizontal semiconductor device. FIG. 2 is a cross-sectional view of the main part of the semiconductor device 100. In the semiconductor device 100, an n ⁻ type group III nitride semiconductor layer 126 is formed on the surface of a substrate 148 made of sapphire (Al ₂ O ₃ ). A p ⁺ type group III nitride semiconductor region 128 is formed in an island shape in a partial region of the n ⁻ type group III nitride semiconductor layer 126. Magnesium is used as an impurity in the group III nitride semiconductor region 128. An impurity diffusion preventing film 136 is formed on a part of the surface of group III nitride semiconductor region 128. A group III nitride semiconductor region 130 is formed in a region of the group III nitride semiconductor region 128 where the impurity diffusion prevention film 136 is not formed. A group III nitride semiconductor region 144 is formed over a portion of the group III nitride semiconductor layer 126 where the group III nitride semiconductor region 128 is not formed from the impurity diffusion preventing film 136. A group III nitride semiconductor region 138 having a band gap larger than that of the group III nitride semiconductor region 144 is formed on the surface of the group III nitride semiconductor region 144. A gate insulating film 142 is formed on the surface of the group III nitride semiconductor region 138. A group III nitride semiconductor region 142 and a group III nitride semiconductor region in which an n ⁺ -type source region 132 is formed at the left end of the group III nitride semiconductor region 142 and the group III nitride semiconductor region 138 in the drawing. An n ⁺ -type drain region 146 is formed at the end of the right side of the sheet 138. A group III nitride semiconductor region 130 is formed on the surface of the group III nitride semiconductor region 128 where the impurity diffusion prevention film 136 is not formed.

In a state where a positive voltage is not applied to the gate electrode 140, a depletion layer extends from the group III nitride semiconductor region 128 and the group III nitride semiconductor region 144, and the region 138a is depleted. In the state where no voltage is applied to the gate electrode 140, the electron travel is stopped, and the semiconductor device 100 is turned off. The semiconductor device 100 performs a normally-off operation.
On the other hand, when a positive voltage is applied to gate electrode 140, the depletion layer formed in group III nitride semiconductor region 138a disappears, and group III nitride semiconductor region 144 and group III nitride semiconductor region 138 are lost. A two-dimensional electron gas layer is formed on the heterojunction surface. Electrons travel in the two-dimensional electron gas layer, and the semiconductor device 100 is turned on.

(Third embodiment)
A semiconductor device 200 of the present invention will be described with reference to FIG. In addition, about the structure substantially the same as 1st Example, the same reference number is attached and description is abbreviate | omitted. The semiconductor device 200 is different from the semiconductor device 10 of the first embodiment in that n is larger in band gap than the group III nitride semiconductor region 28 instead of the group III nitride semiconductor region 44 and the group III nitride semiconductor region 38. ^{A −} type group III nitride semiconductor region 244 is formed. The group III nitride semiconductor region 28 and the group III nitride semiconductor region 244 form a heterojunction. In FIG. 3, an impurity diffusion preventing film 36 is formed between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 244. However, since the impurity diffusion preventing film 36 is an extremely thin film, a heterojunction is formed between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 244. By forming a heterojunction between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 38, the group III nitride semiconductor region 28 and the group III are not applied to the gate electrode 40. A depletion layer extends from the heterojunction surface of nitride semiconductor region 244 toward group III nitride semiconductor region 244. That is, in a state where no voltage is applied to the gate electrode 40, a depletion layer is formed in the region 244a of the group III nitride semiconductor region 244. The energy level of the conduction band of the heterojunction surface exists above the Fermi level, and the two-dimensional electron gas layer cannot exist on the heterojunction surface. That is, in a state where no voltage is applied to the gate electrode 40, the traveling of electrons is stopped, and the semiconductor device 200 is turned off. The semiconductor device 200 performs normally-off operation.
On the other hand, when a positive voltage is applied to the gate electrode 40, the depletion layer formed in the region 244a of the group III nitride semiconductor region 244 disappears, and the group III nitride semiconductor region 28 and the group III nitride are lost. A two-dimensional electron gas layer is formed on the heterojunction surface of the semiconductor region 244. Therefore, the energy level of the conduction band of the two-dimensional electron gas layer exists below the femil level, and a state where a two-dimensional electron gas layer exists in the potential well of the heterojunction surface is created. The As a result, electrons run in the two-dimensional electron gas layer, and the semiconductor device 200 is turned on.

(Fourth embodiment)
A semiconductor device 300 of the present invention will be described with reference to FIG. In addition, about the structure substantially the same as 1st Example and 3rd Example, the same reference number is attached | subjected and description is abbreviate | omitted. The semiconductor device 300 is different from the semiconductor device 10 of the first embodiment in that n ⁻ having the same band gap as the group III nitride semiconductor region 28 instead of the group III nitride semiconductor region 44 and the group III nitride semiconductor region 38. A type III nitride semiconductor region 344 is formed. In FIG. 4, an impurity diffusion prevention film 36 is formed between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 344. In a state where no voltage is applied to the gate electrode 40, a depletion layer extends from the junction surface between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 344 toward the group III nitride semiconductor region 344. That is, in a state where no voltage is applied to the gate electrode 40, a depletion layer is formed in the region 344a of the group III nitride semiconductor region 344. Therefore, there is no carrier that can contribute to the current in group III nitride semiconductor region 344. That is, in a state where no voltage is applied to the gate electrode 40, the traveling of electrons is stopped, and the semiconductor device 300 is turned off. The semiconductor device 300 performs normally-off operation.
On the other hand, in a state where a positive voltage is applied to the gate electrode 40, the depletion layer formed in the region 344a of the group III nitride semiconductor region 344 disappears, and current flows in the group III nitride semiconductor region 344. There are carriers that can contribute. As a result, electrons as carriers travel in the group III nitride semiconductor region 344, and the semiconductor device 300 is turned on.

(Experimental example)
FIG. 5 shows the result of measuring the magnesium concentration in the group III nitride semiconductor region 30 of the semiconductor device 10 by SIMS (Secondary ion mass spectrometry). The vertical axis of FIG. 4 indicates the magnesium concentration (unit: cm ⁻³ ), and the horizontal axis indicates the distance (unit: nm) from the surface of the group III nitride semiconductor region 30. A dotted line 62 in the figure indicates the boundary between the group III nitride semiconductor region 30 and the group III nitride semiconductor region 28. That is, the left side of the dotted line 62 in the drawing shows the semiconductor region 30, and the right side of the dotted line 62 in the drawing shows the group III nitride semiconductor region 28.
As is apparent from the curve 60, the magnesium concentration is high near the surface of the group III nitride semiconductor region 30 and decreases as the distance from the surface of the group III nitride semiconductor region 30 increases. The magnesium concentration once lowered increases as it approaches the group III nitride semiconductor region 28. A dotted line 64 in the figure indicates a magnesium concentration of 3 × 10 ¹⁸ cm ⁻³ . Here, the magnesium concentration of the group III nitride semiconductor region 30 is 3 × 10 ¹⁸ cm ⁻³ or more even at the lowest magnesium concentration. The n ^- type group III nitride semiconductor region 44 has an n-type impurity concentration of about 1 × 10 ¹⁶ cm ⁻³ . Here, even if it is assumed that the activation rate of magnesium is 1% and the activation rate of the n-type impurity in the group III nitride semiconductor region 44 is 100%, the conductivity type of the group III nitride semiconductor region 30 is a semiconductor. It becomes p-type over the entire region. Further, as a result of this experiment, it has been found that the magnesium concentration near the surface of the group III nitride semiconductor region 30 is higher than the magnesium concentration outside the surface of the group III nitride semiconductor region 30. This cannot be explained by the narrow diffusion phenomenon. In the present invention, the shift of magnesium in the group III nitride semiconductor region 28 to the group III semiconductor region 30 through some process is referred to as diffusion. Since the magnesium concentration in the portion of the group III nitride semiconductor region 30 that contacts the source electrode 34 is high, the contact resistance between the group III nitride semiconductor region 30 and the source electrode 34 is reduced. That is, good ohmic contact characteristics can be obtained between the group III nitride semiconductor region 30 and the source electrode 34.

Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, in the above embodiment, the n-type low-concentration group III nitride semiconductor region is formed on the surface of the p-type group III nitride semiconductor region, but instead of the n-type group III nitride semiconductor region. An i-type group III nitride semiconductor region may be formed.
Further, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of purposes at the same time, and has technical utility by achieving one of the purposes.

1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. Sectional drawing of the principal part of the semiconductor device of 2nd Example is shown. Sectional drawing of the principal part of the semiconductor device of 3rd Example is shown. Sectional drawing of the principal part of the semiconductor device of 4th Example is shown. In the semiconductor region in which magnesium is diffused, the relationship between the distance from the surface of the semiconductor region and the magnesium concentration is shown.

Explanation of symbols

22, 122: drain electrode 24, 146: n ⁺ -type drain region 26, 126: n ⁻ -type low concentration group III nitride semiconductor layer 28, 128: first group III nitride semiconductor region 30, 130, 230 , 330: third group III nitride semiconductor region 32, 132, 232, 332: source region 34, 134: source electrode 36, 136: impurity diffusion prevention layer 38: fourth group III nitride semiconductor region 40, 140 : Gate electrodes 42, 142: Gate insulating films 44, 144, 244, 344: Second group III nitride semiconductor region

Claims (9)

a first group III nitride semiconductor region containing p-type impurities;
An impurity diffusion preventing film covering a part of the surface of the first group III nitride semiconductor region;
An n-type impurity or i-type second group III nitride semiconductor region facing the first group III nitride semiconductor region via an impurity diffusion prevention film and
A third group III nitride semiconductor region facing the first group III nitride semiconductor region without an impurity diffusion preventing film and containing a p-type impurity;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the third group III nitride semiconductor region is p-type in the entire region from the surface to the first group III nitride semiconductor region.   3. The semiconductor device according to claim 1, wherein the band gap of the second group III nitride semiconductor region is larger than the band gap of the first group III nitride semiconductor region.   The surface of the second group III nitride semiconductor region has a band gap larger than the band gap of the second group III nitride semiconductor region and contains an n-type impurity or is an i-type fourth group III nitride 3. The semiconductor device according to claim 1, wherein a physical semiconductor region is formed.   The semiconductor device according to claim 1, wherein the impurity contained in the first group III nitride semiconductor region is magnesium.   6. The semiconductor device according to claim 1, wherein the impurity diffusion preventing film is formed of a group III nitride semiconductor containing aluminum as a part of the composition. A drain electrode;
A high-concentration group III nitride semiconductor layer formed on the surface of the drain electrode and containing a high concentration of n-type impurities;
A low concentration group III nitride semiconductor layer formed on the surface of the high concentration group III nitride semiconductor layer and containing an n-type impurity at a low concentration;
A first group III nitride semiconductor region formed in an island shape on the low concentration group III nitride semiconductor layer and containing p-type impurities;
An impurity diffusion preventing film formed on a part of the surface of the first group III nitride semiconductor region;
An n-type impurity or i-type second group III nitride semiconductor region formed on the surface of the low concentration group III nitride semiconductor layer and the surface of the impurity diffusion preventing film;
A third group III nitride semiconductor region formed on a portion of the surface of the first group III nitride semiconductor region where the impurity diffusion prevention film is not formed and containing a p-type impurity;
A gate insulating film formed on the surface side of the second group III nitride semiconductor region facing the first group III nitride semiconductor region;
A gate electrode formed on the surface of the gate insulating film;
A source electrode formed on the surface side of the second group III nitride semiconductor region and the surface of the third group III nitride semiconductor region at a position facing the first group III nitride semiconductor region;
A semiconductor device comprising: an n-type group III nitride semiconductor layer containing an n-type impurity;
a first group III nitride semiconductor region formed in an island shape on the n-type group III nitride semiconductor layer and containing p-type impurities;
An impurity diffusion preventing film formed on a part of the surface of the first group III nitride semiconductor region;
an n-type group III nitride semiconductor region formed on the surface of the n-type group III nitride semiconductor layer and the surface of the impurity diffusion prevention film and containing an n-type impurity or an i-type second group III nitride semiconductor region;
A third group III nitride semiconductor region formed on a portion of the surface of the first group III nitride semiconductor region where the impurity diffusion prevention film is not formed and containing a p-type impurity;
A gate insulating film formed on the surface side of the second group III nitride semiconductor region facing the first group III nitride semiconductor region;
A gate electrode formed on the surface of the gate insulating film;
A source electrode formed on the surface side of the second group III nitride semiconductor region and the surface of the third group III nitride semiconductor region at a position facing the first group III nitride semiconductor region;
A drain electrode formed on the surface side of the second group III nitride semiconductor region at a position not facing the first group III nitride semiconductor region;
A semiconductor device comprising: The surface of the second group III nitride semiconductor region has a band gap larger than the band gap of the second group III nitride semiconductor region and contains an n-type impurity or is an i-type fourth group III nitride A semiconductor region is formed,
9. The semiconductor device according to claim 7, wherein a gate insulating film is formed on a surface of the fourth group III nitride semiconductor region.

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