CN109560120B - GaN normally-off MISFET device with vertical grooves grown in selective area and manufacturing method thereof - Google Patents
GaN normally-off MISFET device with vertical grooves grown in selective area and manufacturing method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention relates to a GaN normally-closed MISFET device with vertical grooves grown in a selected region and a manufacturing method thereof, which comprises a conductive GaN substrate and an epitaxial layer, wherein the epitaxial layer comprises an n-type lightly-doped GaN layer, an intrinsic GaN layer and a secondary epitaxial layer grown on the n-type lightly-doped GaN layer and the selected region, the secondary epitaxial layer is an electron blocking layer and a low-voltage GaN layer from bottom to top, the non-doping epitaxial GaN layer and the heterostructure barrier layer form a groove channel after secondary epitaxial growth, insulating layers cover the surfaces of the groove channel and the heterostructure barrier layer, a grid electrode covers the groove channel on the insulating layers, source electrode areas are formed by etching two ends of the insulating layers, the source electrode areas are etched to the p-type barrier layer to form base area areas, ohmic metal is evaporated at the base area to form a short circuit effect with the source electrode, the ohmic metal is evaporated at the source electrode areas to form a source electrode in contact with the heterostructure barrier layer, and drain electrode ohmic contact metal is arranged on the back of the conductive GaN substrate. The invention improves the switching control capability of the device, reduces the on-resistance of the device and improves the reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a GaN normally-off MISFET device with a vertical groove grown in a selected region and a manufacturing method thereof.
Background
The GaN semiconductor material has the advantages of large forbidden bandwidth, high breakdown electric field, large saturated electron drift velocity, high thermal conductivity and the like, and two-dimensional electron gas (2 DEG) with high concentration and high electron mobility exists on a heterojunction interface, so that the GaN semiconductor material is more suitable for preparing power electronic devices with high power, large capacity and high switching speed compared with Si material, and becomes an ideal substitute of the next generation of power switching devices.
The GaN power switch device is divided into a transverse conducting device and a longitudinal conducting device from the view point of device structure. The transverse conduction device directly utilizes the AlGaN/GaN heterojunction 2DEG channel as a device conduction channel, an active region of the transverse conduction device is concentrated on the surface of an epitaxial layer of the device, and a source electrode, a grid electrode and a drain electrode of the device are all designed on the same plane of the device. The design structure is a commonly used device structure of the GaN-based HFET device at present, and the device can realize low on resistance and high switching frequency under low voltage. However, in a high-voltage working environment, the GaN device is transversely conducted, and the GaN device has great problems, such as that firstly, an electric field edge concentration effect is easily formed at the edge of a grid electrode, and the GaN device is easily broken down; besides, due to the effects of ionization of defect states on the surface of the heterostructure barrier layer, ionization of acceptor traps in the GaN epitaxial layer and the like, current collapse of the device can be caused, and the performance of the device is deteriorated. Longitudinally conducting devices have significant advantages over lateral devices: firstly, a source electrode is positioned on the heterojunction barrier layer, a drain electrode is positioned below the conductive substrate, and a longitudinal conductive channel is controlled by utilizing a grid electrode, so that the power of a chip in unit area is improved, and the utilization efficiency of the chip is increased; the current is longitudinally distributed in the device, so that the electric field is distributed more uniformly, and the breakdown voltage of the device is effectively improved; thirdly, the high field area is in the material and far away from the surface, so that the influence of the surface state can be weakened and the current collapse effect can be relieved; therefore, the longitudinally conducted GaN switch device is more suitable for being applied to the working environment with high power and high voltage.
At present, the longitudinal conduction structure MISFET based on the AlGaN/GaN heterojunction and the insulated gate structure can realize the characteristics of low on-resistance, high voltage, large on-current and the like. The current mainstream structures are three, namely Fin FET, electron hole type and groove type. Among them, the electron hole structure has the advantage of high channel mobility, but often faces the problem of diffusion of electron blocking layer (p-GaN) Mg and the problem of difficulty in realizing normally-off operation. The Fin FET can effectively realize normally-off devices when Mg doped p-GaN is not introduced, but the problems of low channel mobility caused by the structure voltage endurance and etching are urgently needed to be solved. The groove structure can realize high voltage resistance through the thick drift layer and is a normally-off device, and the groove structure is a potential scheme for realizing a vertical power device. But still face the following problems: the trench etch damage results in low channel mobility. Electron blocking layer Mg diffusion problem. The Selective Area Growth (SAG) method forms a U-shaped groove gate structure in a secondary epitaxial growth mode, so that groove etching damage can be avoided, and great progress is made in the preparation of a high-performance transverse conduction normally-off GaN field effect transistor. However, the following problems are encountered in the fabrication of vertical devices using this scheme: secondary growth interface defect, electron barrier layer Mg diffusion.
Disclosure of Invention
The invention provides a GaN normally-off MISFET device with a vertical groove grown in a selected region and a manufacturing method thereof, aiming at overcoming at least one defect in the prior art, and the manufactured device has the advantages of low on-resistance, high threshold voltage, high switching control capability and stable and reliable performance.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a GaN normally-closed MISFET device with vertical grooves grown in a selective area comprises a grid electrode, a source electrode, a drain electrode, an insulating layer, a conductive GaN substrate and an epitaxial layer on the grid electrode, wherein the epitaxial layer comprises an n-type lightly-doped GaN layer and an intrinsic GaN layer which are epitaxially grown for the first time and a secondary epitaxial layer on the conductive GaN substrate and grown in the selective area, the secondary epitaxial layer comprises an electron blocking layer, a low-voltage GaN layer, a non-doped GaN layer and a heterostructure barrier layer from bottom to top, a groove channel is formed after secondary epitaxial growth, the surfaces of the groove channel and the heterostructure barrier layer are covered with the insulating layer, source electrode areas are formed by etching the two ends of the insulating layer at the groove channel on the grid electrode insulating layer, the source electrode areas are etched to the electron blocking layer to form base area, ohmic metal is evaporated at the base area to form short circuit with the source electrode, and the source electrode areas are evaporated with ohmic metal to form a source electrode in contact with the heterostructure barrier layer, and the drain electrode ohmic contact metal is arranged on the back surface of the conductive GaN substrate.
The invention improves the problem of low electron mobility of the electron blocking layer in the prior art scheme, and repairs two interfaces: the electron blocking layer and the secondary growth interface, and the electron blocking layer and the channel interface. The growth of a high-quality electron blocking layer is realized by improving a secondary epitaxial interface through the primary epitaxial growth of the low-doping-concentration intrinsic GaN layer, so that the switching control capability of the device is improved. A low-voltage GaN layer grows on the current blocking layer and the upper heterojunction channel interface, so that high-temperature diffusion of Mg is effectively inhibited, the surface of p-GaN can be improved, and the electron mobility of the heterojunction channel is improved.
Furthermore, the groove is in a V-shaped or U-shaped structure.
Further, the conductive GaN substrate is a heavily doped GaN substrate, and the conductive GaN substrate can also be composed of a low-resistance silicon substrate or low-resistance silicon carbide and a conductive buffer layer; the heavily doped GaN substrate has a doping concentration of 10 18 Above, in thisThe lower value is light doping; the thickness of the n-type lightly doped GaN layer is 1-50 μm.
Furthermore, an n-type heavily doped GaN layer is arranged between the n-type lightly doped GaN layer and the secondary epitaxial layer, and the thickness of the n-type heavily doped GaN layer is 10-100 nm.
Furthermore, the low-pressure GaN layer is made of low-pressure GaN and the thickness of the low-pressure GaN layer is 1-500 nm.
Further, the electron blocking layer is made of a p-type doped GaN layer or a doped high-resistance GaN layer, or a p-type doped AlGaN layer or a doped high-resistance AlGaN layer, the doping elements of the doped high-resistance GaN layer and the doped AlGaN layer include, but are not limited to, carbon or iron, and the thickness of the electron blocking layer is 10-500 nm; the thickness of the non-doped GaN layer is 10-500 nm;
further, an AlN layer is grown between the non-doped GaN layer and the heterostructure barrier layer, and the thickness of the AlN layer is 1-10 nm.
Further, the heterostructure barrier layer material includes but is not limited to one or a combination of any several of AlGaN, AlInN, InGaN, AlInGaN, AlN, and the heterostructure barrier layer has a thickness of 5-50 nm.
Further, the insulating layer material includes, but is not limited to, SiO 2 、SiN x 、Al 2 O 3 、AlN、HfO 2 、MgO、Sc 2 O 3 、Ga 2 O 3 、AlHfO x Or HfSiON or the stacking combination of any several of HfSiON, wherein the thickness of the insulating layer is 1-100 nm; the source electrode and the drain electrode materials comprise but are not limited to Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy, and other various metals or alloys capable of realizing ohmic contact can be used as the source electrode and the drain electrode materials; the gate material includes, but is not limited to, Ni/Au alloy, Pt/Al alloy or Pd/Au alloy, and various other metals or alloys capable of achieving high threshold voltage can be used as the gate material.
The invention also provides a GaN normally-off MISFET device with a vertical groove grown in a selective area, which comprises the following steps:
s1, carrying out primary epitaxial growth on the n-type lightly doped GaN layer on the conductive GaN substrate; an intrinsic GaN layer;
s2 growing a layer of SiO on the intrinsic GaN layer 2 A layer as a mask layer;
s3, reserving a mask layer on the grid electrode forming area through a photoetching method;
s4, secondary epitaxial growth of an electronic barrier layer, a low-voltage GaN layer, a non-doped GaN layer and a heterostructure barrier layer is carried out on the selected region to form a groove grid;
s5, removing the mask layer above the grid region;
s6, depositing an insulating layer of the grid electrode on the heterojunction barrier layer and the groove part;
s7, completing device isolation by dry etching, and etching a base ohmic contact region on the insulating layer; and depositing a base ohmic contact metal on the base region
S8, etching a source ohmic contact area on the insulating layer;
s9, evaporating source ohmic contact metal on the source region, and evaporating drain ohmic contact metal on the back of the conductive GaN substrate;
and S10, evaporating a gate metal in the gate region on the insulating layer at the groove.
Further, the growth method of the n-type lightly doped GaN layer and the intrinsic GaN layer in the step S1 and the electron blocking layer, the low-pressure GaN layer, the undoped GaN layer and the heterostructure barrier layer in the step S4 is metal organic chemical vapor deposition or molecular beam epitaxy;
further, the mask layer in step S2 and the insulating layer in step S5 are grown by a plasma enhanced chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method, or a magnetron sputtering method.
Compared with the prior art, the beneficial effects are: the device adopts a secondary epitaxial growth technology, an electronic barrier layer, a low-voltage GaN layer, a non-doped GaN layer and a heterojunction barrier layer are secondarily epitaxially grown on an n-type lightly-doped GaN layer and an intrinsic GaN layer, the low-voltage GaN layer is utilized, the channel mobility is effectively improved, the side wall of a channel is grown in situ through secondary epitaxy, the interface quality of a p-type layer and an mis interface and the interface quality of a p-type heterojunction above the p-type layer and the p-type heterojunction are protected, the current leakage problem of the current barrier layer is reduced, meanwhile, the secondary growth interface state problem is completely reduced by adopting a primary grown intrinsic GaN layer, the influence of background doping during secondary growth is overcome, the threshold voltage stability of the device is improved together through the improvements, and the current leakage problem of each electrode is reduced.
Drawings
Fig. 1 to 9 are schematic process diagrams of a device manufacturing method according to embodiment 1 of the present invention;
FIG. 10 is a schematic view of the device structure of example 2 of the present invention;
FIG. 11 is a schematic view of the device structure of embodiment 3 of the present invention;
FIG. 12 is a structural diagram of a secondary epitaxy SEM according to the present invention.
Detailed Description
The drawings are for illustration purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.
The experimental group has verified the appearance of the cross section in the related research work of secondary epitaxial growth of GaN: as shown in fig. 12, which is a structure diagram of a secondary epitaxy SEM, it is evident from fig. 12 that the secondary epitaxy includes a sidewall with an angle of 60 ° and the distribution of each layer on the sidewall, which also shows from the side that a channel layer and a heterojunction grown thereon can be grown in situ through secondary growth, and it is expected that the beneficial properties of reducing the channel resistance and improving the stability of the threshold voltage can be expected.
Example 1
As shown in fig. 9, which is a schematic structural diagram of the device of this embodiment, the device includes a gate, a source, a drain, an insulating layer 11, a conductive GaN substrate 1 and an epitaxial layer thereon, the epitaxial layer includes a primary epitaxially grown n-type lightly doped GaN layer 2, an intrinsic GaN layer 3 and a secondary epitaxial layer grown on a selective region thereon, the secondary epitaxial layer includes, from bottom to top, an electron blocking layer 4, a low voltage GaN layer 5, a non-doped GaN layer 6 and a heterostructure barrier layer 7, a trench channel is formed after the secondary epitaxial growth, the surface of the trench channel and the heterostructure barrier layer 7 covers the insulating layer 11, the gate covers the trench channel on the insulating layer 11, source regions are formed by etching two ends of the insulating layer 11, the source regions are etched to the electron blocking layer 4 to form base regions, ohmic metal 9 is deposited on the base regions to form a short-connection effect with the source, ohmic metal 8 is deposited on the source regions to form a source in contact with the heterostructure barrier layer, a drain ohmic contact metal 10 is disposed on the back surface of the conductive GaN substrate 1.
Specifically, the groove channel is U-shaped, and the conductive GaN substrate 1 is a heavily doped GaN substrate.
Wherein the thickness of the n-type lightly doped GaN layer 2 is 1-50 μm; an intrinsic GaN layer 3 is also arranged between the n-type lightly doped GaN layer 2 and the secondary epitaxial layer, and the thickness of the intrinsic GaN layer is 10-100 nm. The low-pressure GaN layer 5 is made of low-pressure GaN and has the thickness of 1-500 nm; the electron barrier layer 4 is made of a p-type doped GaN layer or a p-type doped AlGaN layer; the thickness of the electron blocking layer 4 is 10-500 nm; the thickness of the undoped GaN layer 6 is 10 to 500 nm.
The heterostructure barrier layer 7 is made of one or a combination of any of AlGaN, AlInN, InGaN, AlInGaN and AlN, and the heterostructure barrier layer 7 is 5-50 nm thick.
The insulating layer 11 is made of SiO2, SiNx, Al2O3, AlN, HfO2, MgO, Sc2O3, Ga2O3, AlHfOx or HfSiON, and the thickness of the insulating layer 11 is 1-100 nm; the source electrode and the drain electrode are made of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; the grid electrode material is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy.
The method for manufacturing the longitudinally-conducting GaN normally-off MISFET device as shown in fig. 1 to 9 includes the following steps:
s1, growing an n-type lightly doped GaN layer 2 and an intrinsic GaN layer 3 on the conductive GaN substrate 1 by using a metal organic chemical vapor deposition method, as shown in FIG. 1;
s2 deposition of a layer of SiO by plasma enhanced chemical vapor deposition 2 As mask layer 14, as shown in fig. 2;
s3, selectively etching the gate region by photolithography, and retaining the mask layer 14 on the gate region, as shown in fig. 3;
s4, carrying out secondary epitaxial growth on the electron blocking layer 4, the low-voltage GaN layer 5, the non-doped GaN layer 6 and the heterostructure barrier layer 7 in a selective area by utilizing a metal organic chemical vapor deposition method to form a groove gate, as shown in FIG. 4;
s5, removing the mask layer 14 on the gate region by etching, as shown in fig. 5;
s6, depositing a high-K dielectric insulating layer 11 on the surface of the heterojunction barrier layer and the grooved gate region by using a plasma enhanced chemical vapor deposition method, as shown in FIG. 6;
s7, utilizing ICP to complete device isolation, simultaneously etching a base ohmic contact area on the insulating layer 11 on the heterojunction barrier layer, adopting an evaporation process to evaporate Ni/Au alloy on the base area as ohmic contact of the base, and as shown in figure 7
S8, utilizing ICP to complete device isolation, etching a source ohmic contact area on the insulating layer 11 on the heterojunction barrier layer, adopting an evaporation process to evaporate Ti/Al/Ni/Au alloy on the source area to be used as ohmic contact of a source electrode, and evaporating Ti/Al/Ni/Au alloy on the back surface of the conductive GaN substrate 1 to be used as ohmic contact of a drain electrode, as shown in FIG. 8;
s9, evaporating a gate metal 12Ni/Au alloy on the insulating layer 11 of the recessed gate region as a gate, as shown in fig. 9.
Thus, the whole device manufacturing process is completed. Fig. 9 is a schematic view of the device structure of example 1.
Example 2
Fig. 10 is a schematic view showing the structure of the device of this example, which is similar to the structure of example 1, except that an AlN layer 15 is interposed between the undoped GaN layer 6 and the heterostructure barrier layer 7, and the AlN layer 15 can improve the mobility of 2DEG at the heterostructure channel.
Example 3
Fig. 11 is a schematic view showing the device structure of this example, which is similar to embodiment 1 except that the cost of the device can be reduced by using an inexpensive silicon substrate using a low-resistance silicon substrate or low-resistance silicon carbide 17 and a conductive buffer layer 16 instead of the conductive GaN substrate 1, where the low resistance means that the resistivity ρ < 20 Ω · cm of the silicon substrate.
Furthermore, it should be noted that the drawings of the above embodiments are for illustrative purposes only and are not necessarily drawn to scale.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A GaN normally-closed MISFET device with vertical grooves grown in a selective area comprises a grid electrode, a source electrode, a drain electrode, an insulating layer (11), a conductive GaN substrate (1) and an epitaxial layer on the conductive GaN substrate, wherein the epitaxial layer comprises an n-type lightly-doped GaN layer (2) and an intrinsic GaN layer (3) which are epitaxially grown for the first time and a secondary epitaxial layer on which the selective area is grown, the secondary epitaxial layer comprises an electron blocking layer (4), a low-voltage GaN layer (5), an undoped GaN layer (6) and a heterostructure barrier layer (7) from bottom to top, groove channels are formed after secondary epitaxial growth, the surfaces of the groove channels and the heterostructure barrier layer (7) are covered with the insulating layer (11), the grid electrode is covered on the groove channels on the insulating layer (11), the two ends of the insulating layer (11) are etched to form source electrode areas, and the source electrode areas are etched to the electron blocking layer (4) to form base areas, and ohmic metal is evaporated in the base region to form a source electrode short circuit effect, ohmic metal is evaporated in the source electrode region to form a source electrode in contact with the heterojunction barrier layer, and the drain electrode ohmic contact metal (10) is arranged on the back of the conductive GaN substrate (1).
2. The selective area growth groove-vertical GaN normally-off MISFET device of claim 1, wherein: the groove is U-shaped.
3. The selected region grown trench vertical GaN normally off MISFET device of claim 2 wherein: the conductive GaN substrate (1) is a heavily doped GaN substrate, or consists of a low-resistance silicon substrate or low-resistance silicon carbide and a conductive buffer layer.
4. The selected region grown trench vertical GaN normally off MISFET device of claim 2 wherein: the thickness of the n-type lightly doped GaN layer (2) is 1-50 mu m; an intrinsic GaN layer (3) is also arranged between the n-type lightly doped GaN layer (2) and the secondary epitaxial layer, and the thickness of the intrinsic GaN layer is 10-100 nm.
5. The selective area growth groove-vertical GaN normally-off MISFET device of claim 3 or 4, wherein: the low-pressure GaN layer (5) is made of low-pressure GaN and has the thickness of 1-500 nm; the electron blocking layer (4) is made of a p-type doped GaN layer or a p-type doped AlGaN layer; the thickness of the electron blocking layer (4) is 10-500 nm; the thickness of the non-doped GaN layer (6) is 10-500 nm.
6. The MISFET device of claim 5, of the selective area growth groove-vertical GaN normally-off type, wherein: an AlN layer (15) is further grown between the undoped GaN layer (6) and the heterostructure barrier layer (7), the AlN layer (15) having a thickness of 1-10 nm.
7. The MISFET device of claim 6, of the selective area growth groove-vertical GaN normally-off type, wherein: the heterostructure barrier layer (7) is made of one or a combination of any one of AlGaN, AlInN, InGaN, AlInGaN and AlN, and the heterostructure barrier layer (7) is 5-50 nm thick.
8. The selective area growth trench vertical GaN normally off MISFET device of claim 7 wherein:the insulating layer (11) is made of SiO 2 、SiN x 、Al 2 O 3 、AlN、HfO 2 、MgO、Sc 2 O 3 、Ga 2 O 3 、AlHfO x Or HfSiON, the thickness of the insulating layer (11) being 1-100 nm; the source electrode and the drain electrode are made of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; the grid electrode material is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy.
9. A method of fabricating a selected area growth trench vertical GaN normally off MISFET device of claim 1 comprising the steps of:
s1, epitaxially growing an n-type lightly doped GaN layer (2) and an intrinsic GaN layer (3) on the conductive GaN substrate (1) for the first time;
s2 growing a SiO layer on the intrinsic GaN layer (3) 2 A layer as a mask layer (14);
s3, reserving a mask layer (14) above the gate forming region through a photoetching method;
s4, secondary epitaxial growth of an electron blocking layer (4), a low-voltage GaN layer (5), a non-doped GaN layer (6) and a heterostructure barrier layer (7) is carried out in the selected region to form a groove grid;
s5, removing the mask layer (14) above the gate region;
s6, depositing an insulating layer (11) of the grid electrode on the heterojunction barrier layer and the groove part;
s7, completing device isolation by dry etching, and etching a base ohmic contact region on the insulating layer (11); and a base ohmic contact metal (9) is vapor-deposited on the base region
S8, etching a source ohmic contact area on the insulating layer (11);
s9, evaporating a source ohmic contact metal (8) on the source region, and evaporating a drain ohmic contact metal (10) on the back surface of the conductive GaN substrate (1);
and S10, evaporating a gate metal (12) in the gate region on the insulating layer (11) at the groove.
10. The method of claim 9 wherein said MISFET device is made by a selective area growth groove vertical GaN normally-off MISFET device, comprising: the growth method of the n-type lightly doped GaN layer (2), the intrinsic GaN layer (3) in the step S1, the electron blocking layer (4), the low-pressure GaN layer (5), the non-doped GaN layer (6) and the heterostructure barrier layer (7) in the step S4 is a metal organic chemical vapor deposition method or a molecular beam epitaxy method;
the mask layer (14) in the step S2 and the insulating layer (11) in the step S5 are grown by a plasma enhanced chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method or a magnetron sputtering method.
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