JP2016086108A - Compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device capable of improving a withstanding voltage without deteriorating high-frequency characteristics.SOLUTION: In only a partial region on a carrier supply layer 13 between a drain electrode 17 and a gate electrode 15, a cap layer 18 in an electrically floating state is provided so as to be separated from the gate electrode 15. No electrode is provided on the cap layer 18 to make it in the floating state. The cap layer 18 is in a stripe shape and arranged in parallel to the gate electrode 15. The magnitude of polarization of the cap layer 18 is set to be lower than that of the carrier supply layer 13.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a compound semiconductor device, for example, a compound semiconductor device such as a HEMT (High Electron Mobility Transistor) using a GaN-based semiconductor.

  In recent years, GaN-based HEMTs using AlGaN / GaN heterojunctions and using GaN as an electron transit layer have been actively developed. GaN-based semiconductors are characterized by having a wide band gap, a high breakdown field strength, and a large saturation electron velocity compared to other III-V group compound semiconductors such as GaAs. With this feature, it is extremely promising as a material that can realize a transistor with a large current, high voltage, and low on-resistance.

  For this reason, development is actively conducted aiming at application to next-generation high-efficiency amplifiers used in base stations and the like in wireless communication systems and high-efficiency switching elements for controlling power.

  FIG. 17 is an explanatory view of a conventional GaN-based HEMT, FIG. 17 (a) is a cross-sectional view, and FIG. 17 (b) is an explanatory view of an electric field distribution near the gate electrode. As shown in FIG. 17A, the conventional GaN-based HEMT sequentially forms an i-type GaN electron transit layer 53 and an n-type AlGaN electron supply layer 54 on an SiC substrate 51 via an AlN nucleation layer 52. . At this time, a two-dimensional electron gas 55 is generated near the interface between the i-type GaN electron transit layer 53 and the n-type AlGaN electron supply layer 54. A SiN film 56 serving as a protective film is provided on the n-type AlGaN electron supply layer 54, and a source electrode 57, a drain electrode 58, and a gate electrode 59 are provided in the removed portion of the SiN film 56.

  In this GaN-based HEMT, high voltage operation is required, so that improvement in breakdown voltage performance is essential. However, when the carrier concentration of the two-dimensional electron gas 55 is increased in order to reduce the on-resistance, the pressure resistance performance deteriorates. This is because, as shown in FIG. 17B, when the carrier concentration of the two-dimensional electron gas 55 is high, the depletion layer is difficult to expand, and the electric field applied to the depletion layer becomes strong.

  Since the potential change between the gate electrode 59 and the drain electrode 58 occurs in the depletion layer having a high resistance, when the width of the depletion layer is narrow, the equipotential lines 60 are closely spaced and the potential changes greatly at a short distance. In addition, the electric field applied to the depletion layer becomes strong.

  In order to solve such a problem, it has been proposed to increase the width of the depletion layer by providing a field plate electrode or forming a gate electrode in a step shape to improve the withstand voltage performance (for example, patents). Reference 1 or Patent Document 2).

  FIG. 18 is a cross-sectional view of a conventional improved GaN-based HEMT. FIG. 18A shows a field plate 61 connected to a source electrode 57 between a gate electrode 59 and a drain electrode 58. FIG. 18B shows the gate electrode 62 having a ridge that protrudes toward the drain electrode 58. In either case, the width of the depletion layer in the vicinity of the gate electrodes 59 and 62 can be widened to improve the breakdown voltage performance.

  However, in these proposals, there is a problem that high-frequency characteristics are deteriorated due to generation of parasitic capacitance, and this situation will be described with reference to FIG. FIG. 19 is an explanatory diagram of problems of the conventional improved GaN-based HEMT. As shown in FIG. 19A, when the field plate 61 is provided, a parasitic capacitance is formed between the field plate 61 and the two-dimensional electron gas 55, causing a signal delay. As shown in FIG. 19B, when the gate electrode 62 is provided with a flange, a parasitic capacitance is formed between the flange and the two-dimensional electron gas 55, causing a signal delay. Become.

  On the other hand, it has been proposed that a GaN cap layer is provided so as to be in contact with the gate electrode, and the carrier concentration of the two-dimensional electron gas near the gate electrode is reduced by the GaN cap layer, thereby increasing the breakdown voltage (for example, Patent Document 3). reference).

  FIG. 20 is a cross-sectional view of a conventional high voltage GaN-based HEMT. A GaN channel layer 73, an AlGaN barrier layer 74, and a GaN cap layer 76 are formed on a semi-insulating SiC substrate 71 through a buffer layer 72. Also in this case, a two-dimensional electron gas 75 is generated in the vicinity of the interface between the GaN channel layer 73 and the AlGaN barrier layer 74. Si ions are implanted into the source / drain electrode formation region to form a Si implantation region 77, and a source electrode 78 and a drain electrode 79 are formed on the Si implantation region 77.

  After removing the GaN cap layer 76 in the gate electrode formation region, a T-type gate electrode 80 is formed, and the GaN cap layer is etched away leaving a part of the GaN cap layer on the drain side in contact with the gate electrode 80. A dielectric film 81 for protecting the surface is formed. Immediately below the remaining GaN cap layer 76, the carrier concentration of the two-dimensional electron gas 75 is reduced, so that the depletion layer is easily expanded and the breakdown voltage is improved.

Japanese Unexamined Patent Publication No. 2014-072391 JP, 2014-072360, A JP 2013-229486 A JP 2013-162078 A

  However, even in the case of this high breakdown voltage GaN-based HEMT, there is a problem that high-frequency characteristics are deteriorated due to the generation of parasitic capacitance, and this situation will be described with reference to FIG. FIG. 21 is an explanatory view of the problem of the conventional high-voltage GaN-based HEMT. A parasitic capacitance is formed between the two-dimensional electron gas 75 and the flange portion on the drain side of the T-type gate electrode 80, Cause delay.

  Furthermore, since the GaN cap layer 76 is very close to the gate electrode 80, there is a problem in that the electric field strength is still high at the drain side end of the GaN cap layer 76 and the breakdown voltage improvement effect is not always sufficient.

  Accordingly, it is an object of the compound semiconductor device to improve the breakdown voltage without deteriorating the high frequency characteristics.

  From one aspect disclosed, a substrate, a carrier running layer formed above the substrate, a carrier supply layer formed above the carrier running layer, and a gate electrode formed above the carrier supply layer And a region above the carrier supply layer between the source electrode and the drain electrode, and between the drain electrode and the gate electrode, which are formed at positions sandwiching the gate electrode in a direction parallel to the substrate There is provided a compound semiconductor device having a cap layer in an electrically floating state, which is formed only apart from the gate electrode.

  According to the disclosed compound semiconductor device, the breakdown voltage can be improved without deteriorating the high frequency characteristics.

It is explanatory drawing of the compound semiconductor device of embodiment of this invention. It is explanatory drawing of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 3 of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing after FIG. 4 of the manufacturing process of GaN-type HEMT of Example 1 of this invention. It is explanatory drawing of GaN-type HEMT of Example 2 of this invention. It is explanatory drawing to the middle of the manufacturing process of GaN-type HEMT of Example 2 of this invention. It is explanatory drawing after FIG. 7 of the manufacturing process of GaN-type HEMT of Example 2 of this invention. It is sectional drawing of GaN-type HEMT of Example 3 of this invention. It is sectional drawing of GaN-type HEMT of Example 4 of this invention. It is sectional drawing of GaN-type HEMT of Example 5 of this invention. It is sectional drawing of GaN-type HEMT of Example 6 of this invention. It is sectional drawing of GaN-type HEMT of Example 7 of this invention. It is explanatory drawing to the middle of the manufacturing process of GaN-type HEMT of Example 7 of this invention. It is explanatory drawing after FIG. 14 of the manufacturing process of GaN-type HEMT of Example 7 of this invention. It is sectional drawing of GaN-type HEMT of Example 8 of this invention. It is explanatory drawing of the conventional GaN-type HEMT. It is sectional drawing of the conventional improved GaN-type HEMT. It is explanatory drawing of the problem of the conventional improved GaN-type HEMT. It is sectional drawing of the conventional high voltage | pressure-resistant GaN-type HEMT. It is explanatory drawing of the problem of the conventional high voltage | pressure-resistant GaN-type HEMT.

  Here, a compound semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is an explanatory view of a compound semiconductor device according to an embodiment of the present invention, FIG. 1 (a) is a top view, and FIG. 1 (b) is a point connecting AA 'in FIG. 1 (a). It is sectional drawing along a dashed line. In this compound semiconductor device, a carrier travel layer 12 and a carrier supply layer 13 are provided on a substrate 11, and a gate electrode 15 is provided on the carrier supply layer 13. In addition, the source electrode 16 is provided on one side of the gate electrode, and the drain electrode 17 is provided on the opposite side of the gate electrode 15 from the source electrode 16.

  In the embodiment of the present invention, a cap layer 18 is provided apart from the gate electrode 15 only in a partial region on the carrier supply layer 13 between the drain electrode 17 and the gate electrode 15. Is not provided with an electrode, and is in a floating state. The cap layer 18 has a stripe shape and is arranged in parallel with the gate electrode 15. It is assumed that the polarization magnitude of the cap layer 18 is smaller than the polarization magnitude of the carrier supply layer 13. As a result, negative fixed charges are generated between the cap layer 18 and the carrier supply layer 13, the potential of the carrier supply layer is raised, and the carrier concentration of the two-dimensional electron gas is reduced in the region where the cap layer is formed. In order to sufficiently reduce the carrier concentration, the thickness of the cap layer is desirably 10 nm or more, although it depends on the thickness of the carrier supply layer 13. However, when a plurality of cap layers are provided, the cap layer is effective even if the thickness of the cap layer is 10 nm or less, for example, 5 nm.

  Thus, by providing the cap layer 18 apart from the gate electrode 15, the carrier concentration of the two-dimensional carrier gas 14 immediately below the cap layer 18 is reduced, the depletion layer is easily expanded, and the breakdown voltage is improved. Since the cap layer 18 is in a floating state without providing an electrode, no parasitic capacitance is generated.

  Moreover, since the formation of a new electrode becomes unnecessary by adopting the above-described structure, a parasitic capacitance is not newly generated, and the high frequency characteristics are not deteriorated. Further, by limiting the formation of the cap layer 18 to only a part between the gate electrode 15 and the drain electrode 17, the carrier concentration of the two-dimensional carrier gas remains high except under the cap layer 18. Can be suppressed to a slight increase.

  A plurality of cap layers 18 may be formed in parallel to each other. Thus, by forming a plurality of cap layers 18, the interval between equipotential lines near the end on the drain side of the cap layer 18 closest to the gate electrode 15 can be increased, and the breakdown voltage is further increased. Can do. In addition, since it is not necessary to provide the cap layer 18 wide, the carrier concentration of the two-dimensional carrier gas is not reduced more than necessary, and an increase in on-resistance can be suppressed.

  In this case, the thickness of the cap layer 18 may be gradually decreased toward the drain electrode 17. Since the electric field strength decreases as the distance from the gate electrode 15 decreases, the piezo electric field relaxation effect may be small, thereby suppressing the increase in on-resistance more than when the cap layer 18 having the same thickness is provided. it can.

  Further, a protective layer may be provided on the entire surface of the carrier supply layer 13 between the gate electrode 15 and the source electrode 16 and on the entire surface of the carrier supply layer 13 between the gate electrode 15 and the drain electrode 17. If the surface of the carrier supply layer 13 is exposed, it is oxidized and trap levels are generated, which tends to cause unstable operation problems such as current collapse. For this reason, the problem of unstable operation due to oxidation of the carrier supply layer 13 can be prevented by setting the protective layer to the outermost surface.

  In this case, the protective layer may be formed by thinly etching a semiconductor layer for forming a piezoelectric field relaxation layer deposited on the entire surface, or may be formed separately from the cap layer 18. For example, when an n-type layer is provided as the protective layer, the source electrode 16 and the drain electrode 17 may be formed on the protective layer without removing the protective layer. The protective layer is desirably 3 nm or less in thickness so as not to excessively affect the carrier concentration of the two-dimensional carrier gas.

The carrier running layer 12 in this case is typically a GaN-based semiconductor containing GaN such as GaN, InGaN, AlGaN or the like. As the carrier supply layer 13, InAlGaN containing GaN such as In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) such as GaN, AlGaN, or AlInGaN. System semiconductors are typical. The cap layer 18 is typically a GaN-based semiconductor containing GaN such as GaN or InGaN.

  The substrate 11 is typically a Si substrate, a sapphire substrate, a SiC substrate, or a GaN substrate, and an SiC substrate or a GaN substrate with few occurrences of threading dislocations is preferable from the viewpoint of crystallinity. On the other hand, the Si substrate is optimal from the viewpoint of cost.

  In order to reduce leakage current due to threading dislocations, it has been proposed to provide a GaN layer on the AlGaN layer so as to cover the threading dislocations separately from the gate electrode (see, for example, Patent Document 4). ). However, in this proposal, the GaN layer is necessarily provided near the source electrode, and the GaN layer is locally provided so as to cover the threading dislocations individually. The effect of increasing the withstand voltage is insufficient. On the other hand, in the embodiment of the present invention, since the cap layer 18 is arranged in parallel with the gate electrode 15, the electric field is uniformly relaxed and the withstand voltage is sufficiently increased.

  Next, a GaN-based HEMT according to Example 1 of the present invention will be described with reference to FIGS. 2A and 2B are explanatory diagrams of the GaN-based HEMT according to the first embodiment of the present invention, FIG. 2A is a cross-sectional view, and FIG. 2B is an explanatory diagram of equipotential line distribution. As shown in FIG. 2A, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22 to form an i-type GaN electron transit layer. A two-dimensional electron gas 25 is formed at the interface between the n-type AlGaN electron supply layer 24 and the n-type AlGaN electron supply layer 24.

  A source electrode 31, a drain electrode 32, and a gate electrode 35 are formed on the n-type AlGaN electron supply layer 24, and a thickness of 10 nm is formed on the drain side of the gate electrode 35 at a position 0.5 μm away from the gate electrode 35. An i-type GaN cap layer 28 having a width of 1 μm is provided. Since the i-type GaN cap layer 28 has a smaller polarization than the n-type AlGaN electron supply layer 24, a negative fixed charge is generated at the boundary between the i-type GaN cap layer 28 and the n-type AlGaN electron supply layer 24. For this reason, the potential of the n-type AlGaN electron supply layer 24 rises, and the carrier concentration of the two-dimensional electron gas 25 immediately below the i-type GaN cap layer 28 decreases.

  As shown in FIG. 2B, the carrier concentration of the two-dimensional electron gas 25 immediately below the i-type GaN cap layer 28 decreases and the depletion layer easily expands, so that the equipotential lines 36 near the gate electrode 35 Widening the interval increases the breakdown voltage.

  Next, with reference to FIGS. 3 to 5, a manufacturing process of the GaN-based HEMT according to the first embodiment of the present invention will be described. First, as shown in FIG. 3A, an AlN nucleation layer 22, an i-type GaN electron transit layer 23 having a thickness of 2 μm, and a MOCVD (metal organic chemical vapor deposition) method are used on an SiC substrate 21. An n-type AlGaN electron supply layer 24 having a thickness of 10 nm and an Al composition ratio of 0.2 is sequentially formed. At this time, a two-dimensional electron gas 25 is formed between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24.

  Subsequently, as shown in FIG. 3B, an i-type GaN layer 26 having a thickness of 10 nm is formed on the n-type AlGaN electron supply layer 24. Since the i-type GaN layer 26 acts to prevent the generation of the two-dimensional electron gas 25 between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24, the carrier concentration of the two-dimensional electron gas 25 is reduced. Decreases.

Next, as shown in FIG. 4C, a resist pattern 27 having a width of 1 μm is formed. Next, as shown in FIG. 4D, by performing dry etching using the resist pattern 27 as a mask, the exposed portion of the i-type GaN layer 26 is removed and the remaining portion is used as an i-type GaN cap layer 28. At this time, the carrier concentration of the two-dimensional electron gas 25 in the removed portion of the i-type GaN layer 26 is increased again. In dry etching, a chlorine-based gas such as Cl ₂ or BCl ₃ is used as an etching gas. The i-type GaN cap layer 28 has a stripe pattern as shown in FIG. 1A, and is arranged in parallel with a gate electrode formed in a later step.

  Next, as shown in FIG. 5E, after the resist pattern 27 is removed by ashing, a resist pattern 29 having openings in the source / drain electrode formation portions is newly formed. Next, a Ti film having a thickness of 10 nm and an Al film having a thickness of 200 nm are sequentially deposited to form a Ti / Al film 30. At this time, the Ti / Al film deposited in the opening becomes the source electrode 31 and the drain electrode 32.

  Next, as shown in FIG. 5F, the Ti / Al film 30 deposited on the resist pattern 29 is removed together with the resist pattern 29 by lift-off. Next, a resist pattern 33 having an opening for a gate electrode is formed at a position 0.5 μm away from the i-type GaN cap layer 28. Next, a Ni film having a thickness of 50 nm and an Au film having a thickness of 300 nm are sequentially deposited to form a Ni / Au film 34. At this time, the Ni / Au film deposited in the opening becomes the gate electrode 35. The interval between the opposing ends of the gate electrode 35 and the drain electrode 32 is 5 μm. Thereafter, the Ni / Au film 34 deposited on the resist pattern 33 is removed together with the resist pattern 33 by lift-off, thereby completing the basic structure of the GaN-based HEMT shown in FIG.

  In Embodiment 1 of the present invention, the electrically floating i-type GaN cap layer 28 serving as a piezoelectric field relaxation layer is disposed in the vicinity of the gate electrode 35 and spaced apart from the gate electrode 35, so that the parasitic capacitance is greatly increased. Can be reduced. As a result, it is possible to realize a GaN-based HEMT having excellent high frequency characteristics and excellent withstand voltage performance.

  Next, a GaN-based HEMT according to Example 2 of the present invention will be described with reference to FIGS. 6 is an explanatory diagram of a GaN-based HEMT according to Example 2 of the present invention, FIG. 6A is a sectional view, and FIG. 6B is an explanatory diagram of equipotential line distribution. As shown in FIG. 6A, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22 to form an i-type GaN electron transit layer. A two-dimensional electron gas 25 is formed at the interface between the n-type AlGaN electron supply layer 24 and the n-type AlGaN electron supply layer 24.

On the n-type AlGaN electron supply layer 24, a source electrode 31, a drain electrode 32, and a gate electrode 35 are formed. A gate electrode 35 and 0.5μm thick at a position spaced a width at 10nm is 1μm of the i-type GaN cap layer 38 ₁ on the drain side of the gate electrode 35, away 0.5μm from i-type GaN cap layer 38 ₁ width position provided i-type GaN cap layer 38 ₂ of 1 [mu] m.

As shown in FIG. 6B, since the i-type GaN cap layers 38 ₁ and 38 ₂ have a piezoelectric field relaxation effect, carriers of the two-dimensional electron gas 25 immediately below the i-type GaN cap layers 38 ₁ and 38 ₂ are obtained. The concentration decreases and the depletion layer tends to expand. As a result, the withstand voltage is improved because the interval between the equipotential lines 36 near the gate electrode 35 is increased.

This, at both ends of the edge and the i-type GaN cap layer 38 ₁ of the gate electrode 35 due to large changes in concentration and interface states of charge, will be the electric field is concentrated, there is a case where the breakdown voltage is deteriorated. Therefore it is possible to reduce the intensity of the electric field generated by the electric field concentration by dispersing the concentration portions of an electric field by a plurality installing i-type GaN cap layer 38 _1, 38 _2.

  Next, with reference to FIGS. 7 and 8, the manufacturing process of the GaN-based HEMT according to the second embodiment of the present invention will be described. First, as shown in FIG. 7A, as in the first embodiment, the AlN nucleation layer 22 and the i-type GaN electron transit layer having a thickness of 2 μm are formed on the SiC substrate 21 by using the MOCVD method. 23 and an n-type AlGaN electron supply layer 24 having a thickness of 10 nm and an Al composition ratio of 0.2 are sequentially formed. Subsequently, an i-type GaN layer 26 having a thickness of 10 nm is formed on the n-type AlGaN electron supply layer 24. Next, two resist patterns 37 having a width of 1 μm and an interval of 0.5 μm are formed.

Next, as shown in FIG. 7B, by performing dry etching using the resist pattern 37 as a mask, the exposed portion of the i-type GaN layer 26 is removed and the remaining portions are replaced with i-type GaN cap layers 38 ₁ and 38 ₂ . To do. The i-type GaN cap layers 38 ₁ and 38 ₂ are also in a stripe pattern as shown in FIG. 1A, and are arranged in parallel with the gate electrode formed in a later step. In dry etching, a chlorine-based gas such as Cl ₂ or BCl ₃ is used as an etching gas.

  Next, as shown in FIG. 8C, after the resist pattern 37 is removed by ashing, a resist pattern 29 having openings in the source / drain electrode formation portions is newly formed. Next, a Ti film having a thickness of 10 nm and an Al film having a thickness of 200 nm are sequentially deposited to form a Ti / Al film 30. At this time, the Ti / Al film deposited in the opening becomes the source electrode 31 and the drain electrode 32.

Next, as shown in FIG. 8D, the Ti / Al film 30 deposited on the resist pattern 29 is removed together with the resist pattern 29 by lift-off. Next, a resist pattern 33 having an opening for the gate electrode from the i-type GaN cap layer 38 ₁ at a distance 0.5 [mu] m. Next, a Ni film having a thickness of 50 nm and an Au film having a thickness of 300 nm are sequentially deposited to form a Ni / Au film 34. At this time, the Ni / Au film deposited in the opening becomes the gate electrode 35. The interval between the opposing ends of the gate electrode 35 and the drain electrode 32 is 5 μm. Thereafter, the Ni / Au film 34 deposited on the resist pattern 33 is removed together with the resist pattern 33 by lift-off, thereby completing the basic configuration of the GaN-based HEMT shown in FIG.

Since is provided by dispersing electrically floating i-type GaN cap layer 38 _1, 38 ₂ as a piezoelectric field relaxation layer in two in the second embodiment of the present invention, the depletion layer width than that of Example 1 Can be further spread and the electric field concentration points can be dispersed. As a result, it is possible to realize a GaN-based HEMT having a better pressure resistance than that of the first embodiment.

  Next, a GaN-based HEMT according to Example 3 of the present invention will be described with reference to FIG. 9, but the basic manufacturing process is the same as that of Example 2 described above except that the number of i-type GaN cap layers is different. Therefore, only the final cross-sectional structure will be described. FIG. 9 is a sectional view of a GaN-based HEMT according to Example 3 of the present invention. As shown in FIG. 9, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22, and the i-type GaN electron transit layer 23 and n A two-dimensional electron gas 25 is formed at the interface with the type AlGaN electron supply layer 24.

On the n-type AlGaN electron supply layer 24, a source electrode 31, a drain electrode 32, and a gate electrode 35 are formed. The spacing thickness of three to the gate electrode 35 and 0.5μm spaced positions width at 10nm an i-type GaN cap layer ₃₈ 1-38 ₃ 1μm of each other on the drain side of the gate electrode 35 is 0.5μm Arrange so that

Since in the third embodiment of the present invention is provided by dispersing electrically floating i-type GaN cap layer 38 _{1-38 3} as a piezoelectric field relaxation layer 3, the depletion layer width than that of Example 2 Can be further spread and the electric field concentration points can be dispersed. As a result, it is possible to realize a GaN-based HEMT having a better pressure resistance than that of the second embodiment. However, since the carrier concentration of the two-dimensional electron gas 25 immediately below the i-type GaN cap layer is lowered, the on-resistance is somewhat increased. In the third embodiment, three i-type GaN cap layers are provided, but four or more may be provided depending on the distance between the gate electrode 35 and the drain electrode 32.

  Next, a GaN-based HEMT according to Example 4 of the present invention will be described with reference to FIG. 10. The basic manufacturing process is the same as that described above except that the film thickness of the second i-type GaN cap layer is different. Since this is the same as Example 2, only the final cross-sectional structure will be described. FIG. 10 is a sectional view of a GaN-based HEMT according to Example 4 of the present invention. As shown in FIG. 10, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22, and the i-type GaN electron transit layer 23 and n A two-dimensional electron gas 25 is formed at the interface with the type AlGaN electron supply layer 24.

On the n-type AlGaN electron supply layer 24, a source electrode 31, a drain electrode 32, and a gate electrode 35 are formed. A gate electrode 35 and 0.5μm thick at a position spaced a width at 10nm is 1μm of the i-type GaN cap layer 38 ₁ on the drain side of the gate electrode 35, away 0.5μm from i-type GaN cap layer 38 ₁ thickness position width 5nm is provided an i-type GaN cap layer 38 ₄ 1 [mu] m. In order to form such a structure, the i-type GaN layer (26) may be etched for each cap layer.

Because are provided distributed electrically floating i-type GaN cap layer 38 1 serving as a piezoelectric field relaxation _layer, 38 ₄ to 2 in the fourth embodiment of the present invention, the depletion layer width than that of Example 1 Can be further spread and the electric field concentration points can be dispersed. Further, since the film thickness of the second i-type GaN cap layer 38 ₄ is thinner, so the two-dimensional carrier density of electron gas 25 just below the i-type GaN cap layer 38 ₄ is not so much reduced, Example 2 It is possible to realize a GaN-based HEMT having a smaller on-resistance.

  Next, a GaN-based HEMT according to Example 5 of the present invention will be described with reference to FIG. 11. Since the other structure is the same as that of Example 2 just by replacing the cap layer with InGaN, the final example is as follows. Only a typical cross-sectional structure will be described. FIG. 11 is a sectional view of a GaN-based HEMT according to Example 4 of the present invention. As shown in FIG. 11, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22, and the i-type GaN electron transit layer 23 and n A two-dimensional electron gas 25 is formed at the interface with the type AlGaN electron supply layer 24.

On the n-type AlGaN electron supply layer 24, a source electrode 31, a drain electrode 32, and a gate electrode 35 are formed. A gate electrode 35 and 0.5μm thick at a position spaced a width at 10nm is 1μm of i-type InGaN cap layer 39 ₁ on the drain side of the gate electrode 35, away 0.5μm from i-type InGaN cap layer 39 ₁ width position provided i-type InGaN cap layer 39 ₂ of 1 [mu] m. In the i-type InGaN cap layers 39 ₁ and 39 ₂ grown on the n-type AlGaN electron supply layer 24, compressive strain is generated, so that piezoelectric polarization occurs on the surface side. Therefore, since the polarization in the i-type InGaN cap layers 39 ₁ and 39 ₂ has different polarities in the n-type AlGaN electron supply layer 24, the i-type InGaN cap layers 39 ₁ and 39 ₂ and the n-type AlGaN electron supply layer 24 are different. A negative fixed charge is generated at the boundary. For this reason, the potential of the n-type AlGaN electron supply layer 24 rises, and the carrier concentration of the two-dimensional electron gas 25 immediately below the i-type InGaN cap layers 39 ₁ and 39 ₂ decreases.

The negative fixed charges generated by the i-type InGaN cap layers 39 ₁ and 39 ₂ are larger than the negative fixed charges when the i-type GaN cap layer is formed, and the amount of decrease in the carrier concentration of the two-dimensional electron gas 25 is larger. Become. Therefore, in the fifth embodiment of the present invention, the depletion layer width can be further expanded and the electric field concentration portions can be dispersed as compared with the first embodiment.

  Next, a GaN-based HEMT according to Example 6 of the present invention will be described with reference to FIG. 12. However, the other structure is the same as that of Example 2 above, except that the cap layer is replaced with p-type GaN. Only the final cross-sectional structure will be described. FIG. 12 is a sectional view of a GaN-based HEMT according to Example 6 of the present invention. As shown in FIG. 12, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22, and the i-type GaN electron transit layer 23 and n A two-dimensional electron gas 25 is formed at the interface with the type AlGaN electron supply layer 24.

On the n-type AlGaN electron supply layer 24, a source electrode 31, a drain electrode 32, and a gate electrode 35 are formed. A p-type GaN cap layer 40 ₁ thickness to the gate electrode 35 and 0.5μm position spaced drain side width 10nm of 1μm of the gate electrode 35, away 0.5μm p-type GaN cap layer 40 ₁ width position provided p-type GaN cap layer 40 ₂ of 1 [mu] m. n-type AlGaN electron supply layer p-type GaN cap layer grown on the 24 ₄₀ 1, 40 ₂ by lifting the potential of the n-type AlGaN electron supply layer 24, p-type GaN two-dimensional electron gas 25 of the carrier immediately below the capping layer 39 Concentration decreases.

Thus, also in the GaN-based HEMT grown on nonpolar plane that does not generate polarization by using a p-type GaN cap layer 40 _1, 40 _2, it is possible to reduce the carrier concentration of the two-dimensional electron gas 25. Therefore, in Example 6 of the present invention, a GaN-based HEMT having excellent high-frequency characteristics and excellent withstand voltage performance can be realized even in a GaN-based HEMT grown on a nonpolar surface.

  Next, a GaN-based HEMT according to Example 7 of the present invention will be described with reference to FIGS. FIG. 13 is a sectional view of a GaN-based HEMT according to Example 7 of the present invention. As shown in FIG. 13, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22, and the i-type GaN electron transit layer 23 and n A two-dimensional electron gas 25 is formed at the interface with the type AlGaN electron supply layer 24.

  On the n-type AlGaN electron supply layer 24, a source electrode 31, a drain electrode 32, and a gate electrode 35 are formed. An i-type GaN protective layer 41 having a thickness of 2 nm is provided on the surface of the n-type AlGaN electron supply layer 24 between the gate electrode 35 and the source electrode 31 and between the gate electrode 35 and the drain electrode 32. Further, an i-type GaN cap layer 42 having a thickness of 10 nm and a width of 1 μm from the n-type AlGaN electron supply layer 24 is provided on the drain side of the gate electrode 35 at a position 0.5 μm away from the gate electrode 35.

  The n-type AlGaN electron supply layer 24 is easily oxidized because it contains Al. Therefore, if the n-type AlGaN electron supply layer 24 is exposed on the outermost surface, the surface of the n-type AlGaN electron supply layer 24 is oxidized and trap levels are generated, thereby causing unstable operation problems such as current collapse. Become. However, as shown in FIG. 13, the i-type GaN protective layer 41 is placed on the outermost surface, so that the problem of unstable operation due to oxidation of the n-type AlGaN electron supply layer can be prevented. A stable GaN-based HEMT can be realized.

  Next, with reference to FIGS. 14 and 15, a manufacturing process of the GaN-based HEMT according to Example 7 of the present invention will be described. First, as shown in FIG. 14A, as in the first embodiment, the AlN nucleation layer 22 and the i-type GaN electron transit layer having a thickness of 2 μm are formed on the SiC substrate 21 using the MOCVD method. 23 and an n-type AlGaN electron supply layer 24 having a thickness of 10 nm and an Al composition ratio of 0.2 are sequentially formed. Subsequently, an i-type GaN layer 26 having a thickness of 10 nm is formed on the n-type AlGaN electron supply layer 24. Next, a resist pattern 27 having a width of 1 μm is formed.

Next, as shown in FIG. 14B, by performing dry etching using the resist pattern 27 as a mask, the exposed portion of the i-type GaN layer 26 is removed until the thickness becomes 2 nm, and the i-type GaN protective layer 41 is removed. And the remainder is the i-type GaN cap layer 42. The i-type GaN cap layer 42 also has a stripe pattern as shown in FIG. 1A, and is arranged in parallel with a gate electrode formed in a later step. In dry etching, a chlorine-based gas such as Cl ₂ or BCl ₃ is used as an etching gas.

  Next, as shown in FIG. 15C, after the resist pattern 27 is removed by ashing, a resist pattern 42 having openings in the source / drain electrode formation portion and the gate electrode formation portion is newly formed. Next, the exposed i-type GaN protective layer 41 is removed using the resist pattern 43 as a mask to expose the surface of the n-type AlGaN electron supply layer 24.

  Thereafter, as shown in FIG. 15 (d), the source electrode 31, the drain electrode 32, and the gate electrode 35 are formed by using the lift-off method in the same procedure as in the first embodiment, so that the seventh embodiment of the present invention. The basic structure of the GaN-based HEMT is completed.

  In Example 7 of the present invention, when forming the electrically floating i-type GaN cap layer 42 to be a piezoelectric field relaxation layer, the i-type GaN protective layer 41 is formed so as to cover the surface of the n-type AlGaN electron supply layer 24. Is provided. As a result, since the generation of trap levels can be suppressed, a GaN-based HEMT having more stable characteristics than Example 1 can be realized.

  Next, a GaN-based HEMT according to Example 8 of the present invention will be described with reference to FIG. 16. This is basically the same as Example 7 except that the surface protective layer is an n-type GaN protective layer. Therefore, only the final cross-sectional structure will be described. FIG. 16 is a sectional view of a GaN-based HEMT according to Example 8 of the present invention. As shown in FIG. 16, an i-type GaN electron transit layer 23 and an n-type AlGaN electron supply layer 24 are formed on an SiC substrate 21 via an AlN nucleation layer 22, and the i-type GaN electron transit layer 23 and n A two-dimensional electron gas 25 is formed at the interface with the type AlGaN electron supply layer 24.

  A gate electrode 35 is provided on the n-type AlGaN electron supply layer 24, and an n-type GaN protective layer 44 having a thickness of 2 nm is provided in other regions, and the source electrode 31 and the n-type GaN protective layer 44 are interposed through the n-type GaN protective layer 44. A drain electrode 32 is provided.

  An i-type GaN cap layer 45 having a thickness of 8 nm and a width of 1 μm is provided on the drain side of the gate electrode 35 at a position spaced 0.5 μm from the gate electrode 35. In the case of forming such a structure, a 2 nm n-type GaN layer and an 8 nm i-type GaN layer may be sequentially formed in the growth process of the 10 nm i-type GaN layer 26 in Example 6.

  Also in the eighth embodiment, since the n-type AlGaN electron supply layer 24 is covered with the n-type GaN protective layer 44, the problem of unstable operation due to oxidation of the n-type AlGaN electron supply layer can be prevented. A GaN-based HEMT having more stable electrical characteristics than 1 can be realized.

Here, the following additional notes are attached to the embodiment of the present invention including Examples 1 to 8.
(Appendix 1) Substrate, carrier running layer formed above the substrate, carrier supply layer formed above the carrier running layer, gate electrode formed above the carrier supply layer, In the direction parallel to the substrate, the source electrode and the drain electrode formed at positions sandwiching the gate electrode, and only in a partial region above the carrier supply layer between the drain electrode and the gate electrode. A compound semiconductor device comprising: a cap layer which is formed in an electrically floating state so as to be separated from the gate electrode.
(Supplementary Note 2) The carrier travel layer is made of a nitride semiconductor, and the carrier supply layer is In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y << 1, 0 ≦ x + y ≦ 1). The compound semiconductor device according to appendix 1, wherein the cap layer is made of a nitride semiconductor.
(Additional remark 3) The compound semiconductor device of Additional remark 1 or Additional remark 2 characterized by the absolute value of the magnitude | size of the polarization in the said cap layer being smaller than the absolute value of the magnitude of the polarization in the said carrier supply layer.
(Additional remark 4) The compound semiconductor device of Additional remark 1 or Additional remark 2 characterized by the polarity of the polarization in the said cap layer differing from the polarity of the polarization of the said carrier supply layer.
(Supplementary note 5) The compound semiconductor device according to supplementary note 1 or supplementary note 2, wherein the cap layer is doped with a p-type impurity.
(Supplementary note 6) The compound semiconductor device according to any one of supplementary notes 1 to 5, wherein the cap layer has a stripe shape and is arranged in parallel with the gate electrode.
(Supplementary note 7) The compound semiconductor device according to supplementary note 6, wherein a plurality of the cap layers are formed in parallel to each other.
(Additional remark 8) The compound semiconductor device of Additional remark 7 characterized by the thickness of the said cap layer becoming thin gradually toward the said drain electrode.
(Supplementary Note 9) A protective layer is provided on the entire surface of the carrier supply layer between the gate electrode and the source electrode and on the entire surface of the carrier supply layer between the gate electrode and the drain electrode, and the cap 9. The compound semiconductor device according to any one of appendix 1 to appendix 8, wherein a layer is provided on the protective layer.
(Supplementary note 10) The compound semiconductor device according to supplementary note 9, wherein the protective layer has a composition different from that of the cap layer including impurities contained therein.
(Supplementary note 11) The compound semiconductor device according to any one of supplementary notes 1 to 10, wherein the substrate is any one of a Si substrate, a sapphire substrate, a SiC substrate, and a GaN substrate.

11 substrate 12 carrier traveling layer 13 carrier supply layer 14 two-dimensional carrier gas 15 gate electrode 16 source electrode 17 drain electrode 18 cap layer 21, 51 SiC substrate 22, 52 AlN nucleation layer 23, 53 i-type GaN electron traveling layer 24, 54 n-type AlGaN electron supply layer 25, 55 the two-dimensional electron gas 26 i-type GaN layer 27, 37 resist pattern 28,38 ₁ ~38 ₄ i-type GaN cap layer 29 a resist pattern 30 Ti / Al film 31,57 source electrode 32 , 58 Drain electrode 33 Resist pattern 34 Ni / Au film 35, 59, 62 Gate electrode 36, 60 Equipotential line 39 ₁ , 39 ₂ i-type InGaN cap layer 40 ₁ , 40 ₂ p-type GaN cap layer 41 i-type GaN protection Layers 42 and 45 i-type InGaN cap layer 43 resist pattern 44 n-type GaN protective layer 56 SiN film 61 Field plate 71 Semi-insulating SiC substrate 72 Buffer layer 73 GaN channel layer 74 AlGaN barrier layer 75 Two-dimensional electron gas 76 GaN cap layer 77 Si injection region 78 Source electrode 79 Drain electrode 80 Gate Electrode 81 Dielectric film

Claims (8)

A substrate,
A carrier running layer formed above the substrate;
A carrier supply layer formed above the carrier travel layer;
A gate electrode formed above the carrier supply layer;
A source electrode and a drain electrode formed at positions sandwiching the gate electrode in a direction parallel to the substrate;
A cap layer in an electrically floating state, formed apart from the gate electrode only in a partial region above the carrier supply layer between the drain electrode and the gate electrode;
A compound semiconductor device comprising: The carrier traveling layer is made of a nitride semiconductor,
The carrier supply layer is made of _{In x Al y Ga 1-x} -y N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1),
The compound semiconductor device according to claim 1, wherein the cap layer is made of a nitride semiconductor.   3. The compound semiconductor device according to claim 1, wherein an absolute value of a polarization magnitude in the cap layer is smaller than an absolute value of a polarization magnitude in the carrier supply layer.   The compound semiconductor device according to claim 1, wherein a polarity of polarization in the cap layer is different from a polarity of polarization of the carrier supply layer.   The compound semiconductor device according to claim 1, wherein the cap layer is doped with a p-type impurity.   The compound semiconductor device according to claim 1, wherein the cap layer has a stripe shape and is arranged in parallel with the gate electrode.   The compound semiconductor device according to claim 6, wherein a plurality of the cap layers are formed in parallel to each other. A protective layer is provided on the entire surface of the carrier supply layer between the gate electrode and the source electrode and on the entire surface of the carrier supply layer between the gate electrode and the drain electrode;
The compound semiconductor device according to claim 1, wherein the cap layer is provided on the protective layer.

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