JP5505698B2 - Semiconductor device - Google Patents

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JP5505698B2
JP5505698B2 JP2010020134A JP2010020134A JP5505698B2 JP 5505698 B2 JP5505698 B2 JP 5505698B2 JP 2010020134 A JP2010020134 A JP 2010020134A JP 2010020134 A JP2010020134 A JP 2010020134A JP 5505698 B2 JP5505698 B2 JP 5505698B2
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就彦 前田
△惠▽之 名西
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日本電信電話株式会社
学校法人立命館
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The present invention relates to a semiconductor device, particularly relates to a microwave compound semiconductor field effect transistor of the high temperature, high power and high breakdown voltage.

  Heterostructure field effect transistors (HFETs) using nitride semiconductors are very promising as next-generation high-frequency, high-power, high-voltage, ultrahigh-frequency transistors, and are currently promising for practical application. Research has been conducted. In the future, to improve the performance of these nitride semiconductor HFETs, the ohmic contact resistance between the source and drain electrodes and the nitride semiconductor will be reduced, and the resistance from the source electrode to the channel (access resistance) will be reduced. It is very important and essential to increase the speed, gain, and loss (reduction in power consumption) of the element by reducing the element.

  Currently, AlGaN / GaN HFETs that use AlGaN as the barrier layer semiconductor and GaN as the channel layer semiconductor, which are most practically used, are designed to reduce ohmic contact resistance and access resistance. In the ohmic region where the drain electrode and the drain electrode are formed, the AlGaN barrier layer semiconductor is removed, and a GaN layer that is a channel layer semiconductor is stacked (regrown) instead of the AlGaN barrier layer semiconductor, and the source electrode and the drain electrode are formed as the AlGaN barrier layer. It is known that a regrowth ohmic structure formed on a GaN layer having a smaller bandgap than the above is effective (see Non-Patent Document 1 below). This is because GaN having a smaller band gap than AlGaN has a smaller ohmic contact resistance with the electrode metal and a smaller resistance (access resistance) from the source electrode to the channel.

  In the AlGaN / GaN HFET having the above-mentioned regrowth ohmic structure, in order to further reduce the ohmic contact resistance, in the ohmic region where the source electrode and the drain electrode are formed, the band gap is smaller than GaN, not GaN. It is an effective means to form a source electrode and a drain electrode on the InGaN layer using a structure in which InGaN is laminated (regrown) instead of GaN. On the other hand, in this case, the InGaN layer in the ohmic region A conduction band edge discontinuity is formed between the GaN layer that functions as a channel layer and exists under the gate electrode, and this conduction band discontinuity becomes a barrier for electron transport. Since it does not decrease, the characteristics of the HFET do not improve. Therefore, in the nitride semiconductor HFET, there has been a strong demand for the development of a new device structure that greatly reduces the ohmic contact resistance and at the same time greatly reduces the access resistance, and as a result, enables high performance.

  Non-Patent Document 1 below is a report of AlGaN / GaN HFETs using a regrowth ohmic structure, and Non-Patent Document 2 includes bands and lineups of various semiconductors (conduction bands and AlN, GaN, InN, etc.). Relative position of valence band) is shown, and Non-Patent Document 3 is a report of surface charge accumulation in InN.

N. Maeda et.al., Jpn. J. of Appl.Phys. 44, L646 (2005). C. G. Van de Walle and J. Neugebauer, Nature 423, 626 (2003). H. Lu et. Al., Appl. Phys. Lett. 82, 1736 (2003).

The present invention has been made in view of the above-mentioned demands, and the problem to be solved by the present invention is to greatly reduce the ohmic contact resistance in a heterostructure field effect transistor using a nitride semiconductor, and at the same time, a source electrode It is an object to provide a semiconductor device capable of greatly reducing the resistance (access resistance) from the channel to the channel and, as a result, achieving high speed and low loss (low power consumption).

In the present invention, in order to solve the above problem, as described in claim 1,
In a semiconductor device that is a heterostructure field effect transistor using a nitride semiconductor, the band gap of the source side nitride semiconductor that is in ohmic contact with the source electrode and the drain side nitride semiconductor that is in ohmic contact with the drain electrode forms a channel. Smaller than the band gap of the nitride channel layer semiconductor, and between the source side nitride semiconductor and the nitride channel layer semiconductor, and between the drain side nitride semiconductor and the nitride channel layer semiconductor. Are connected via a composition graded nitride semiconductor whose composition changes continuously, respectively, thereby connecting the source electrode and the channel and the drain electrode and the channel. discontinuity of the semiconductor bandgap has been resolved in the source-side nitride Composition of the semiconductor and the drain-side nitride semiconductor, (here, it is 0.46 ≦ X ≦ 1.0) In X Ga 1-X N is represented by the surface of the both nitride semiconductor, the gate electrode Formed on the surface of the source-side nitride semiconductor by being positioned above the heterointerface between the nitride barrier layer semiconductor existing below and the nitride channel layer semiconductor by a distance of 0 nm to 10 nm. The semiconductor device is characterized in that the electron distribution in the charge storage layer is overlapped with the electron distribution in the nitride channel layer semiconductor .

Oite The semiconductor device according to the present invention,
A nitride semiconductor having a smaller band gap than the channel layer semiconductor is used as the nitride semiconductor (source-side nitride semiconductor and drain-side nitride semiconductor) in the ohmic region in which the source electrode and the drain electrode are formed, and the ohmic region Therefore, there is no conduction band edge discontinuity (that is, band gap discontinuity) between the nitride semiconductor and the channel layer semiconductor existing under the gate electrode. It is possible to realize a high-performance nitride semiconductor HFET capable of reducing loss (reducing power consumption).

In particular, in the above HFET, In X Ga 1-X N (0.46 ≦ X ≦ 1.0) is used as the nitride semiconductor (source side nitride semiconductor and drain side nitride semiconductor) in the ohmic region where the source electrode and the drain electrode are formed. ) And the surface of the In X Ga 1-X N (0.46 ≦ X ≦ 1.0) is 0 nm or more than the position of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode It is possible to obtain a particularly high performance HFET by being present at an upper position of 10 nm or less.

It is a figure which shows typically the layer structure and electrode arrangement | positioning of the heterostructure field effect transistor using a nitride semiconductor. It is a figure which shows the HFET structure for reducing the ohmic contact resistance between a source electrode and a barrier layer semiconductor, and reducing the resistance (access resistance) from a source electrode to a channel. It is a figure which shows typically the device structure of HFET using the nitride semiconductor which has a regrowth ohmic structure by this invention. FIG. 4 is a diagram schematically showing a potential structure from a source electrode to a channel in order to show the operation of the structure of FIG. 3 according to the present invention. It is the figure which showed the band structure (position of a conduction band and a valence band) of AlN, GaN, and InN with respect to the charge neutral position (equivalent to a Fermi level). It is a figure which shows the potential shape in the surface vicinity of a nitride semiconductor. In the structure shown in FIG. 3, the regrowth nitride semiconductor (2) is particularly effective when an InN nitride semiconductor having a small band gap, that is, InN, InGaN, InAlN, and InAlGaN are used. FIG. 4 is a diagram schematically showing a device structure of an HFET having a regrown ohmic structure. FIG. 6 is a diagram schematically showing a potential structure from a source electrode 2 to a channel when an InN nitride semiconductor having a small band gap is used as the regrowth nitride semiconductor (2) in the ohmic region. It is the figure which expanded the structure from the source electrode 2 shown in FIG. 7 to the gate electrode 3, and showed the mode of electron distribution typically. It is a figure which shows the specific conditions in the Example of this invention.

(1) Basic Structure and Action According to the Present Invention FIG. 1 schematically shows the layer structure and electrode arrangement of a heterostructure field effect transistor (HFET) using a nitride semiconductor. A state in which a source electrode 2, a gate electrode 3, and a drain electrode 4 are arranged on a barrier layer semiconductor / channel layer semiconductor heterostructure 1 using a semiconductor to form a field effect transistor is shown.

  In FIG. 1, the most common layer structure of a nitride semiconductor is an AlGaN / GaN HFET in which AlGaN is used as a barrier layer semiconductor and GaN is used as a channel layer semiconductor. The condition that acts as a barrier layer and a channel layer is that the band gap of the barrier layer semiconductor is larger than that of the channel layer semiconductor. Generally, if the heterostructure satisfies this condition, the barrier layer semiconductor and the channel layer semiconductor Even if it is a nitride semiconductor other than the above, the device operation of a field effect transistor can be obtained. That is, using AlN, AlGaN, InAlN, InAlGaN, GaN, InGaN, etc. as the barrier layer semiconductor, and using GaN, AlGaN, InN, InGaN, InAlN, InAlGaN, etc. as the channel layer, the band gap of the barrier layer semiconductor is the channel layer semiconductor. For example, AlN / AlGaN, AlGaN / AlGaN, AlGaN / InN, AlGaN / InGaN, GaN / InGaN, GaN / InN, InGaN / InGaN, InGaN / InN, InAlN / InN Various barrier layer semiconductor / channel layer semiconductor heterostructures such as InAlN / InGaN, InAlN / InAlN, InAlGaN / InN, and InAlGaN / InGaN can be formed.

  In FIG. 1, channel electrons exist in the vicinity of the barrier layer semiconductor / channel layer semiconductor heterointerface in the nitride channel layer semiconductor, thereby realizing transistor operation. At this time, electrons injected from the source electrode 2 into the channel reach the channel by overcoming the energy barrier of the nitride barrier layer semiconductor, and the ohmic contact between the source electrode 2 and the barrier layer semiconductor at this time Reducing the resistance and reducing the resistance (access resistance) from the source electrode 2 to the channel is effective for improving the performance of the HFET.

  FIG. 2 shows an HFET structure for reducing the ohmic contact resistance between the source electrode 2 and the barrier layer semiconductor and reducing the resistance (access resistance) from the source electrode 2 to the channel, that is, the source, as described above. In the ohmic region where the electrode 2 and the drain electrode 4 are formed, the barrier layer semiconductor is removed, and a regrowth nitride semiconductor 5 having a band gap smaller than that of the barrier layer semiconductor is stacked instead of the barrier layer semiconductor. 4 schematically shows the structure of an HFET having a regrown ohmic structure in which the drain electrode 4 is formed not on the barrier layer semiconductor but on the regrown nitride semiconductor 5 having a smaller band gap. . Here, generally, the nitride semiconductor 5 in ohmic contact with the source electrode 2 is referred to as “source side nitride semiconductor”, and the nitride semiconductor 5 in ohmic contact with the drain electrode 4 is referred to as “drain side nitride semiconductor”.

  Here, in the structure of FIG. 2, by using a nitride semiconductor of the same material as the channel layer semiconductor as the regrowth nitride semiconductor 5, it is possible to improve the performance of the element. That is, when the HFET structure of FIG. 2 in this case is compared with the HFET structure of FIG. 1, in the HFET of the structure of FIG. 2, the channel layer semiconductor in which the source electrode 2 and the drain electrode 4 have a smaller band gap than the barrier layer semiconductor. 1 is formed on a nitride semiconductor of the same material as that described above, the ohmic contact resistance with the electrode metal is reduced, and the resistance from the source electrode 2 to the channel (access resistance) compared to the HFET structure of FIG. As a result, the device performance is improved in the HFET structure of FIG. 2 (see Non-Patent Document 1 above).

  In the HFET using the nitride semiconductor having the regrowth ohmic structure shown in FIG. 2, in order to further reduce the ohmic contact resistance, an ohmic region (source-side nitride semiconductor) in which the source electrode 2 and the drain electrode 4 are formed is formed. In the region where the rain-side nitride semiconductor is formed), the regrowth nitride semiconductor 5 is not a nitride semiconductor of the same material as the channel layer semiconductor, but a nitride semiconductor having a smaller band gap than the channel layer semiconductor. It is an effective means to form the source electrode 2 and the drain electrode 4 on the regrowth nitride semiconductor 5 by using the laminated (regrown) structure. On the other hand, in this case, the ohmic region is regenerated. A conduction band is formed between the grown nitride semiconductor 5 and the channel layer semiconductor that functions as the channel layer and exists below the gate electrode 3. An edge discontinuity (ie, a band gap discontinuity) is formed, and this conduction band discontinuity becomes a barrier to electron transport. As a result, the access resistance is not reduced, and the characteristics of the HFET are not improved. Therefore, in the nitride semiconductor HFET, it is necessary to develop a new device structure that greatly reduces the ohmic contact resistance and at the same time greatly reduces the access resistance, and as a result, enables high performance.

  FIG. 3 schematically shows a device structure of an HFET using a nitride semiconductor having a regrowth ohmic structure according to the present invention to achieve the above object. In the device structure of FIG. 3, the nitride semiconductor in the ohmic region in which the source electrode 2 and the drain electrode 4 are formed, that is, the source-side nitride semiconductor in ohmic contact with the source electrode, and the drain in ohmic contact with the drain electrode As the side nitride semiconductor, a nitride semiconductor (regrown nitride semiconductor (2)) having a band gap smaller than that of the channel layer semiconductor is used, and the nitride semiconductor in the ohmic region and below the gate electrode 3 are used. The composition gradient nitride semiconductor (regrown composition gradient nitride semiconductor) in which the composition of the nitride semiconductor is continuously changed so that there is no discontinuity of the conduction band edge with the channel layer semiconductor existing in It shows how (1)) is used. As described above, the source-side nitride semiconductor and the nitride channel layer semiconductor and the drain-side nitride semiconductor and the nitride channel layer semiconductor are connected via the composition gradient nitride semiconductor, respectively. Thus, the discontinuity of the semiconductor band gap in the electric path connecting the source electrode 2 and the channel and the drain electrode 4 and the channel is eliminated.

  FIG. 4 schematically shows the potential structure from the source electrode 2 to the channel in order to show the operation of the structure of FIG. 3 according to the present invention. (A) In the structure of FIG. 5 is a comparison of the potential structure from the source electrode 2 to the channel in the structure formed of a nitride semiconductor having a band gap smaller than that of the channel layer semiconductor and (b) the structure of FIG. FIG. 4 shows the conduction band discontinuity (that is, the band gap discontinuity) between the regrown nitride semiconductor 5 and the channel layer semiconductor in the case (a) in the case (b) according to the present invention. As a result, the state in which the access resistance from the source electrode 2 to the channel is reduced is schematically shown. Therefore, as described above, the present invention shown in FIG. 3 can improve the performance of the HFET.

(2) InN-based ohmic structure and operation In the present invention shown in FIG. 3, the nitride semiconductor (source side nitride semiconductor and drain side nitride semiconductor (2) in the ohmic region where the source electrode 2 and the drain electrode 4 are formed As for)), it is advantageous to use InN-based nitride semiconductors having a small band gap, that is, InGaN including InN, InAlN, and InAlGaN in order to reduce ohmic contact resistance. In that case, it is very effective to devise a special device in the structure of FIG. 3 so that the following characteristics of the InN-based nitride semiconductor can be utilized. The structure and operation will be described below.

  FIG. 5 shows the band structure of AlN, GaN, and InN (position of conduction band and valence band) with respect to the charge neutral position (corresponding to the Fermi level). In AlN and GaN, While the charge neutral position exists between the conduction band and the valence band, InN shows that the charge neutral position exists at a position higher than the conduction band. 2).

  FIG. 6 shows the potential shape in the vicinity of the surface of the nitride semiconductor, in the case of (a) AlN-based semiconductor or GaN-based semiconductor, that is, AlN, AlGaN, or GaN, and (b) InN-based semiconductor, That is, in InN, InGaN, InAlN, or InAlGaN, the In composition is large, and as a result, the case where the conduction band exists at a position lower than the charge neutral position is shown for the two cases. In the AlN semiconductor or GaN semiconductor of (a), an energy barrier is formed near the surface, whereas in the InN semiconductor of (b), the conduction band position is higher than the charge neutral position. As a result, the negative energy barrier is formed near the surface. Therefore, in the AlN semiconductor or GaN semiconductor in (a), electrons are depleted near the surface, whereas in the InN semiconductor in (b), electrons accumulate on the surface. In fact, it has also been experimentally reported that a surface charge accumulation layer in which electrons having a high electron concentration are accumulated is formed on the surface of InN (see Non-Patent Document 3). Therefore, the vicinity of the InN surface can be used as a low-resistance conductive layer (surface conductive layer). Of course, due to the presence of the surface charge storage layer, the ohmic contact resistance of the ohmic electrode formed on the InN-based semiconductor is very small.

  7 shows an InN-based nitride semiconductor having a small band gap as the regrowth nitride semiconductor (2) in the ohmic region where the source electrode 2 and the drain electrode 4 are formed in the structure according to the present invention shown in FIG. FIG. 3 schematically shows the device structure of an HFET having a regrowth ohmic structure that is particularly effective when InGaN, InAlN, and InAlGaN including InN are used. Is a special case of the structure. In the structure according to the present invention shown in FIG. 7, in addition to greatly reducing the ohmic contact resistance due to the presence of the surface charge accumulation layer of the InN-based semiconductor, in order to further utilize the effect of high electron concentration in the surface charge accumulation layer, Due to the structure in which the surface position of the InN-based semiconductor (2) exists in the vicinity of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode 3 (above 0 nm or more and 10 nm or less) The state of the structure for minimizing the access resistance from the source electrode 2 to the channel is shown. Hereinafter, the operation of the structure shown in FIG. 7 will be described in more detail.

  FIG. 8 shows an InN-based nitride semiconductor having a small band gap as the regrowth nitride semiconductor (2) in the ohmic region where the source electrode 2 and the drain electrode 4 are formed as shown in FIG. 3 schematically shows the potential structure from the source electrode 2 to the channel when is used. FIG. 8 shows a state in which the ohmic contact resistance is greatly reduced by the presence of the surface charge storage layer of the InN semiconductor (compare with FIG. 4B).

  FIG. 9 is an enlarged view of the structure from the source electrode 2 to the gate electrode 3 shown in FIG. 7 of the present invention, and schematically shows the state of electron distribution. A regrown nitride semiconductor using an InN-based semiconductor. High concentration electrons (surface charge storage layer) are distributed on the surface of (2) and in the vicinity of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor in the channel layer semiconductor existing below the gate electrode 3 A state in which high-concentration channel electrons (two-dimensional electrons) exist is shown. As shown in FIG. 9, in the present invention, the surface position of the regrown InN-based semiconductor (2) is in the vicinity of the position of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode 3 (0 In order to minimize the access resistance from the source electrode 2 to the channel, the high-concentration electron distribution in both the above regions overlaps. The structure is shown. Therefore, according to the present invention shown in FIG. 7, the ohmic contact resistance between the source electrode 2 and the semiconductor layer can be reduced and the resistance (access resistance) from the source electrode 2 to the channel can be reduced. As a result, high performance of the HFET becomes possible, and a high performance nitride semiconductor HFET is realized.

  As described above, the configuration and the operation of the present invention are all shown.

(3) Effect of Embodiment In a heterostructure field effect transistor (HFET) using a nitride semiconductor, the ohmic contact resistance is greatly reduced, and at the same time, the resistance from the source electrode 2 to the channel (access resistance) The following invention is effective to realize a high-performance nitride semiconductor HFET with a device structure that can achieve a high speed and low loss (low power consumption) as a result. .

  That is, as the nitride semiconductor in the ohmic region where the source electrode 2 and the drain electrode 4 are formed, a nitride semiconductor having a smaller band gap than the channel layer semiconductor is used, and the nitride semiconductor in the ohmic region And a layer structure in which the composition of the nitride semiconductor is continuously changed so that there is no discontinuity of the conduction band edge between the channel layer semiconductor existing under the gate electrode 3. By using an HFET using a nitride semiconductor, a high-performance nitride semiconductor HFET is realized.

In particular, in an HFET using a nitride semiconductor having the above structure, In X Ga 1-X N (0.46 ≦ X ≦ 1.0) is used as the nitride semiconductor in the ohmic region where the source electrode 2 and the drain electrode 4 are formed. And the surface position of the In X Ga 1-X N (0.46 ≦ X ≦ 1.0) is more than the position of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode 3. A nitride semiconductor HFET with higher performance can be realized by using an HFET using a nitride semiconductor, characterized in that it exists in an upper position of 0 nm or more and 10 nm or less.

In the HFET structure using the nitride semiconductor shown in FIG. 7, Al XB Ga 1-XBN (0 <XB ≦ 1.0) is used as the barrier layer semiconductor, GaN is used as the channel layer semiconductor, and the regrowth composition gradient nitride semiconductor (1) As In X1 Ga 1-X1 N (X1 is a value that continuously changes within the layer, and 0 ≦ X1 ≦ 1.0), and as a regrown nitride semiconductor (2), In X2 Ga 1-X2 N (X2 Is an HFET structure with a constant value within the range of 0.46 ≦ X2 ≦ 1.0. Here, in In X1 Ga 1-X1 N of the regrowth composition gradient nitride semiconductor (1), GaN of the adjacent channel layer semiconductor and In X2 Ga 1-X2 N of the regrowth nitride semiconductor (2) In any lateral interface, the In composition X1 is continuously changed in the layer so that no conduction band discontinuity occurs, and a composition gradient is provided. In X1 Ga 1-X1 N / GaN X1 = 0, in X2 Ga 1 -X2 N / in X1 Ga 1-X1 N X1 = X2 becomes designed laterally interface have been made in the transverse direction interface.

FIG. 10 shows the In composition (X) dependence of the conduction band energy position of In X Ga 1-X N, and the broken line shows the dependence using linear approximation from the energy position of the conduction band of GaN and InN ( Reference), the solid line is the dependence measured by experiment. When 0.46 ≦ X ≦ 1.0, the conduction band energy position of In X Ga 1-X N is lower than the energy position of the charge neutral point. Therefore, it can be understood that a surface charge accumulation layer is formed in this In composition region. This is the reason why the In composition of 0.46 ≦ X ≦ 1.0 is used in In X2 Ga 1 -X2 N of the regrown nitride semiconductor (2).

In this example, the surface position of In X2 Ga 1-X2 N in the regrowth nitride semiconductor (2) (equal to the surface position of In X1 Ga 1-X1 N in the regrowth composition gradient nitride semiconductor (1)) ) Is less than the position of the Al XB Ga 1-XB N / GaN heterointerface between the barrier layer semiconductor Al XB Ga 1-XBN and the channel layer semiconductor GaN existing below the gate electrode 3. It is designed to exist at an upper position of 10 nm or less. This is a condition required to superimpose the electron distribution near the surface of the regrown nitride semiconductor (2) on the electron distribution of the channel electrons.When the above positional relationship is less than 0 nm, the electron distribution is This is because there is no overlap, and the electron distribution overlap becomes smaller when the thickness exceeds 10 nm. The latter condition is to supply electrons for low resistance to In X1 Ga 1-X1 N of the regrowth composition gradient nitride semiconductor (1) and In X2 Ga 1-X2 N of the regrowth nitride semiconductor (2). This is because even when doping is performed, the distribution width of high-concentration electrons near the surface is at most about 10 nm.

Further, in FIG. 7, the magnitude relationship or ratio between the lateral layer thickness and the longitudinal layer thickness of the In X1 Ga 1 -X1 N layer subjected to the composition gradient of the regrowth composition gradient nitride semiconductor (1) It can be controlled by the growth condition (regrowth condition) of the grown nitride semiconductor, and the lateral layer thickness of the In X1 Ga 1-X1 N layer is controlled to about 1-20 nm or more. It is possible. Here, the lateral layer thickness of the composition gradient layer is such that the In composition X2 of In X2 Ga 1 -X2 N of the regrowth nitride semiconductor (2) is large, and strain or conduction with the GaN of the channel layer When the difference in the position of the band edge is large, the design value of the lateral layer thickness generally increases.

  As this example, an HFET having the following structure in FIG. 7 was produced by the following manufacturing method.

First, as a growth process for forming a laminated structure including a nitride channel layer semiconductor and a nitride barrier layer semiconductor as parts on a substrate by an epitaxial crystal growth method, GaN as a channel layer semiconductor and a layer thickness of 10 nm as a barrier layer semiconductor of Al 0.4 Ga 0.6 N Al 0.4 Ga 0.6 N / GaN heterostructures using, MBE method (MBE: Molecular Beam epitaxy) or MOVPE method (MOVPE: Metal Organic Vapor Phase epitaxy ) sapphire substrate by a crystal growth method such as I grew up.

Next, as an etching process in which the portion of the stacked structure at the position where the composition-graded nitride semiconductor, the source-side nitride semiconductor, and the drain-side nitride semiconductor are formed is removed by dry etching, the source electrode and the drain electrode are Al 0.4 Ga 0.6 N with a layer thickness of 10 nm in the ohmic region to be formed and GaN with a layer thickness of 40 nm below the layer were removed by dry etching.

Next, as a regrowth process for forming a composition-graded nitride semiconductor, a source-side nitride semiconductor, and a drain-side nitride semiconductor by an epitaxial crystal growth method, a composition-graded InGaN with a vertical layer thickness of 10 nm is used as an initial In composition 0, Re-growth was performed by a crystal growth method such as MBE method or MOVPE method as a compositionally-graded InGaN layer having a linear change with a final In composition of 1.0. Under the crystal growth conditions at this time, the lateral layer thickness of the composition gradient InGaN layer was 5 nm. Subsequent to the regrowth of the composition gradient InGaN layer, InN having a vertical layer thickness of 22 nm was regrown by the same crystal growth method. As a result, the InN surface position is 2 nm above the position of the Al 0.4 Ga 0.6 N / GaN heterointerface between Al 0.4 Ga 0.6 N and GaN existing below the gate electrode. became. Here, during the regrowth of the composition-graded InGaN layer and InN layer, Si doping at a concentration of 1 × 10 19 cm −3 was performed as an electron supply for reducing the resistance. After the re-growth, an HFET having the structure shown in FIG. 7 was manufactured by a normal method for manufacturing an HFET. As a result, an excellent high frequency characteristic with a cutoff frequency of 220 GHz was realized in a device having a gate length of 0.05 μm.

Here, the heterostructure composed of the channel layer semiconductor and the barrier layer semiconductor of this embodiment is not only on the sapphire substrate, but also on the SiC (silicon carbide) substrate or Si (silicon) substrate, or on these substrates. The source electrode 2 and the drain electrode can be formed on any substrate such as a formed template substrate such as GaN, AlN, AlGaN, or InGaN, or a free-standing substrate such as GaN, AlN, InN, AlGaN, or InGaN. 4 in X Ga 1-X N (0.46 ≦ X ≦ 1.0) have been used as a nitride semiconductor ohmic region is formed, and the in X Ga 1-X N ( 0.46 ≦ X ≦ 1.0) Layer structure (composition gradient layer) in which the composition of the nitride semiconductor is continuously changed so that there is no band gap discontinuity between the gate electrode 3 and the channel layer semiconductor existing below the gate electrode 3 And the In X Ga The surface position of 1-X N (0.46 ≦ X ≦ 1.0) exists above 0 nm or more and 10 nm or less than the position of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode 3 As long as it has the structural features shown in FIG. 7, all are within the scope of the present invention. Moreover, the structure having the above-described features of the present invention is within the scope of the present invention regardless of the presence or absence of doping as an electron supply for reducing resistance in any part of the HFET structure.

  In this embodiment, AlGaN is used as the barrier layer semiconductor and GaN is used as the channel layer semiconductor. However, AlN, InAlN, and InAlGaN are used as the barrier layer semiconductor, and the band gap of the barrier layer semiconductor is the channel layer semiconductor GaN. FIG. 7 also shows the case where a barrier layer semiconductor / channel layer semiconductor heterostructure of InAlN / GaN and InAlGaN / GaN is formed in addition to AlN / GaN under the condition that it is larger than the above. All structures having the above-described features according to the present invention are within the scope of the present invention.

  In this embodiment, as shown in FIG. 7, the gate electrode 3 is formed immediately above the barrier layer semiconductor layer. However, as a device structure, an insulating film is formed between the gate electrode 3 and the barrier layer semiconductor. Even the so-called insulated gate structure (that is, MIS structure (MIS: Metal-Insulator-Semiconductor)) inserted, all the structures having the above-described features according to the present invention shown in FIG. 7 are within the scope of the present invention. It is.

A structure using Al XC Ga 1-XCN (0 <XC <1.0) as the channel layer semiconductor instead of GaN used as the channel layer semiconductor in Example 1. That is, in the HFET structure using the nitride semiconductor shown in FIG. 7, Al XB Ga 1-XBN (0 <XB ≦ 1.0) is used as the barrier layer semiconductor, and Al XC Ga 1-XCN (0 < X is used as the channel layer semiconductor). XC <1.0, XC <XB), Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N (X11 and X12 are values that change continuously in the layer) as regrown composition graded nitride semiconductor (1) In the range of 0 ≦ X11, X12 ≦ 1.0), In X2 Ga 1-X2 N as the regrown nitride semiconductor (2) (X2 is a constant value within the range of 0.46 ≦ X2 ≦ 1.0) HFET structure. Here, in Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N of the regrowth composition graded nitride semiconductor (1), Al XC Ga 1-XCN and the regrowth nitride of the adjacent channel layer semiconductor Al X11 Ga 1-X11 N / In X12 Ga 1-X12 of the regrowth composition graded nitride semiconductor (1) at any lateral interface with the In X2 Ga 1-X2 N of the semiconductor layer (2) Also at the N interface, the Al composition X11 and the In composition X12 are continuously changed in the layer so as not to cause a conduction band discontinuity, and a composition gradient is provided, and Al X11 Ga 1-X11 N / Al XC Ga 1-XC X11 = XC at the N lateral interface, In X2 Ga 1-X2 N / In X12 Ga 1-X12 N X12 = X2 at the lateral interface, and regrowth composition gradient nitride semiconductor (1) In this case, X11 = X12 = 0 is designed at the Al X11 Ga 1 -X11 N / In X12 Ga 1 -X12 N interface. Here, the reason why the In composition of 0.46 ≦ X ≦ 1.0 is used in In X2 Ga 1 -X2 N of the regrowth nitride semiconductor layer 2 is exactly the same as in Example 1, and the contents are shown in FIG. ing.

In this example, the surface position of In X2 Ga 1-X2 N in the regrowth nitride semiconductor (2) (equal to the surface position of In X1 Ga 1-X1 N in the regrowth composition gradient nitride semiconductor (1)) ) Between the barrier layer semiconductor Al XB Ga 1 -XB N and the channel layer semiconductor Al XC Ga 1 -XCN existing below the gate electrode 3, but Al XB Ga 1 -XB N / Al XC Ga 1 It is designed to exist at an upper position of 0 nm or more and 10 nm or less than the position of the -XCN hetero interface. This is a condition required to superimpose the electron distribution near the surface of the regrown nitride semiconductor (2) on the electron distribution of the channel electrons.When the above positional relationship is less than 0 nm, the electron distribution is This is because there is no overlap, and the electron distribution overlap becomes smaller when the thickness exceeds 10 nm. The latter condition is that Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N of regrowth composition graded nitride semiconductor (1) and In X2 Ga 1-X2 N of regrowth nitride semiconductor (2), This is due to the fact that the distribution width of high-concentration electrons in the vicinity of the surface is only about 10 nm even when doping is performed as an electron supply for resistance reduction.

In FIG. 7, the lateral layer thickness and the longitudinal layer thickness of the Al X11 Ga 1 -X11 N / In X12 Ga 1 -X12 N layer subjected to the composition gradient of the regrowth composition gradient nitride semiconductor (1) are shown. The magnitude relation or ratio can be controlled by the deposition condition (regrowth condition) of the regrowth composition gradient nitride semiconductor, and the lateral relationship of the Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N layer can be controlled. It is possible to control the directional layer thickness to a layer thickness of about 1-20 nm or more. Here, the lateral layer thickness of the composition gradient layer is such that the In composition X2 of In X2 Ga 1 -X2 N of the regrowth nitride semiconductor (2) is large, and the Al XC Ga 1 -XCN of the channel layer If the distortion or the difference in the conduction band edge position is large, the lateral layer thickness design is also generally large.

  As this example, an HFET having the following structure in FIG. 7 was produced by the following manufacturing method. Also in this case, like the first embodiment, the growth process, the etching process, and the regrowth process described in claim 3 are used.

First, an Al 0.4 Ga 0.6 N / Al 0.1 Ga 0.9 N heterostructure using Al 0.1 Ga 0.9 N as a channel layer semiconductor and Al 0.4 Ga 0.6 N with a thickness of 10 nm as a barrier layer semiconductor is fabricated by MBE (MBE: Molecular The crystal was grown on a sapphire substrate by a crystal growth method such as Beam Epitaxy or MOVPE (MOVPE: Metal Organic Vapor Phase Epitaxy). Next, Al 0.4 Ga 0.6 N with a layer thickness of 10 nm and Al 0.1 Ga 0.9 N with a layer thickness of 40 nm below the ohmic region where the source electrode 2 and the drain electrode 4 are formed are removed by dry etching. A compositionally graded Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N layer having a longitudinal layer thickness of 10 nm, an initial Al composition of 0.1, and a final Al composition of 0 nm, a linearly varying 5 nm compositionally graded AlGaN layer, and Re-growth was performed by a crystal growth method such as the MBE method or the MOVPE method as a 5 nm composition gradient InGaN layer having a linear change of initial In composition 0 and final In composition 1.0. Under the crystal growth conditions at this time, the lateral thickness of the composition gradient AlGaN / InGaN layer was 5 nm. Subsequent to the regrowth of the composition-graded AlGaN / InGaN layer, InN having a longitudinal layer thickness of 22 nm was regrown by the same crystal growth method. As a result, the InN surface position is 2 nm higher than the position of the Al 0.4 Ga 0.6 N / Al 0.1 Ga 0.9 N heterointerface between Al 0.4 Ga 0.6 N and GaN existing below the gate electrode 3. It became the structure which exists in. Here, during the regrowth of the composition gradient AlGaN / InGaN layer and InN layer, Si doping with a concentration of 1 × 10 19 cm −3 was performed as an electron supply for reducing the resistance. After the re-growth, an HFET having the structure shown in FIG. 7 was fabricated by a normal fabrication method of HFET. As a result, an excellent high frequency characteristic with a cutoff frequency of 180 GHz was realized in a device having a gate length of 0.05 μm.

  Compared to Example 1 in which AlGaN is used for the channel layer and Example 1 in which GaN is used for the channel layer, although the high frequency characteristics are inferior to Example 1, the blocking withstand voltage is increased by 20%. Advantages were confirmed in Example 2.

Here, the heterostructure composed of the channel layer semiconductor and the barrier layer semiconductor of this embodiment is not only on the sapphire substrate, but also on the SiC (silicon carbide) substrate or Si (silicon) substrate, or on these substrates. The source electrode 2 and the drain electrode can be formed on any substrate such as a formed template substrate such as GaN, AlN, AlGaN, or InGaN, or a free-standing substrate such as GaN, AlN, InN, AlGaN, or InGaN. 4 in X Ga 1-X N (0.46 ≦ X ≦ 1.0) have been used as a nitride semiconductor ohmic region is formed, and the in X Ga 1-X N ( 0.46 ≦ X ≦ 1.0) Layer structure (composition gradient layer) in which the composition of the nitride semiconductor is continuously changed so that there is no band gap discontinuity between the gate electrode 3 and the channel layer semiconductor existing below the gate electrode 3 And the In X Ga The surface position of 1-X N (0.46 ≦ X ≦ 1.0) exists above 0 nm or more and 10 nm or less than the position of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode 3 As long as it has the structural features shown in FIG. 7, all are within the scope of the present invention. Moreover, the structure having the above-described features of the present invention is within the scope of the present invention regardless of the presence or absence of doping as an electron supply for reducing resistance in any part of the HFET structure.

  In this embodiment, AlGaN is used as the barrier layer semiconductor and AlGaN is used as the channel layer semiconductor. However, AlN, InAlN, and InAlGaN are used as the barrier layer semiconductor, and the band gap of the barrier layer semiconductor is AlGaN. FIG. 7 also shows a case where a barrier layer semiconductor / channel layer semiconductor heterostructure of InAlN / AlGaN and InAlGaN / AlGaN is formed in addition to AlN / AlGaN under the condition that it is larger than that of All structures having the above-described features according to the present invention are within the scope of the present invention.

  In this embodiment, as shown in FIG. 7, the gate electrode 3 is formed immediately above the barrier layer semiconductor layer. However, as a device structure, an insulating film is formed between the gate electrode 3 and the barrier layer semiconductor. Even the so-called insulated gate structure (that is, MIS structure (MIS: Metal-Insulator-Semiconductor)) inserted, all the structures having the above-described features according to the present invention shown in FIG. 7 are within the scope of the present invention. It is.

A structure using In XC Ga 1-XCN (0 <XC ≦ 1.0) as a channel layer semiconductor instead of GaN used as a channel layer semiconductor in Example 1. That is, in the HFET structure using the nitride semiconductor shown in FIG. 7, Al XB Ga 1-XBN (0 <XB ≦ 1.0) is used as the barrier layer semiconductor, and In XC Ga 1-XCN (0 < X ) is used as the channel layer semiconductor. XC ≦ 1.0), In X1 Ga 1-X1 N as regrown composition graded nitride semiconductor (1) (X1 is a value that continuously changes in the layer, and 0 ≦ X1 ≦ 1.0), regrown nitriding HFET structure with In X2 Ga 1-X2 N (X2 is a constant value within the range of 0.46 ≦ X2 ≦ 1.0) as the physical semiconductor (2). Here, in In X1 Ga 1 -X1 N of the regrowth composition gradient nitride semiconductor (1), In XC Ga 1 -XCN of the adjacent channel layer semiconductor and In X2 Ga 1 of the regrowth nitride semiconductor layer 2 In X1 Ga 1 , the In composition X1 is continuously changed in the layer so that no conduction band discontinuity occurs at any lateral interface with -X2N. -X1 N / in XC Ga 1- XC N lateral surface in X1 = XC, in X2 Ga 1 -X2 N / in X1 Ga 1-X1 N lateral surface in X1 = X2 becomes designs have been made. Here, the reason why the In composition of 0.46 ≦ X ≦ 1.0 is used in In X2 Ga 1 -X2 N of the regrowth nitride semiconductor layer 2 is exactly the same as in Example 1, and the contents are shown in FIG. ing.

In this example, the surface position of In X2 Ga 1-X2 N in the regrowth nitride semiconductor (2) (equal to the surface position of In X1 Ga 1-X1 N in the regrowth composition gradient nitride semiconductor (1)) ) Between the barrier layer semiconductor Al XB Ga 1-XB N and the channel layer semiconductor In XC Ga 1-XC N existing below the gate electrode 3, but Al XB Ga 1-XB N / In XC Ga 1 It is designed to exist at an upper position of 0 nm or more and 10 nm or less than the position of the -XCN hetero interface. This is a condition required to superimpose the electron distribution near the surface of the regrown nitride semiconductor (2) on the electron distribution of the channel electrons.When the above positional relationship is less than 0 nm, the electron distribution is This is because there is no overlap, and the electron distribution overlap becomes smaller when the thickness exceeds 10 nm. The latter condition is to supply electrons for low resistance to In X1 Ga 1-X1 N of the regrowth composition gradient nitride semiconductor (1) and In X2 Ga 1-X2 N of the regrowth nitride semiconductor (2). This is because even when doping is performed, the distribution width of high-concentration electrons near the surface is at most about 10 nm.

Further, in FIG. 7, the magnitude relationship or ratio between the lateral layer thickness and the longitudinal layer thickness of the In X1 Ga 1 -X1 N layer subjected to the composition gradient of the regrowth composition gradient nitride semiconductor (1) It can be controlled by the growth composition gradient nitride semiconductor deposition conditions (regrowth conditions), and the lateral thickness of the In X1 Ga 1-X1 N layer is set to about 1-20 nm or more. It is possible to control. Here, the lateral layer thickness of the composition gradient layer is such that the In composition X2 of In X2 Ga 1 -X2 N of the regrowth nitride semiconductor (2) is large, and strain or conduction with the InGaN of the channel layer is large. If the band edge position is significantly different, the lateral layer thickness design is generally larger.

  As this example, an HFET having the following structure in FIG. 7 was produced by the following manufacturing method. Also in this case, like the first embodiment, the growth process, the etching process, and the regrowth process described in claim 3 are used.

First, an Al 0.4 Ga 0.6 N / In 0.2 Ga 0.8 N heterostructure using In 0.4 Ga 0.6 N as a channel layer semiconductor and Al 0.4 Ga 0.6 N with a thickness of 10 nm as a barrier layer semiconductor is fabricated by MBE (MBE: Molecular The crystal was grown on a sapphire substrate by a crystal growth method such as Beam Epitaxy or MOVPE (MOVPE: Metal Organic Vapor Phase Epitaxy). Next, Al 0.4 Ga 0.6 N with a layer thickness of 10 nm and In 0.2 Ga 0.8 N with a layer thickness of 40 nm below the ohmic region where the source electrode 2 and the drain electrode 4 are formed are removed by dry etching. Then, a composition-graded InGaN having a vertical layer thickness of 10 nm was regrown by a crystal growth method such as MBE or MOVPE as a linearly-graded composition-graded InGaN layer having an initial In composition of 0.2 and a final In composition of 1.0. Under the crystal growth conditions at this time, the lateral layer thickness of the composition gradient InGaN layer was 5 nm. Subsequent to the regrowth of the composition gradient InGaN layer, InN having a vertical layer thickness of 22 nm was regrown by the same crystal growth method. As a result, the InN surface position is 2 <2> higher than the position of the Al 0.4 Ga 0.6 N / In 0.2 Ga 0.8 N heterointerface between Al 0.4 Ga 0.6 N and In 0.2 Ga 0.8 N existing below the gate electrode 3. The structure was present at a position above nm. Here, during the regrowth of the composition-graded InGaN layer and InN layer, Si doping at a concentration of 1 × 10 19 cm −3 was performed as an electron supply for reducing the resistance. After the re-growth, an HFET having the structure shown in FIG. 7 was manufactured by a normal method for manufacturing an HFET. As a result, an excellent high frequency characteristic with a cutoff frequency of 240 GHz was realized in a device having a gate length of 0.05 μm.

  Compared with Example 1 in which InGaN is used for the channel layer and Example 1 in which GaN is used for the channel layer, this Example 3 has the disadvantage that stricter control of crystal growth conditions is required. However, it was confirmed that the high frequency characteristic was superior to that of Example 1.

Here, the heterostructure composed of the channel layer semiconductor and the barrier layer semiconductor of this embodiment is not only on the sapphire substrate, but also on the SiC (silicon carbide) substrate or Si (silicon) substrate, or on these substrates. The source electrode 2 and the drain electrode can be formed on any substrate such as a formed template substrate such as GaN, AlN, AlGaN, or InGaN, or a free-standing substrate such as GaN, AlN, InN, AlGaN, or InGaN. 4 in X Ga 1-X N (0.46 ≦ X ≦ 1.0) have been used as a nitride semiconductor ohmic region is formed, and the in X Ga 1-X N ( 0.46 ≦ X ≦ 1.0) Layer structure (composition gradient layer) in which the composition of the nitride semiconductor is continuously changed so that there is no band gap discontinuity between the gate electrode 3 and the channel layer semiconductor existing below the gate electrode 3 And the In X Ga The surface position of 1-X N (0.46 ≦ X ≦ 1.0) exists above 0 nm or more and 10 nm or less than the position of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode 3 As long as it has the structural features shown in FIG. 7, all are within the scope of the present invention. Moreover, the structure having the above-described features of the present invention is within the scope of the present invention regardless of the presence or absence of doping as an electron supply for reducing resistance in any part of the HFET structure.

  In this example, AlGaN is used as the barrier layer semiconductor and InGaN is used as the channel layer semiconductor. However, the band gap of the barrier layer semiconductor is increased by using AlN, AlGaN, GaN, InAlN, and InAlGaN as the barrier layer semiconductor. Barrier layer semiconductor / channel layer semiconductor heterogeneous AlN / InGaN, AlGaN / InGaN, GaN / InGaN, InGaN / InGaN, InAlN / InGaN, InAlGaN / InGaN under the condition that it is larger than that of channel layer semiconductor InGaN Even if the structure is constructed, all structures having the above-described features according to the present invention shown in FIG. 7 are within the scope of the present invention.

  In this embodiment, as shown in FIG. 7, the gate electrode 3 is formed immediately above the barrier layer semiconductor layer. However, as a device structure, an insulating film is formed between the gate electrode 3 and the barrier layer semiconductor. Even the so-called insulated gate structure (that is, MIS structure (MIS: Metal-Insulator-Semiconductor)) inserted, all the structures having the above-described features according to the present invention shown in FIG. 7 are within the scope of the present invention. It is.

The following structure comprising Example 1 as its special case. That is, in the HFET structure using the nitride semiconductor shown in FIG. 3, Al XB Ga 1-XBN (0 <XB ≦ 1.0) is used as the barrier layer semiconductor, GaN is used as the channel layer semiconductor, and the regrowth composition gradient nitride semiconductor ( 1) In X1 Ga 1-X1 N (X1 is a value that continuously changes within the layer, and 0 ≦ X1 ≦ 1.0), and regrowth nitride semiconductor (2) In X2 Ga 1-X2 N (X2 is a constant value within the layer, and 0 <X2 ≦ 1.0) HFET structure. Here, in In X1 Ga 1 -X1 N of the regrowth composition graded nitride semiconductor (1), either GaN of the adjacent channel layer semiconductor or In X2 Ga 1 -X2 N of the regrowth nitride semiconductor layer 2 At the lateral interface, the In composition X1 is continuously changed in the layer so that no conduction band discontinuity occurs, and a composition gradient is provided, and the In X1 Ga 1-X1 N / GaN lateral X1 = 0, in X2 Ga 1 -X2 N / in X1 Ga 1-X1 N X1 = X2 becomes designed laterally interface have been made in the direction interface.

Further, in FIG. 3, the magnitude relationship or ratio between the lateral layer thickness and the longitudinal layer thickness of the In X1 Ga 1 -X1 N layer subjected to the composition gradient of the regrowth composition gradient nitride semiconductor (1) It can be controlled by the growth composition gradient nitride semiconductor deposition conditions (regrowth conditions), and the lateral thickness of the In X1 Ga 1-X1 N layer is set to about 1-20 nm or more. It is possible to control. Here, the lateral layer thickness of the composition gradient layer is such that the In composition X2 of In X2 Ga 1 -X2 N of the regrowth nitride semiconductor (2) is large, and strain or conduction with the GaN of the channel layer If the band edge position is significantly different, the lateral layer thickness design is generally larger.

  As this example, an HFET having the following structure in FIG. 3 was produced by the following manufacturing method. Also in this case, like the first embodiment, the growth process, the etching process, and the regrowth process described in claim 3 are used.

First, an Al 0.4 Ga 0.6 N / GaN heterostructure using GaN as the channel layer semiconductor and Al 0.4 Ga 0.6 N with a thickness of 10 nm as the barrier layer semiconductor is fabricated by MBE (MBE: Molecular Beam Epitaxy) or MOVPE (MOVPE) : Grown on sapphire substrate by crystal growth method such as Metal Organic Vapor Phase Epitaxy). Next, after removing Al 0.4 Ga 0.6 N having a layer thickness of 10 nm and GaN having a layer thickness of 20 nm below the ohmic region in which the source electrode 2 and the drain electrode 4 are formed by a dry etching method, a vertical direction layer is formed. The compositionally-graded InGaN having a thickness of 10 nm was regrown by a crystal growth method such as MBE or MOVPE as a linearly-graded compositionally-graded InGaN layer having an initial In composition of 0 and a final In composition of 0.4. Under the crystal growth conditions at this time, the lateral layer thickness of the composition gradient InGaN layer was 5 nm. Subsequent to the regrowth of the composition-graded InGaN layer, In 0.4 Ga 0.6 N having a vertical layer thickness of 30 nm was regrown by the same crystal growth method. As a result, the surface position of In 0.4 Ga 0.6 N was 10 nm higher than the surface position of Al 0.4 Ga 0.6 N existing below the gate electrode 3. Here, during the regrowth of the composition-graded InGaN layer and In 0.4 Ga 0.6 N layer, Si doping at a concentration of 1 × 10 19 cm −3 was performed as an electron supply for reducing the resistance. After the re-growth, an HFET having the structure shown in FIG. 3 was fabricated by a normal fabrication method of HFET. As a result, an excellent high frequency characteristic with a cutoff frequency of 200 GHz was realized in a device having a gate length of 0.05 μm.

Example 4 in which In 0.4 Ga 0.6 N was used for the nitride semiconductor layer in the ohmic region for forming the source electrode 2 and the drain electrode 4, and InN was used for the corresponding nitride semiconductor layer, and its surface position Compared with Example 1 in which special conditions are applied to the above, there is a disadvantage that the high-frequency characteristics are inferior to Example 1, but in Example 4, the reconfiguration required in Example 1 is present. There is an advantage that strict control of crystal growth conditions including growth layer thickness control is relaxed.

Here, the heterostructure composed of the channel layer semiconductor and the barrier layer semiconductor of this embodiment is not only on the sapphire substrate, but also on the SiC (silicon carbide) substrate or Si (silicon) substrate, or on these substrates. The source electrode 2 and the drain electrode can be formed on any substrate such as a formed template substrate such as GaN, AlN, AlGaN, or InGaN, or a free-standing substrate such as GaN, AlN, InN, AlGaN, or InGaN. In X Ga 1-X N (0 <X ≦ 1.0) is used as the nitride semiconductor in the ohmic region where 4 is formed, and In X Ga 1-X N (0 <X ≦ 1.0) Layer structure (composition gradient layer) in which the composition of the nitride semiconductor is continuously changed so that there is no band gap discontinuity between the gate electrode 3 and the channel layer semiconductor existing below the gate electrode 3 As long as it has It is within the range. Moreover, the structure having the above-described features of the present invention is within the scope of the present invention regardless of the presence or absence of doping as an electron supply for reducing resistance in any part of the HFET structure.

  In this embodiment, AlGaN is used as the barrier layer semiconductor and GaN is used as the channel layer semiconductor. However, AlN, InAlN, and InAlGaN are used as the barrier layer semiconductor, and the band gap of the barrier layer semiconductor is the channel layer semiconductor GaN. In addition to AlN / GaN, a barrier layer semiconductor / channel layer semiconductor heterostructure consisting of InAlN / GaN and InAlGaN / GaN is also shown in FIG. All structures having the above-described features according to the present invention are within the scope of the present invention.

  In this embodiment, as shown in FIG. 3, the gate electrode 3 is formed immediately above the barrier layer semiconductor layer. However, as a device structure, an insulating film is formed between the gate electrode 3 and the barrier layer semiconductor. Even the inserted so-called insulated gate structure (that is, MIS structure (MIS: Metal-Insulator-Semiconductor)), all the structures having the above-described features according to the present invention shown in FIG. 3 are all within the scope of the present invention. It is.

In the following structure including Example 2 as a special case, Al XC Ga 1-XCN (0 <XC <1.0) is used as the channel layer semiconductor instead of GaN used as the channel layer semiconductor in Example 4. Structure using. That is, in the HFET structure using the nitride semiconductor shown in FIG. 3, Al XB Ga 1-XBN (0 <XB ≦ 1.0) as the barrier layer semiconductor and Al XC Ga 1-XCN (0 < XC <1.0, XC <XB), Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N (X11 and X12 are values that vary continuously in the layer) In the range of 0 ≦ X11, X12 ≦ 1.0), In X2 Ga 1-X2 N as the regrown nitride semiconductor (2) (X2 is a constant value within the range 0 ≦ X2 ≦ 1.0) HFET structure. Here, in Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N of the regrowth composition graded nitride semiconductor (1), Al XC Ga 1-XCN and the regrowth nitride of the adjacent channel layer semiconductor At any lateral interface of the semiconductor layer 2 with In X2 Ga 1 -X2 N, the Al X11 Ga 1 -X11 N / In X12 Ga 1 -X12 N interface of the regrowth composition graded nitride semiconductor (1) However, the Al composition X11 and the In composition X12 are continuously changed in the layer so that the conduction band discontinuity does not occur, and a composition gradient is provided, and Al X11 Ga 1-X11 N / Al XC X11 = XC at the Ga 1-XC N lateral interface, X12 = X2 at the In X2 Ga 1-X2 N / In X12 Ga 1-X12 N lateral interface, and Al of the regrowth composition gradient nitride semiconductor (1) X11 Ga 1 -X11 N / In The X12 Ga 1 -X12 N interface is designed so that X11 = X12 = 0.

In FIG. 3, the lateral layer thickness and the longitudinal layer thickness of the Al X11 Ga 1 -X11 N / In X12 Ga 1 -X12 N layer subjected to the composition gradient of the regrowth composition gradient nitride semiconductor (1) are shown. The magnitude relation or ratio can be controlled by the deposition condition (regrowth condition) of the regrowth composition gradient nitride semiconductor, and the lateral relationship of the Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N layer can be controlled. It is possible to control the directional layer thickness to a layer thickness of about 1-20 nm or more. Here, the lateral layer thickness of the composition gradient layer is such that the In composition X2 of In X2 Ga 1 -X2 N of the regrowth nitride semiconductor (2) is large, and the Al XC Ga 1 -XCN of the channel layer If the distortion or the difference in the conduction band edge position is large, the lateral layer thickness design is also generally large.

  As this example, an HFET having the following structure in FIG. 3 was produced by the following manufacturing method. Also in this case, like the first embodiment, the growth process, the etching process, and the regrowth process described in claim 3 are used.

First, an Al 0.4 Ga 0.6 N / Al 0.1 Ga 0.9 N heterostructure using Al 0.1 Ga 0.9 N as a channel layer semiconductor and Al 0.4 Ga 0.6 N with a thickness of 10 nm as a barrier layer semiconductor is fabricated by MBE (MBE: Molecular The crystal was grown on a sapphire substrate by a crystal growth method such as Beam Epitaxy or MOVPE (MOVPE: Metal Organic Vapor Phase Epitaxy). Next, Al 0.4 Ga 0.6 N having a layer thickness of 10 nm and Al 0.1 Ga 0.9 N having a layer thickness of 20 nm below the ohmic region where the source electrode 2 and the drain electrode 4 are formed are removed by dry etching. A compositionally graded Al X11 Ga 1-X11 N / In X12 Ga 1-X12 N layer having a longitudinal layer thickness of 10 nm, an initial Al composition of 0.1, and a final Al composition of 0 nm, a linearly varying 5 nm compositionally graded AlGaN layer, and Re-growth was performed by a crystal growth method such as the MBE method or the MOVPE method as a 5 nm composition gradient InGaN layer with a linear change of initial In composition 0 and final In composition 0.4. Under the crystal growth conditions at this time, the lateral thickness of the composition gradient AlGaN / InGaN layer was 5 nm. Subsequent to the regrowth of the composition-graded AlGaN / InGaN layer, In 0.4 Ga 0.6 N having a vertical layer thickness of 30 nm was regrown by the same crystal growth method. As a result, the surface position of In 0.4 Ga 0.6 N was 10 nm higher than the surface position of Al 0.4 Ga 0.6 N existing below the gate electrode 3. Here, during the regrowth of the composition-graded AlGaN / InGaN layer and In 0.4 Ga 0.6 N layer, Si doping at a concentration of 1 × 10 19 cm −3 was performed as an electron supply for reducing the resistance. After the re-growth, an HFET having the structure shown in FIG. 7 was manufactured by the usual method for manufacturing an HFET. As a result, an excellent high frequency characteristic with a cutoff frequency of 160 GHz was realized in a device having a gate length of 0.05 μm.

Example 5 in which In 0.4 Ga 0.6 N was used for the nitride semiconductor layer in the ohmic region for forming the source electrode 2 and the drain electrode 4, and InN was used for the corresponding nitride semiconductor layer, and its surface position Compared with Example 2 in which special conditions are applied to the above, there is a disadvantage that the high frequency characteristics are inferior to Example 2, but in Example 5, the re-requirement required in Example 2 is present. There is an advantage that strict control of crystal growth conditions including growth layer thickness control is relaxed.

Here, the heterostructure composed of the channel layer semiconductor and the barrier layer semiconductor of this embodiment is not only on the sapphire substrate, but also on the SiC (silicon carbide) substrate or Si (silicon) substrate, or on these substrates. The source electrode 2 and the drain electrode can be formed on any substrate such as a formed template substrate such as GaN, AlN, AlGaN, or InGaN, or a free-standing substrate such as GaN, AlN, InN, AlGaN, or InGaN. 4 in X Ga 1-X N (0 ≦ X ≦ 1.0) have been used as a nitride semiconductor ohmic region is formed, and the in X Ga 1-X N ( 0 ≦ X ≦ 1.0) Layer structure (composition gradient layer) in which the composition of the nitride semiconductor is continuously changed so that there is no band gap discontinuity between the gate electrode 3 and the channel layer semiconductor existing below the gate electrode 3 As long as it has It is within the range. Moreover, the structure having the above-described features of the present invention is within the scope of the present invention regardless of the presence or absence of doping as an electron supply for reducing resistance in any part of the HFET structure.

  In this embodiment, AlGaN is used as the barrier layer semiconductor and AlGaN is used as the channel layer semiconductor. However, AlN, InAlN, and InAlGaN are used as the barrier layer semiconductor, and the band gap of the barrier layer semiconductor is AlGaN. In addition to AlN / AlGaN, a barrier layer semiconductor / channel layer semiconductor heterostructure consisting of InAlN / AlGaN and InAlGaN / AlGaN is also shown in FIG. All structures having the above-described features according to the present invention are within the scope of the present invention.

  In this embodiment, as shown in FIG. 3, the gate electrode 3 is formed immediately above the barrier layer semiconductor layer. However, as a device structure, an insulating film is formed between the gate electrode 3 and the barrier layer semiconductor. Even the inserted so-called insulated gate structure (that is, MIS structure (MIS: Metal-Insulator-Semiconductor)), all the structures having the above-described features according to the present invention shown in FIG. 3 are all within the scope of the present invention. It is.

In XC Ga 1-XCN (0 <XC ≦ 1.0) as a channel layer semiconductor, instead of GaN used as a channel layer semiconductor in Example 4 with the following structure including Example 3 as its special case Structure using. That is, in the HFET structure using the nitride semiconductor shown in FIG. 3, Al XB Ga 1-XBN (0 <XB ≦ 1.0) is used as the barrier layer semiconductor, and In XC Ga 1-XCN (0 < X ) is used as the channel layer semiconductor. XC ≦ 1.0), In X1 Ga 1-X1 N as regrowth composition graded nitride semiconductor (1) (X1 is a value that continuously changes in the layer, and 0 <X1 ≦ 1.0), regrowth nitridation HFET structure with In X2 Ga 1-X2 N (X2 is a constant value within the range of 0 <X2 ≦ 1.0) as the physical semiconductor (2). Here, in In X1 Ga 1 -X1 N of the regrowth composition gradient nitride semiconductor (1), In XC Ga 1 -XCN of the adjacent channel layer semiconductor and In X2 Ga 1 of the regrowth nitride semiconductor layer 2 In X1 Ga 1 , the In composition X1 is continuously changed in the layer so that no conduction band discontinuity occurs at any lateral interface with -X2N. -X1 N / in XC Ga 1- XC N lateral surface in X1 = XC, in X2 Ga 1 -X2 N / in X1 Ga 1-X1 N lateral surface in X1 = X2 becomes designs have been made.

Further, in FIG. 3, the magnitude relationship or ratio between the lateral layer thickness and the longitudinal layer thickness of the In X1 Ga 1 -X1 N layer subjected to the composition gradient of the regrowth composition gradient nitride semiconductor (1) It can be controlled by the growth composition gradient nitride semiconductor deposition conditions (regrowth conditions), and the lateral thickness of the In X1 Ga 1-X1 N layer is set to about 1-20 nm or more. It is possible to control. Here, the lateral layer thickness of the composition gradient layer is such that the In composition X2 of In X2 Ga 1 -X2 N of the regrowth nitride semiconductor (2) is large, and strain or conduction with the InGaN of the channel layer is large. If the band edge position is significantly different, the lateral layer thickness design is generally larger.

  As this example, an HFET having the following structure in FIG. 3 was produced by the following manufacturing method. Also in this case, like the first embodiment, the growth process, the etching process, and the regrowth process described in claim 3 are used.

First, an Al 0.4 Ga 0.6 N / In 0.2 Ga 0.8 N heterostructure using In 0.4 Ga 0.6 N as a channel layer semiconductor and Al 0.4 Ga 0.6 N with a thickness of 10 nm as a barrier layer semiconductor is fabricated by MBE (MBE: Molecular The crystal was grown on a sapphire substrate by a crystal growth method such as Beam Epitaxy or MOVPE (MOVPE: Metal Organic Vapor Phase Epitaxy). Next, Al 0.4 Ga 0.6 N with a layer thickness of 10 nm and In 0.2 Ga 0.8 N with a layer thickness of 20 nm below the ohmic region where the source electrode 2 and the drain electrode 4 are formed are removed by dry etching. Then, a composition-graded InGaN having a vertical layer thickness of 10 nm was regrown by a crystal growth method such as MBE or MOVPE as a linearly-graded composition-graded InGaN layer having an initial In composition of 0.2 and a final In composition of 0.4. Under the crystal growth conditions at this time, the lateral layer thickness of the composition gradient InGaN layer was 5 nm. Subsequent to the regrowth of the composition-graded InGaN layer, In 0.4 Ga 0.6 N having a vertical layer thickness of 30 nm was regrown by the same crystal growth method. As a result, the surface position of In 0.4 Ga 0.6 N was 10 nm higher than the surface position of Al 0.4 Ga 0.6 N existing below the gate electrode 3. Here, during the regrowth of the composition-graded InGaN layer and In 0.4 Ga 0.6 N layer, Si doping at a concentration of 1 × 10 19 cm −3 was performed as an electron supply for reducing the resistance. After the re-growth, an HFET having the structure shown in FIG. 7 was manufactured by a normal method for manufacturing an HFET. As a result, an excellent high frequency characteristic with a cutoff frequency of 220 GHz was realized in a device having a gate length of 0.05 μm.

Example 6 in which In 0.4 Ga 0.6 N was used for the nitride semiconductor layer in the ohmic region for forming the source electrode 2 and the drain electrode 4, and InN was used for the corresponding nitride semiconductor layer, and its surface position Compared with Example 3 in which special conditions were applied to this example, although there is a disadvantage that the high-frequency characteristics are inferior to Example 3, the present Example 6 requires a reconstitution that was required in Example 3. There is an advantage that strict control of crystal growth conditions including growth layer thickness control is relaxed.

Here, the heterostructure composed of the channel layer semiconductor and the barrier layer semiconductor of this embodiment is not only on the sapphire substrate, but also on the SiC (silicon carbide) substrate or Si (silicon) substrate, or on these substrates. The source electrode 2 and the drain electrode can be formed on any substrate such as a formed template substrate such as GaN, AlN, AlGaN, or InGaN, or a free-standing substrate such as GaN, AlN, InN, AlGaN, or InGaN. In X Ga 1-X N (0 <X ≦ 1.0) is used as the nitride semiconductor in the ohmic region where 4 is formed, and In X Ga 1-X N (0 <X ≦ 1.0) Layer structure (composition gradient layer) in which the composition of the nitride semiconductor is continuously changed so that there is no band gap discontinuity between the gate electrode 3 and the channel layer semiconductor existing below the gate electrode 3 And the In X Ga 1-X N The surface position of (0 <X ≦ 1.0) exists at an upper position of 0 nm or more and 10 nm or less than the position of the heterointerface between the barrier layer semiconductor and the channel layer semiconductor existing below the gate electrode 3. As long as it has the characteristics of the structure shown in FIG. In addition, the structure having the above-described features of the present invention is within the scope of the present invention regardless of the presence or absence of doping as an electron supply for reducing resistance in any part of the HFET structure.

  In this example, AlGaN is used as the barrier layer semiconductor and InGaN is used as the channel layer semiconductor. However, the band gap of the barrier layer semiconductor is increased by using AlN, AlGaN, GaN, InAlN, and InAlGaN as the barrier layer semiconductor. Barrier layer semiconductor / channel layer semiconductor heterogeneous AlN / InGaN, AlGaN / InGaN, GaN / InGaN, InGaN / InGaN, InAlN / InGaN, InAlGaN / InGaN under the condition that it is larger than that of channel layer semiconductor InGaN Even if the structure is constructed, all structures having the above-described features according to the present invention shown in FIG. 3 are within the scope of the present invention.

  In this embodiment, as shown in FIG. 3, the gate electrode 3 is formed immediately above the barrier layer semiconductor layer. However, as a device structure, an insulating film is formed between the gate electrode 3 and the barrier layer semiconductor. Even the inserted so-called insulated gate structure (that is, MIS structure (MIS: Metal-Insulator-Semiconductor)), all the structures having the above-described features according to the present invention shown in FIG. 3 are all within the scope of the present invention. It is.

  1: barrier layer semiconductor / channel layer semiconductor heterostructure, 2: source electrode, 3: gate electrode, 4: drain electrode, 5: regrown nitride semiconductor.

Claims (1)

  1. In a semiconductor device which is a heterostructure field effect transistor using a nitride semiconductor,
    The band gap of the source side nitride semiconductor in ohmic contact with the source electrode and the drain side nitride semiconductor in ohmic contact with the drain electrode is smaller than the band gap of the nitride channel layer semiconductor forming the channel, and
    A composition-graded nitride whose composition changes continuously between the source-side nitride semiconductor and the nitride channel layer semiconductor and between the drain-side nitride semiconductor and the nitride channel layer semiconductor, respectively. By connecting through the semiconductor, discontinuity of the semiconductor band gap in the electric path connecting the source electrode and the channel and between the drain electrode and the channel, respectively , has been eliminated ,
    The composition of the source-side nitride semiconductor and the drain-side nitride semiconductor is represented by In X Ga 1-X N (here, 0.46 ≦ X ≦ 1.0), and the surfaces of the both nitride semiconductors Is located above the position of the heterointerface between the nitride barrier layer semiconductor and the nitride channel layer semiconductor existing below the gate electrode by a distance of 0 nm or more and 10 nm or less, whereby the source-side nitride A semiconductor device characterized in that an electron distribution in a charge storage layer formed on a surface of a semiconductor and an electron distribution in the nitride channel layer semiconductor overlap each other.
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