JP2012169470A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high performance InN-based FET which can significantly reduce surface charge storage on a crystal surface participating in a gate operation and obtain pinch-off characteristics.SOLUTION: A semiconductor device that is a field effect transistor including an InN-based semiconductor as a channel layer in which a stepped portion is formed on a surface (c-plane) of a channel layer 2 composed of an InN-based semiconductor to form a sidewall surface 2a composed of a-plane or m-plane of a hexagonal crystal of a nitride semiconductor, a gate electrode 6 is arranged on the sidewall surface 2a, and a source electrode 3 and a drain electrode 4 are formed on the c-plane so as to sandwich the gate electrode 6.

Description

  The present invention relates to a semiconductor device, and more particularly to a field effect transistor using an InN (indium nitride) based semiconductor and a method for manufacturing the same.

  Field effect transistors (FETs) using nitride semiconductors are very promising as next-generation high-temperature, high-output, high-voltage ultrahigh-frequency transistors, and are actively researched for practical application. It has been broken. Such field effect transistors include heterostructure field effect transistors (HFETs). However, with regard to FETs using nitride semiconductors, most research and development currently being carried out is GaN (gallium nitride) using GaN (or AlGaN having a large Ga composition) as a semiconductor constituting the channel layer (channel layer semiconductor). ) System HFET. Compared with this, regarding InN-based FETs using InN-based semiconductors as channel layer semiconductors, almost no research results such as realization of transistor operations and demonstration of characteristics have been reported. InN-based FETs using InN-based semiconductors (including InGaN, InAlN, InAlGaN, etc.) as channel layer semiconductors have higher electron mobility and maximum electron velocity than GaN-based FETs. Accordingly, the InN-based FET is expected to operate at a higher speed than the GaN-based FET.

FIG. 7 schematically shows a configuration of a reference example of the InN-based FET 100 manufactured using the channel layer 101 made of an InN-based semiconductor grown in a direction perpendicular to the c-plane ((0001) plane). . In this InN-based FET 100, a source electrode 102 and a drain electrode 103 are formed on a channel layer 101, an insulating film 104 is deposited between the source electrode 102 and the drain electrode 103, and a gate electrode 105 is formed on the insulating film 104. Is formed. Such InN-based FET 100 is theoretically expected to operate at a higher speed than GaN-based FETs (see Non-Patent Document 1, for example). However, there are few reports on InN-based FET manufacturing methods and transistor operations. One reason for this is that a high concentration of surface charge (−10 ¹³ cm ⁻² ) is accumulated on the surface of the InN crystal (see, for example, Non-Patent Document 2). A broken line sc1 shown in FIG. 7 schematically shows the surface charge accumulated on the surface of the channel layer 101. When such surface charge sc1 is accumulated, pinch-off characteristics (characteristic that can make the drain current zero by applying a positive voltage to the gate electrode 105) that is essential for transistor operation cannot be obtained. In order to solve this problem, it is necessary to significantly reduce the amount of accumulated surface charge sc1 existing on the surface of the channel layer 101 made of InN crystal.

  Originally, even if high concentration surface charge accumulation (electron accumulation) exists, a pinch-off characteristic should be obtained by applying a negative voltage to the gate electrode 105 in FIG. However, experimentally, in the InN crystal, even if the gate voltage is applied, the pinch-off characteristic is not actually obtained.

  On the other hand, the accumulation of surface charges on the InN crystal surface is inevitable on the c-plane ((0001) plane) which is a polar plane, but the a-plane ((11-20) plane) and m-plane which are nonpolar planes. It is theoretically expected that ((1-100) plane) disappears or is greatly reduced (Reference 3).

S. K. O 'Leary et al., J. of Appl. Phys. 83, 826 (1998). H. Lu et. Al., Appl. Phys. Lett. 82, 1736 (2003). D. Segev and C. G. Van de Walle, Europhys. Lett. 76, 305 (2006).

  However, it is generally difficult to grow a high quality InN crystal in a direction perpendicular to the nonpolar plane so that the nonpolar plane is exposed, and on any InN surface currently experimentally obtained, No reduction in surface charge accumulation has been observed. Therefore, an InN-based FET showing satisfactory transistor operation has not been realized.

  Under such circumstances, the InN-based semiconductor used as the channel layer semiconductor realizes the pinch-off characteristics that are hindered by the surface charge accumulation by significantly reducing the surface charge accumulation, and the InN-based semiconductor has an excellent It has been strongly desired to realize a high-performance InN-based FET that can utilize electron transport properties (high electron mobility and high saturation electron velocity).

  The object of the present invention is to use a nitride semiconductor FET (including HFET) as a nitride semiconductor channel layer, which has higher electron mobility and saturated electron velocity than GaN, and therefore can be expected to operate at higher speed. InN-based FETs using InN-based semiconductors (including InN and InGaN, InAlN, or InAlGaN, which generally have a large In composition), the surface charge accumulation on the crystal surface involved in gate operation is greatly reduced, and pinch-off characteristics Is to provide a high-performance InN-based FET.

  In order to solve the above-described problems and achieve the object, a feature of the present invention is a semiconductor device which is a field effect transistor including an InN-based semiconductor as a channel layer, and a hexagonal nitride semiconductor is formed on the surface of the channel layer. The gist of the invention is that it has a surface region for forming a gate formed of an a-plane or m-plane of a crystal crystal, and a gate electrode is arranged in the surface region for gate formation.

  According to the present invention, in the above structure, the main surface of the channel layer is a c-plane, and the surface region for gate formation is a side wall surface of a step formed perpendicular to the main surface, and the source electrode and the source electrode so as to sandwich the gate electrode The drain electrode is formed on the c-plane.

  The present invention is characterized in that, in the above configuration, the c-planes on which the source electrode and the drain electrode are formed have different height positions with respect to the side wall surface.

  According to the present invention, in the above configuration, the side wall surface is a side wall surface of the groove formed in the main surface, and the height position of the c surface on which the source electrode is formed and the c surface on which the drain electrode is formed are the same. It is characterized by that.

  In the above structure, the present invention is characterized in that a gate insulating film of 100 nm or less is interposed between the gate forming surface region and the gate electrode.

  The present invention is characterized in that, in the above structure, the channel layer is formed by heterojunction a nitride semiconductor barrier layer on the surface of the InN-based semiconductor layer.

  Another feature of the present invention is a method for manufacturing a semiconductor device, which is a hexagonal crystal a-plane perpendicular to the surface of an InN-based semiconductor substrate, the main surface being a c-plane of a hexagonal crystal of a nitride semiconductor. forming a step having a sidewall surface corresponding to the m-plane, and forming a gate electrode on the sidewall surface and forming a source electrode and a drain electrode on the c-plane at a position sandwiching the sidewall surface. The gist.

  The present invention is characterized in that, in the above configuration, a step of forming a nitride semiconductor barrier layer on the InN-based semiconductor substrate is provided after the step of forming a step in the InN-based semiconductor substrate.

  The present invention is characterized in that, in the above configuration, the step is processed by wet etching using a potassium hydroxide solution.

  According to the present invention, a pinch-off characteristic is realized by significantly reducing surface charge accumulation, and an electric field effect capable of utilizing the excellent electron transport characteristics (high electron mobility and high saturation electron velocity) of InN-based semiconductors. A transistor or a heterostructure field effect transistor can be realized.

It is a figure which shows typically the surface orientation of a hexagonal crystal. It is a figure explaining the structure of the field effect transistor which is a semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure explaining the structure of the heterostructure field effect transistor (HFET) which is a semiconductor device concerning the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure explaining the field effect transistor which is a semiconductor device concerning the 2nd Embodiment of this invention. It is a figure which shows the reference example of the field effect transistor using an InN type semiconductor.

  Details of a semiconductor device and a method for manufacturing the semiconductor device according to each embodiment of the present invention will be described below with reference to the drawings. However, it should be noted that the drawings are schematic, and the dimensions and ratios of the members are different from actual ones. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.

  A field effect transistor using a nitride semiconductor is manufactured using a nitride semiconductor crystal having a hexagonal crystal structure. FIG. 1 schematically shows the plane orientation of a hexagonal crystal of a nitride semiconductor. Considering an InN crystal as a nitride semiconductor, in the c-plane ((0001) plane), group III atoms (In) and group V atoms (N) are alternately stacked, so that this plane becomes a polar plane. . In contrast, in the a-plane ((11-20) plane) and m-plane ((1-100) plane), the group III atom (In) and the group V atom (N) are present on the same plane. These surfaces are nonpolar surfaces. Here, as shown in FIG. 1, the a-plane ((11-20) plane) and the m-plane ((1-100) plane) are perpendicular to the c-plane ((0001) plane).

  In the growth of InN crystal, crystal growth is performed in the c-plane ((0001) plane) direction (c-axis direction), which is a polar plane, as in the growth of other nitride semiconductor crystals. The crystal growth of nitride semiconductors in the a-plane ((11-20) plane) and m-plane ((1-100) plane) directions, which are nonpolar planes, is the crystal growth in the c-plane ((0001) plane) direction. In general, it is difficult to obtain high-quality crystals. This situation is more conspicuous with respect to crystal growth of InN-based nitride semiconductors, in which high-quality crystal growth is inherently much more difficult than GaN-based nitride semiconductors. Therefore, when a field effect transistor (FET) is realized using an InN-based semiconductor, it is possible to fabricate an FET structure in an InN-based semiconductor having a c-plane as a main surface obtained by crystal growth in the c-axis direction. It is essential to obtain the required crystal quality.

(First embodiment)
FIG. 2 is a diagram schematically showing the configuration of the field effect transistor 1 as the semiconductor device according to the first embodiment of the present invention. In the present embodiment, a channel layer 2 made of an InN-based semiconductor is used in which a c-plane ((0001) plane) of a hexagonal nitride semiconductor crystal is grown in the direction along the c-axis. In the element region where the field effect transistor 1 is formed, a step in the direction perpendicular to the c-plane is formed in the channel layer 2. Therefore, as shown in FIG. 2, the channel layer 2 has two high and low (upper and lower) c-plane surfaces, and the source electrode 3 and the drain electrode 4 are formed on each c-plane. . A side wall surface (step surface) 2a as a gate forming surface region perpendicular to the c-plane ((0001) plane) is an a-plane ((11-20) plane) or m-plane ((1-100) of an InN-based semiconductor. ) Surface). An insulating film (gate insulating film) 5 is formed on the element surface region including the a-plane ((11-20) plane) or the m-plane ((1-100) plane). A gate electrode 6 is formed so as to face the side wall surface 2a with the insulating film 5 interposed therebetween.

  As described above, the c-plane ((0001) plane) is a polar plane, and surface charge sc1 is accumulated as shown in FIG. Since the a-plane ((11-20) plane) or m-plane ((1-100) plane) is a nonpolar plane, the surface charge sc2 is greatly reduced compared to the c-plane ((0001) plane). . In addition, the thick broken line sc1 shown in FIG. 2 shows a large surface charge, and the thin broken line sc2 schematically shows the state of the surface charge greatly reduced.

  As described above, the surface charge sc2 of the a-plane ((11-20) plane) or m-plane ((1-100) plane) is small. As a result, the nonpolar plane surface (side wall surface 2a) or the insulating film 5 / channel layer. The potential position of the two interfaces is not fixed (release of surface potential pinning). Therefore, as shown in FIG. 2, the crystal surface involved in the gate operation is a non-polar plane a-plane ((11-20) plane) or m-plane ((1-100) plane). Operation is possible, pinch-off characteristics are obtained, and a high-performance InN-based FET utilizing the excellent electron transport characteristics of the InN-based channel layer semiconductor can be realized.

  As shown in FIG. 2, an aN ((11-20) plane) or m ((1-100) plane) InN crystal that forms a stepped side wall 2a perpendicular to the c plane ((0001) plane). The surface can be formed as a chemically stable surface by performing wet etching using a potassium hydroxide (KOH) solution on the channel layer 2 having the c-plane ((0001) plane) as the crystal surface. It is.

  On the other hand, when such a step shape is formed by performing dry etching, which is generally used for nitride semiconductors, electrons derived from surface defects are generated. Is not realized. Therefore, like the side wall surface 2a in the field effect transistor 1 according to the present embodiment, the a-plane ((11-20) plane) or m-plane ((1 In order to form (-100) plane), it is effective to at least partially use wet etching using a potassium hydroxide (KOH) solution.

As the InN-based channel layer semiconductor constituting the channel layer 2 in the field effect transistor 1, InN and InGaN, InAlN, or InAlGaN having an In composition of 0.5 or more can be used. As the insulating film _{5, Si0 2, Si 3 N} 4, AlN, Al 2 O 3, Zr0 2, HfO 2, other, it is possible to use various insulating material film. The insulating film 5 is for increasing the gate breakdown voltage, and the effect is higher as the film thickness is increased. However, since the gain of the element is reduced as the film thickness is increased, the layer thickness exceeding 100 nm is not necessary. It is also possible to use a structure in which the insulating film 5 is not used, that is, the layer thickness is 0 nm.

  As described above, the field effect transistor 1 using an InN-based semiconductor, which has higher electron mobility and saturated electron velocity than GaN as a constituent material of the channel layer 2 and can be expected to operate at higher speed, is involved in gate operation. As a result, the surface charge accumulation on the crystal surface is greatly reduced, pinch-off characteristics are obtained, and the excellent electron transport characteristics (high electron mobility and high saturation electron velocity) of the InN-based semiconductor can be utilized.

  Next, a manufacturing method of the field effect transistor 1 according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, a GaN layer 11 having a layer thickness of 2 μm is grown on a sapphire substrate 10 having a c-plane ((0001) plane) as a main surface. Thereafter, the channel layer 2 made of InN having a thickness of 800 nm is grown on the GaN layer 11. Since the surface of the channel layer 2 is a c-plane ((0001) plane) and a polar plane, it has a large surface charge sc1. Here, the growth of the channel layer 2 and the GaN layer 11 is performed by MBE (Molecular
Beam
Epitaxy), MOVPE (Metal Organic Vapor Phase Epitaxy), or a combination of these methods. The channel layer 2 may be doped (P-type doping) with an atomic concentration of about 5 × 10 ¹⁸ cm ^{−3 in} order to reduce the background electron concentration in the channel layer 2.

  Next, an element isolation process is performed in which Ga ions or the like are implanted into the non-element region in the channel layer 2 to increase the electrical insulation of the non-element region. The element isolation method is not limited to implanting Ga ions or the like.

Next, as shown in FIG. 3-2, water is formed so that a side wall surface 2a perpendicular to the c-plane ((0001) plane) is formed at a position partitioned in half through almost the center of the element region. A step with a height difference of 200 nm is formed by wet etching using a potassium oxide (KOH) solution. The bottom surface (lower surface) of the step is a c-plane ((0001) surface) parallel to the upper surface. The side wall surface 2a perpendicular to the top and bottom surfaces of the step is an a-plane ((11-20) plane) or m-plane ((1-100) plane) which is a nonpolar plane. Since the a-plane ((11-20) plane) or the m-plane ((1-100) plane) is a nonpolar plane, the surface charge sc2 (see the thin broken line) is significantly larger than that of the c-plane ((0001) plane). Has been reduced. The step (side wall surface 2a) may be formed by a combination of dry etching and wet etching using a potassium hydroxide (KOH) solution. The side wall surface 2a thus formed is a non-polar surface a-plane ((11-20) plane) or m-plane ((1-100) plane) as described above, and is a chemically stable surface. It is. As the accumulation of the surface charge sc2 on the side wall surface 2a, the electron concentration is about 3 × 10 ¹² cm ^−2, and the value of the surface charge sc1 on the c-plane ((0001) plane) surface (5 × 10 ¹³ cm ⁻² ). 1/10 or less.

Thereafter, as shown in FIG. 3C, Al ₂ O ₃ is deposited by an ALD (Atomic Layer Deposition) method so as to have a layer thickness of 20 nm, and then patterned to form an insulating film (gate insulating film) 5. Formed. Then, the source electrode 3, the drain electrode 4, and the gate electrode 6 were formed using the same method as the manufacturing process of a normal nitride semiconductor FET, and the field effect transistor 1 having an InN-based FET structure was manufactured. In this field effect transistor 1, it was confirmed that pinch-off characteristics were obtained, and a high-performance InN-based FET was realized.

  Here, the field effect transistor 1 of the present embodiment is not limited to the sapphire substrate 10, but a SiC (silicon carbide) substrate or Si (silicon) substrate, or AlN, AlGaN, InGaN or the like formed on these substrates. Even if the substrate is formed on any substrate such as a template substrate or a substrate such as GaN, AlN, InN, AlGaN, or InGaN, the scope of application of the present invention is as long as it has the features of this embodiment shown in FIG. Is within. Further, even if any portion of the InN-based FET structure is doped with impurities such as Si or Mg for designing the electron concentration, the field effect according to the present embodiment shown in FIG. As long as it has the characteristics of the structure of the transistor 1, all are within the scope of the present invention.

(Second Embodiment)
Next, a field effect transistor 1A according to a second embodiment of the present invention will be described with reference to FIG. In the field effect transistor 1A according to the present embodiment, the same parts as those of the field effect transistor 1 according to the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.

  The field effect transistor 1A according to the present embodiment has a structure in which the nitride semiconductor barrier layer 7 is provided on the channel layer 2 in the field effect transistor 1 according to the first embodiment described above. This field effect transistor 1A has a heterostructure including an InN-based channel layer semiconductor (nitride semiconductor barrier layer semiconductor / InN-based channel layer semiconductor). The operation of the field effect transistor 1A of the present embodiment is substantially the same as that of the field effect transistor 1 according to the first embodiment described above. The field effect transistor 1A according to the present embodiment includes the nitride semiconductor barrier layer 7 as compared with the field effect transistor 1 according to the first embodiment, so that the element structure is complicated. However, regarding the channel electrons existing below the gate electrode, which is most important for device operation, in the field effect transistor 1 according to the first embodiment, channel electrons exist at the interface between the insulating film 5 and the channel layer 2. On the other hand, in the field effect transistor 1A according to the present embodiment, channel electrons are generally formed at the interface of the semiconductor heterostructure where a higher quality interface is formed, that is, at the nitride semiconductor barrier layer 7 / channel layer 2 heterointerface. Exists. As a result, the field effect transistor 1A according to the present embodiment has an advantage in device operation that a higher channel electron velocity is easily obtained.

  As the InN-based semiconductor for forming the channel layer 2 in the field effect transistor 1A according to the present embodiment, InN and InGaN, InAlN, or InAlGaN having an In composition of 0.5 or more can be used. The semiconductor constituting the physical semiconductor barrier layer 7 can be any nitride semiconductor having a larger band gap than the InN-based semiconductor forming the channel layer 2 and functioning as a barrier layer. That is, the laminated structure of the nitride semiconductor barrier layer 7 / channel layer 2 includes InN / GaN, InN / InGaN, InN / AlN, InN / AlGaN, InGaN / GaN, InGaN / InGaN, InGaN / AlGaN, InGaN / AlN. InAlN / AlGaN, InAlN / AlN, InAlGaN / AlGaN, InAlGaN / AlN, or the like can be used.

Further, as the insulating film 5 in a field effect transistor 1A according to this _{embodiment, Si0 2, Si 3 N 4} , AlN, Al 2 O 3, Zr0 2, HfO 2, other, the use of various insulating material film Is possible. The insulating film 5 is for increasing the gate breakdown voltage, and the effect is higher as the film thickness is increased. However, since the gain of the element is reduced as the film thickness is increased, the layer thickness exceeding 100 nm is not necessary. It is also possible to use a structure in which the insulating film 5 is not used, that is, the layer thickness is 0 nm.

  Next, a method of manufacturing the field effect transistor 1A according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 5A, a GaN layer 11 having a layer thickness of 2 μm is grown on a sapphire substrate 10 having a c-plane ((0001) plane) as a main surface. Thereafter, the channel layer 2 made of InN having a thickness of 800 nm is grown on the GaN layer 11. Since the surface of the channel layer 2 is a c-plane ((0001) plane) and a polar plane, it has a large surface charge sc1. Here, the growth of the channel layer 2 and the GaN layer 11 is performed by MBE (Molecular
Beam
Epitaxy), MOVPE (Metal Organic Vapor Phase Epitaxy), or a combination of these methods. The channel layer 2 may be doped (P-type doping) with an atomic concentration of about 5 × 10 ¹⁸ cm ^{−3 in} order to reduce the background electron concentration in the channel layer 2.

Next, as shown in FIG. 5B, water is formed so that a side wall surface 2a perpendicular to the c-plane ((0001) plane) is formed at a position that is divided in half through almost the center of the element region. A step with a height difference of 200 nm is formed by wet etching using a potassium oxide (KOH) solution. The bottom surface (lower surface) of the step is a c-plane ((0001) surface) parallel to the upper surface. The side wall surface 2a perpendicular to the top and bottom surfaces of the step is an a-plane ((11-20) plane) or m-plane ((1-100) plane) which is a nonpolar plane. Since the a-plane ((11-20) plane) or the m-plane ((1-100) plane) is a nonpolar plane, the surface charge sc2 (see the thin broken line) is significantly larger than that of the c-plane ((0001) plane). Has been reduced. The step (side wall surface 2a) may be formed by a combination of dry etching and wet etching using a potassium hydroxide (KOH) solution. The side wall surface 2a thus formed is a non-polar surface a-plane ((11-20) plane) or m-plane ((1-100) plane) as described above, and is a chemically stable surface. As the surface charge accumulation, the electron concentration is about 3 × 10 ¹² cm ^−2, which is 1/10 or less of the surface charge accumulation value (5 × 10 ¹³ cm ⁻² ) on the c-plane ((0001) plane) surface. Reduce significantly.

  Next, as shown in FIG. 5-3, GaN is grown to a thickness of 5 nm on the channel layer 2 having the stepped surface formed by the above etching process by the crystal growth method by the MBE method or the MOVPE method. A nitride semiconductor barrier layer 7 is formed. As a result, a GaN / InN heterostructure having a step structure in which the surface of the channel layer 2 is entirely covered with the nitride semiconductor barrier layer 7 made of GaN is formed.

  Thereafter, the non-element region is highly insulated by implanting Ga ions or the like into the non-element region (element isolation process).

The non-polar a-plane ((11-20) plane) or m-plane ((1-100) plane) InN plane embedded in the GaN / InN heterostructure is a chemically stabilized plane. The surface charge sc2 electron concentration as charge accumulation at the InN heterointerface is about 3 × 10 ¹² cm ^−2, which is 1 of the value (5 × 10 ¹³ cm ⁻² ) of the surface charge sc1 on the c-plane ((0001) plane) surface. / 10 or less.

Thereafter, as shown in FIG. 5-4, Al ₂ O ₃ is deposited by an ALD (Atomic Layer Deposition) method so as to have a layer thickness of 20 nm, and then patterned to form an insulating film (gate insulating film) 5. Formed. A source electrode 3, a drain electrode 4, and a gate electrode 6 are formed by using a method similar to a process for manufacturing a normal nitride semiconductor FET, and the field effect transistor 1 having an InN-based FET structure having a heterostructure is formed. Produced. In this field effect transistor 1, it was confirmed that pinch-off characteristics were obtained, and a high-performance InN-based FET was realized.

In the field effect transistor 1A according to the present embodiment, the cutoff frequency (f _T ), which is an index of high-speed operation of the FET, is increased by 20% as compared with the field effect transistor 1 according to the first embodiment.

  In the present embodiment, the nitride semiconductor barrier layer 7 is also laminated on the channel layer 2 where the c-plane ((0001) plane) is exposed where the source electrode 3 and the drain electrode 4 are formed. The nitride semiconductor barrier layer 7 does not need to be stacked in the c-plane ((0001) plane) region, and is formed on the c-plane ((0001) plane) of the channel layer 2 by a manufacturing method different from the above-described manufacturing method. A source electrode 3 and a drain electrode 4 may be formed.

  In field effect transistor 1A according to the present embodiment, in addition to sapphire substrate 10, SiC (silicon carbide) substrate or Si (silicon) substrate, or AlN, AlGaN, InGaN, or the like formed on these substrates is used. Even if the substrate is formed on any substrate such as a template substrate or a substrate such as GaN, AlN, InN, AlGaN, or InGaN, the scope of application of the present invention is as long as it has the features of this embodiment shown in FIG. Is within. Moreover, even if any part of the heterostructure InN-based FET is doped with impurities such as Si or Mg for designing the electron concentration, the second embodiment shown in FIG. As long as it has the characteristics of the structure of the field effect transistor 1A, all are within the scope of the present invention.

  The field effect transistors 1 and 1A according to the first and second embodiments described above have the a-plane ((11-20) plane) or m-plane ((1-100) plane) of the InN-based semiconductor. By forming the gate electrode 6 so as to correspond to the above, surface charge accumulation on the surface of the channel layer crystal facing the gate electrode 6 can be greatly reduced, and pinch-off characteristics can be obtained. Therefore, according to the field effect transistors 1 and 1A, the excellent electron transport properties (high electron mobility and high saturation electron velocity) of the InN-based semiconductor can be utilized.

(Other embodiments)
Although the first and second embodiments have been described above, it should not be understood that the description and the drawings, which form part of the disclosure of these embodiments, limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, the field effect transistors 1 and 1A according to the first and second embodiments described above have an a-plane ((11-20) plane) or m-plane ((1-100) plane on the surface of the channel layer 2. The side wall surface 2a is formed between two c-planes ((0001) planes) having different vertical heights, but as in the modification shown in FIG. 6, a groove is formed in the channel layer 2 in the region where the gate electrode 6 is formed. A (trench) is formed, and the gate electrode 6 is embedded in the groove so that the gate electrode 6 is in contact with the pair of side wall surfaces 2a that are the inner walls of the trench. Then, the height position of the c plane on which the source electrode 3 is formed and the c plane on which the drain electrode 4 is formed are the same height position, and in such a structure, a heterostructure is formed on the channel layer 2. Layered nitride semiconductor barrier layer The field effect transistors having these configurations are also within the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1,1A ... Field effect transistor, 2 ... Channel layer, 2a ... Side wall surface, 3 ... Source electrode, 4 ... Drain electrode, 5 ... Insulating film, 6 ... Gate electrode, 7 ... Nitride semiconductor barrier layer

Claims (9)

A semiconductor device which is a field effect transistor including an InN-based semiconductor as a channel layer,
The surface of the channel layer has a gate forming surface region composed of an a-plane or an m-plane of a hexagonal crystal of a nitride semiconductor, and a gate electrode is arranged in the surface region for gate formation. Semiconductor device.   The main surface of the channel layer is a c-plane, the gate forming surface region is a side wall surface of a step formed perpendicular to the main surface, and the source electrode and the drain electrode are c to sandwich the gate electrode. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a surface.   3. The semiconductor device according to claim 1, wherein the heights of the c-planes on which the source electrode and the drain electrode are formed are different from each other across the side wall surface.   The side wall surface is a side wall surface of a groove formed in the main surface, and the height of the c surface on which the source electrode is formed and the c surface on which the drain electrode is formed are the same. The semiconductor device according to claim 1 or 2.   5. The semiconductor device according to claim 1, wherein a gate insulating film of 100 nm or less is interposed between the gate forming surface region and the gate electrode.   The semiconductor device according to claim 1, wherein the channel layer is formed by heterojunction a nitride semiconductor barrier layer on a surface of an InN-based semiconductor layer. Forming a step having a side wall surface corresponding to an a-plane or m-plane of a hexagonal crystal and having a c-plane of a hexagonal crystal of a nitride semiconductor as a main surface and perpendicular to the surface of the InN-based semiconductor substrate;
Forming a gate electrode on the sidewall surface, and forming a source electrode and a drain electrode on a c-plane at a position sandwiching the sidewall surface;
A method for manufacturing a semiconductor device, comprising:   8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a nitride semiconductor barrier layer on the InN-based semiconductor substrate after a step of forming a step in the InN-based semiconductor substrate.   The method of manufacturing a semiconductor device according to claim 7, wherein the step is processed by wet etching using a potassium hydroxide solution.

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