JP2013229486A - Heterojunction field-effect transistor, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a heterojunction field-effect transistor and a method of manufacturing the same capable of improving a withstanding voltage and reducing on-resistance.SOLUTION: A cap layer 5 made of GaN is selectively formed on a barrier layer 4. That is, the cap layer 5 is formed only in a drain direction gate electrode vicinity region that extends from a position (a first position) adjacent on a drain electrode 8 side to an I-shaped part of a T shape of a gate electrode 10 to a position (a second position; a position separated from the drain electrode 8 by a predetermined distance) not reaching the drain electrode 8, in a direction toward the drain electrode 8 (and an Si injection region 6 under the drain electrode).

Description

  The present invention relates to a heterojunction field effect transistor (heterojunction FET) made of a semiconductor containing nitride and a method for manufacturing the same.

  Nitride semiconductors, especially gallium nitride semiconductors, are useful as materials for high-power, high-electron mobility transistors in high-frequency bands because of their high breakdown field strength, high electron saturation speed, and high thermal conductivity. . Further, high electron mobility transistors (HEGaN) using aluminum gallium nitride (AlGaN) / gallium nitride (GaN) heterojunctions have a small band gap among semiconductors forming heterojunctions. A so-called two-dimensional electron gas is formed near the heterojunction interface on the side, in which a so-called two-dimensional electron gas is formed. The two-dimensional electron gas is spatially separated from ionized impurities generated on the side having a large band gap. Therefore, as a result of reducing electron scattering, it is suitable for high-frequency operation in that high electron mobility can be obtained.

  However, in a heterojunction field effect transistor made of a semiconductor containing nitride (nitride semiconductor), in general, the withstand voltage estimated from the physical property values of the gallium nitride semiconductor described above is not obtained. is there. In this regard, it is said that there are still problems peculiar to nitride semiconductors, such as the amount of gate leakage current being larger than the theoretical value compared to other material semiconductors. A measure has been devised.

  In a conventional high electron mobility transistor using a nitride semiconductor, for example, as shown in FIG. 1 of Patent Document 1, the breakdown voltage is improved by forming a cap layer between the source / gate and between the gate / drain. The technique is taken. In addition, for example, as shown in FIG. 4 of Patent Document 2, the access layer barrier layer (the gate-source region and the region of the barrier layer below the gate-drain region) is thinned. As shown in FIG. 5 of Patent Document 3, a method of processing, or a method of forming a stepped gate electrode so as to relieve an electric field distributed in the vicinity of the gate electrode (in the case of the structure shown in FIG. The effect of thinning due to recess processing is also superimposed).

Japanese Patent Laid-Open No. 9-321060 (FIG. 1) Japanese Patent Laying-Open No. 2005-203544 (FIG. 4) JP 2006-286740 A (FIG. 5)

  In a heterojunction field-effect transistor (heterojunction FET), when a cap layer is provided on the barrier layer for the purpose of improving the breakdown voltage, the carrier concentration decreases only in the access region except for the region directly under the gate electrode. to be influenced. That is, due to the presence of the cap layer, the two-dimensional electron gas concentration in the channel layer under the gate-source region and the gate-drain region is affected by the decrease. For this reason, the drain current of the heterojunction FET is reduced, resulting in a problem that power efficiency is lowered.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain a heterojunction field effect transistor and a method for manufacturing the same, in which the breakdown voltage is improved and the on-resistance is reduced.

  According to a first aspect of the present invention, there is provided a heterojunction field effect transistor comprising a channel layer made of a nitride semiconductor formed above a substrate and a nitride semiconductor different from the channel layer formed on the channel layer. A barrier layer, a gate electrode selectively provided on the barrier layer, a source electrode and a drain electrode that are independently provided at a predetermined distance while sandwiching the gate electrode above the substrate, A cap layer made of a nitride semiconductor, which is selectively provided on the barrier layer between the gate electrode and the drain electrode, and the cap layer from a first position adjacent to a side surface of the gate electrode. Formed only in the vicinity of the drain direction gate electrode, which is a region extending to the second position that does not reach the drain electrode in the direction of the drain electrode Is the fact characterized.

  2. The heterojunction field effect transistor according to claim 1, wherein the cap layer is formed only in a region in the vicinity of the drain direction gate electrode, whereby a region where the two-dimensional electron gas concentration is reduced in the channel layer is defined in the drain direction gate electrode. It can be suppressed only to the channel layer under the neighboring region. As a result, by providing the cap layer, it is possible to reduce the on-resistance while improving the withstand voltage, so that it is possible to expect an improvement in power efficiency.

It is sectional drawing which shows the structure of heterojunction FET which consists of nitride semiconductor which is Embodiment 1 of this invention. FIG. 6 is a cross-sectional view showing a structure of a modification of the heterojunction FET of the first embodiment. It is a graph which shows the result of having estimated the electric field strength distribution of heterojunction FET when not forming a cap layer by calculation. It is a graph which shows the result of having estimated the electric field strength distribution of heterojunction FET at the time of forming the cap layer of a predetermined formation width by calculation. It is a graph which shows electric field strength distribution in case the formation width of a cap layer is 0.5 micrometer to 1.4 micrometers. 6 is a cross-sectional view showing a structure of a first aspect of a heterojunction FET in Embodiment 2. FIG. FIG. 6 is a cross-sectional view showing the structure of a second mode of the heterojunction FET in the second embodiment. FIG. 6 is a cross-sectional view showing a structure of a third aspect of the heterojunction FET in the second embodiment. FIG. 10 is a cross-sectional view showing a structure of a fourth mode of the heterojunction FET in the second embodiment. FIG. 10 is a cross-sectional view showing a structure of a fifth mode of the heterojunction FET in the second embodiment. FIG. 10 is a cross-sectional view showing a structure of a sixth aspect of the heterojunction FET in the second embodiment. It is sectional drawing which shows the structure of the 7th aspect of heterojunction FET in Embodiment 2. FIG. It is sectional drawing which shows the structure of the 8th aspect of heterojunction FET in Embodiment 2. It is sectional drawing which shows the manufacturing method of the telojunction FET of the structure shown in FIG. It is sectional drawing which shows the manufacturing method of the telojunction FET of the structure shown in FIG. It is sectional drawing which shows the manufacturing method of the telojunction FET of the structure shown in FIG. It is sectional drawing which shows the manufacturing method of the telojunction FET of the structure shown in FIG. It is sectional drawing which shows the manufacturing method of the telojunction FET of the structure shown in FIG. It is sectional drawing which shows the manufacturing method of the telojunction FET of the structure shown in FIG. It is sectional drawing which shows the manufacturing method of the telojunction FET of the structure shown in FIG.

<Embodiment 1>
1 is a cross-sectional view showing a basic structure of a heterojunction FET made of a nitride semiconductor according to Embodiment 1 of the present invention.

In FIG. 1, the lowermost layer is a semi-insulating SiC substrate 1, and a channel layer 3 made of GaN is formed on the semi-insulating SiC substrate 1 via a buffer layer 2. On the channel layer 3, a barrier layer 4 made of Al _0.28 Ga _0.72 N is formed.

  On the central region of the barrier layer 4, the gate electrode 10 having a recessed gate structure having an umbrella portion at the top and a T-shaped cross section is formed. Then, the Si-injection region 6 under the drain electrode and the Si-injection region 7 under the source electrode are selectively formed through the barrier layer 4 from the upper layer portion of the channel layer 3 with the gate electrode 10 interposed therebetween. Yes. A drain electrode 8 and a source electrode 9 are formed on the Si implantation region 6 under the drain electrode and the Si implantation region 7 under the source electrode.

  Therefore, the drain electrode 8 and the drain electrode 8 are formed independently from the gate electrode 10. The drain electrode 8 and the source electrode 9 are each made of Ti / Nb / Pt, and the gate electrode 10 is made of Ni / Au.

  Further, a cap layer 5 made of GaN is selectively formed on the barrier layer 4. That is, the cap layer 5 extends from a position adjacent to the drain electrode 8 side (first position) with respect to the T-shaped I portion of the gate electrode 10 in the direction of the drain electrode 8 (and the Si implantation region 6 below the drain electrode). It is formed only in the vicinity of the drain direction gate electrode, which is a region extending to a position that does not reach the drain electrode 8 (second position; a position that is separated from the drain electrode 8 by a predetermined distance).

  Then, from the drain electrode 8 to the source electrode 9, on the surface and side surface of the Si implantation region 6 under the drain electrode, on the surface of the barrier layer 4, on the side surface and surface of the cap layer 5, and on the side surface, surface and back surface of the gate electrode 10 ( A dielectric film 11 serving as a protective insulating film is formed on the surface and back surface of the gate umbrella portion, on the surface of the barrier layer 4, and on the side surface and surface of the Si implantation region 7 under the source electrode.

  The Si region under the drain electrode 6 and the Si implantation region 7 under the source electrode are formed by doping an n-type impurity (Si) to obtain ohmic contact with the drain electrode 8 and the source electrode 9.

  The heterojunction FET of the first embodiment exhibits the following effects (1) and (2) by having the above structure.

  (1) Two-dimensional electrons in the channel layer 3 under the region where the cap layer 5 exists (region in the vicinity of the gate electrode in the drain direction) due to the influence of the cap layer 5 composed of GaN remaining adjacent to the gate electrode 10 The pressure resistance is maintained because the gas concentration is suppressed.

  (2) In the channel layer 3 under the region where the cap layer 5 does not exist, the carrier concentration is modulated so that the two-dimensional electron gas concentration becomes high, so that a large saturated drain current can be obtained. That is, effects such as higher output of heterojunction FET made of nitride semiconductor and higher power efficiency are expected.

  Further, by providing only the minimum necessary region in the vicinity of the drain direction gate electrode of the cap layer 5, the amount of gate leakage current through the cap layer 5 can be minimized.

  As described above, in the heterojunction FET according to the first embodiment, the cap layer 5 is formed only in the region in the vicinity of the drain direction gate electrode, whereby the region in the channel layer 3 where the two-dimensional electron gas concentration decreases is the drain direction gate electrode. It can be suppressed only to the channel layer 3 below the neighboring region. As a result, it is possible to reduce the on-resistance while improving the withstand voltage of the heterojunction FET, so that a large saturated drain current can be obtained and the power efficiency can be improved. And energy saving effect can be expected with the improvement of power efficiency.

  FIG. 2 is a cross-sectional view showing the structure of a modification of the heterojunction FET of the first embodiment. As shown in the figure, it differs from the basic structure of FIG. 1 only in that the dielectric film 11 is not formed.

  As shown in FIG. 2, the effects (1) and (2) described above can be obtained without adopting a structure in which the surface of the transistor is covered with the dielectric film 11.

  However, the basic structure having the dielectric film 11 shown in FIG. 1 is superior in that the surface and side surfaces of the barrier layer 4 and the cap layer 6 are prevented from being deformed and a heterojunction FET having high long-term reliability can be obtained. Have That is, in the modification shown in FIG. 2, the semiconductor surfaces such as the barrier layer 4, the cap layer 5, the Si implantation region 6 under the drain electrode, and the Si implantation region 7 under the source electrode are continuously exposed to the atmosphere. The surface of the physical semiconductor is subject to natural oxidation by oxygen and moisture in the atmosphere, and nitrogen in the semiconductor is desorbed. In this case, it has been recognized that problems such as an increase in gate leakage current due to the influence of fluctuations in the energy level due to changes in the surface form occur, and therefore, due to the dielectric film 11 as in the structure shown in FIG. More preferably, the surface protection is formed so as to cover at least the semiconductor surface.

<Embodiment 2>
In the second embodiment, the length (formation width) left of the cap layer 5 is changed to evaluate the electric field strength distribution in the vicinity of the gate electrode 10 so that the on-resistance can be reduced while improving the gate breakdown voltage. After limiting the dimension of the formation width, as shown in the first embodiment (FIGS. 1 and 2), the heterojunction field effect has a structure in which the cap layer 5 is formed only in the vicinity of the drain direction gate electrode. A type transistor is described.

  FIG. 3 is a graph showing a result of estimating the electric field strength distribution of the heterojunction FET when the cap layer 5 is not formed at all. FIG. 4 is a graph showing a result obtained by calculating the electric field strength distribution of the heterojunction FET when the cap layer 5 having a width of 1.5 μm is formed on the barrier layer 4 from the end portion of the gate electrode 10. However, the Al composition and film thickness of AlGaN in the barrier layer 4 are 0.28 and 15 nm, respectively, and the gate length, the gate umbrella length, the gate-source distance, the gate-drain distance, and the edge of the source electrode or drain electrode When the distance from the end of the injection region to the end of the injection region below (corresponding to the distances d1 and d2 in FIG. 1) is 1.0 μm, 3.0 μm, 2.0 μm, 3.0 μm, and 1.0 μm, respectively It is described as a representative.

  FIG. 5 shows the cap layer 5 in addition to the electric field intensity distribution in a cross section at 5 nm below the AlGaN / GaN hetero interface (interface between the barrier layer 4 and the cap layer 5) having the structure shown in FIGS. This is a graph showing the same electric field intensity distribution when the formation width is 0.5 μm to 1.4 μm. The horizontal axis represents the distance from the end of the source electrode 9 to the end of the drain electrode 8. In addition, since the electric field strength distribution when the formation width of the cap layer 5 is 0.5 μm to 1.0 μm is substantially equal, FIG.

  From FIG. 5, it can be seen that the largest electric field is concentrated in the end region of the gate electrode 10 in the direction of the drain electrode 8 (region in the vicinity of a distance of 3 μm). When the formation width of the cap layer 5 exceeds 1.0 μm, a peak of the electric field intensity starts to appear in the end region on the drain electrode 8 side of the cap layer 5 (region in the vicinity of the distance of 4.5 μm). The electric field strength in the end region of the gate electrode 10 on the side tends to decrease (in FIG. 5, it is difficult to see because the peak portions overlap, but as the formation width of the cap layer 5 increases, the gate The peak value of the end region of the electrode 10 is reduced).

  Therefore, in order to improve the breakdown voltage of a heterojunction field effect transistor made of a nitride semiconductor, the electric field strength in the end region of the gate electrode 10 on the drain electrode 8 side is reduced or the carrier concentration in the vicinity of the end region is suppressed. It is necessary to take measures. As is apparent with reference to FIG. 5, in order to reduce the electric field strength in the region, the electric field strength distribution is dispersed in a plurality of locations (in FIG. 5, the peaks are dispersed in the electric field strengths near the distances of 3 μm and 4.5 μm. A so-called electric field relaxation structure is effective.

  On the other hand, from the viewpoint of suppressing current collapse, for example, as described in a related document (Japanese Patent Application Laid-Open No. 2011-103377), it is necessary to provide a nitride cap layer 5 having a film thickness exceeding 28 nm. Therefore, the two-dimensional electron gas concentration in the access region (the gate-drain region and the gate-source region in the channel layer 3) decreases as the formation width of the cap layer 5 is increased in order to form the electric field relaxation structure. As the range increases, the on-resistance increases.

  Therefore, the second embodiment is characterized in that the breakdown voltage is improved by suppressing the concentration of the two-dimensional electron gas 12 in the end region of the gate electrode 10 on the drain electrode 8 side, which is a region where the electric field strength is increased. And That is, 2DEG (2 Dimension Electron Gas) concentration (2) is the most important purpose for improving the breakdown voltage until the electric field strength decreases to 10% (about 200,000) or less of the electric field intensity peak (about 2 million V / cm) in FIG. If the structure is such that the concentration of the dimensional electron gas 12 is suppressed, it can be said that the formation width of the cap layer 5 should be at least about 0.8 μm (distance is about 3.8 μm).

  As described above, the cap layer 5 is formed with the region corresponding to the region of the channel layer 3 in the range until the electric field strength decreases to 10% or less of the electric field intensity peak (maximum value) as the region near the drain direction gate electrode. As a result, it is possible to maintain the breakdown voltage and reduce the on-resistance within a possible range.

  Furthermore, as described in the related literature, the film thickness of the cap layer 5 needs to be at least 28 nm or more from the viewpoint of suppressing current collapse.

  As described above, the occurrence of current collapse of the heterojunction FET can be suppressed by setting the thickness of the cap layer 5 to 28 nm or more.

  6 to 13 are cross-sectional views showing the structures of the first to eighth aspects of the heterojunction FET according to the second embodiment. The specific structure of the first to eighth aspects of the second embodiment will be described later.

  Although only the typical structure (FIGS. 1 and 2) has been described in the first embodiment, the first to eighth embodiments of the second embodiment shown in FIGS. The same effects can be obtained under the following conditions including the embodiment.

(A) In the heterojunction FET shown in FIG. 1, FIG. 2, FIG. 6 to FIG. 13, when the band gap sizes of the channel layer 3, the barrier layer 4, and the cap layer 5 are E3, E4, and E5 Further, if the relationship of E3 <E4 and E5 <E4 is satisfied, it is sufficient to operate the heterojunction field effect transistor. Therefore, in the structure shown in FIG. 1, FIG. 2 and FIG. The layer 3, the barrier layer 4, and the cap layer 5 do not have to be GaN, Al _0.28 Ga _0.72 N, or GaN, and Al, Ga, and N having different compositions of constituent elements include at least 2 containing N. may be composed by a compound consisting of kinds of elements, for example, the channel layer 3, the barrier layer 4, respectively a compound semiconductor forming the capping layer _{5 Al x Ga 1-x N} , Al y Ga _{-Y N,} when the Al _{z Ga 1-z} N, referred to as "0 ≦ x <1", "0 <y <1", "0 ≦ z <1", "x <y", "z <y" What is necessary is just to be comprised with the compound semiconductor which satisfies a relationship. Also. Furthermore, it is not always necessary to be composed of a compound semiconductor composed of at least two elements including N among the three elements Al, Ga and N. For example, a compound semiconductor composed of at least two kinds including N among Al and Ga to which In is added. It may be composed of.

  (B) In the structure of (A), the channel layer 3, the barrier layer 4, and the cap layer 5 are composed of a compound composed of at least two elements including N among Al, Ga, and N (see FIG. 1, FIG. 2, FIG. 6 to FIG. 11 are examples thereof), and since a large polarization effect is generated in the barrier layer 4, it is possible to generate a high-concentration two-dimensional electron gas on the barrier layer 4 side of the channel layer 3. it can. Therefore, it is advantageous for increasing the current and further increasing the output of the transistor, and can be said to be a more preferable structure.

(C) The withstand voltage of the heterojunction FET increases as the breakdown electric field of the semiconductor material used for the channel layer 3 increases. Since Al _X Ga _1-X N has a higher band gap and a higher dielectric breakdown electric field as the Al composition is higher, in the structure of (B), Al _x Ga _1-x N used in the channel layer 3 has a higher Al composition. Higher (x is closer to “1”) is preferable. In addition, since the gate leakage current flowing from the gate electrode to the heterointerface through the barrier layer 4 becomes difficult to flow as the band gap of the semiconductor material used for the barrier layer 4 increases, Al _y Ga _1-y N used as the barrier layer 4. Similarly, a higher Al composition is preferable.

  (D) The channel layer 3, the barrier layer 4, and the cap layer 5 shown in FIGS. 1, 2, and 6 to 13 do not necessarily have a structure of one layer having the same composition, and are shown in (A) above. If the condition of the band gap size is satisfied, the In composition, the Al composition, and the Ga composition may be spatially changed, or a multilayer film composed of several different layers may be used. Further, these layers may contain an impurity that becomes n-type or p-type in the nitride semiconductor.

  (E) A substrate made of Si, sapphire, GaN, AlN or the like may be used as the semi-insulating SiC substrate 1 in FIGS. 1, 2, 6 to 13. For example, when GaN is used as the substrate 1, the channel layer 3, the barrier layer 4, and the like can be formed without necessarily forming the buffer layer 2 on the substrate. Therefore, the buffer layer 2 does not necessarily have to be formed on the substrate 1 and may not be formed.

  (F) The formation width of the cap layer 5 in FIGS. 1 and 2 does not necessarily need to be longer than the umbrella portion of the gate electrode 10, and if the width is at least 0.8 μm or more, the first embodiment shown in FIG. Like the cap layer 5A, it may be flush with the side surface of the umbrella portion of the gate electrode 10, or may be formed shorter than the umbrella length. The first mode of the second embodiment is the same as the basic configuration of the first embodiment shown in FIG. 1 except that the cap layer 5A is flush with the umbrella portion of the gate electrode 10.

  (G) The end portion (side surface portion) on the drain electrode 8 side of the cap layer 5 in FIGS. 1, 2, 6, and 9 to 13 does not necessarily have to be processed vertically, for example, as shown in FIG. 7. The slope may be formed so that the bottom is wide like the cap layer 5B of the second aspect, or the slope part is curved taper like the cap layer 5C of the third aspect shown in FIG. May be.

  As described above, by using the cap layers 5B and 5C shown in FIGS. 7 and 8, the effect of electrolytic relaxation that disperses the electric field applied to the end of the gate electrode 10 on the drain electrode 8 side can be obtained more remarkably. Therefore, there is an advantage that wet etching which is an isotropic processing technique can be adopted from the viewpoint of process. The second and third modes of the second embodiment are the same as the basic configuration of the first embodiment shown in FIG. 1 except for the cap layers 5B and 5C.

  Like the cap layers 5B and 5C in the second and third modes of the second embodiment, the cap layers 5B and 5C are formed to have the largest width on the surface in contact with the barrier layer 4 and to narrow the width as the distance from the barrier layer 4 increases. Thus, a heterojunction field effect transistor with an improved breakdown voltage can be realized by dispersing the electric field generated in the vicinity of the gate electrode 10 toward the drain electrode 8 pole side.

  (H) The drain electrode 8 and the source electrode 9 in FIGS. 1, 2, 6 to 8, 12, and 13 are not necessarily the cap layer 5 (precisely, for the cap layer for providing the cap layer 5. Even if it is not formed on the drain electrode Si injection region 6 and the source electrode Si injection region 7 formed selectively in the formation layer 25 (to be described in detail later), it is generated on the barrier layer 4 side of the channel layer 3. It is sufficient that an ohmic contact with the two-dimensional electron gas 12 is formed. For example, as in the fourth mode shown in FIG. 9, the drain electrode 8 and the drain electrode are contacted on the Si-injection region 6A under the drain electrode and the Si-injection region 7A under the source electrode formed in the barrier layer 4. 8 may be formed. The fourth mode of the second embodiment is the same as the embodiment shown in FIG. 1 except for the formation positions of the drain electrode 8 and the source electrode 9 and the structure of the Si injection region 6A under the drain electrode and the Si injection region 7A under the source electrode. The basic configuration is the same as that of the first embodiment.

  However, according to the description of the above item (A), the barrier layer 4 is configured to have a characteristic that the Al composition is higher than that of the cap layer 5, so that the barrier layer 4 is formed on the cap layer 5. When formed on the barrier layer 4, the barrier height between the metal and the semiconductor becomes high, and as a result, the contact resistance increases. Therefore, it should be noted that depending on the combination of Al compositions selected, the resistance may be lower when formed on the cap layer 5.

  (I) The drain electrode 8 and the source electrode 9 in FIG. 9 are not necessarily provided with an Si injection region under the electrode if an ohmic contact with the two-dimensional electron gas 12 generated on the channel layer 3 on the barrier layer 4 side is formed. There is no need, for example, a structure in which the drain electrode 8 and the source electrode 9 are in direct contact with the surface of the barrier layer 4 as in the fifth mode shown in FIG. 10, or as in the sixth mode shown in FIG. The drain electrode 8 and the source electrode 9 may be in direct contact with the surface of the channel layer 3. The fifth and sixth aspects of the second embodiment are the same as those shown in FIG. 1 except for the formation position of the drain electrode 8 and the source electrode 9 and the structure in which the Si implantation region 6 under the drain electrode and the Si implantation region 7 under the source electrode are not provided. This is the same as the basic configuration of the first embodiment shown in FIG.

  However, the resistance between the two-dimensional electron gas 12 generated on the side of the barrier layer 4 of the channel layer 3 and the source / drain electrodes 9 and 8 can be reduced when the Si injection region is formed under the electrode. This is advantageous for increasing the current and output of the transistor, and can be said to be a more preferable structure. Note that it is not always necessary to implant Si into the Si implantation region, and it is a condition that an n-type impurity is doped at a high concentration, and a material that forms an n-type impurity level in the nitride semiconductor (for example, O , C, N vacancies, etc.) may be doped.

  (J) The drain electrode 8 and the source electrode 9 in FIGS. 1, 2, and 6 to 13 are not necessarily Ti / Nb / Pt. If ohmic characteristics are obtained, Ti, Al, Nb, Hf , Zr, Sr, Ni, Ta, Au, Mo, W, etc., or a multilayer film made of these metals.

  (K) The gate electrode 10 (10A) in FIG. 1, FIG. 6 to FIG. 11 and FIG. 13 is not necessarily in direct contact with the barrier layer 4 as shown in these drawings. As in the embodiment, a MIS (Metal-Insulator-Semiconductor) structure in contact with the dielectric film 11 may be used. Such a configuration is advantageous in that the gate leakage current can be reduced and the threshold value can be shifted. The seventh mode of the second embodiment is the same as the basic configuration of the first embodiment shown in FIG. 1 except for the MISU structure by the dielectric film 11.

  (L) The gate electrode 10 in FIGS. 1, 2, and 6 to 12 does not necessarily have a T-shaped cross section as shown in these drawings. For example, the eighth electrode shown in FIG. The gate electrode 10A having a Γ-shaped cross-section as in the embodiment may be rectangular, trapezoidal, or Y-shaped. The eighth mode of the second embodiment is the same as the basic configuration of the first embodiment shown in FIG. 1 except for the structure of the gate electrode 10A.

(M) The gate electrode 10 in FIGS. 1, 2, and 6 to 13 is not necessarily made of Ni / Au, but a metal such as Ti, Al, Pt, Au, Ni, Pd, IrSi, PtSi, NiSi. _It may be formed of a silicide such as ₂ or a nitride metal such as TiN or WN, or a multilayer film composed of these.

  (N) It is not necessary to employ all the above-mentioned structures individually, and a structure combining them may be used.

  Although only the minimum necessary elements that operate as a transistor are described above, it is assumed that the device is finally used in a structure in which wirings, via holes, and the like are formed.

<Embodiment 3>
14 to 20 are cross-sectional views showing an example of a method for manufacturing a heterojunction FET made of a nitride semiconductor having the structure shown in FIG. In these drawings, the same reference numerals as those in FIGS. 1, 2, and 6 to 13 denote the same or corresponding parts. A method for manufacturing a heterojunction FET according to the third embodiment will be described below with reference to FIGS.

First, as shown in FIG. 14, by applying an epitaxial growth method such as MOCVD method or MBE method on the semi-insulating SiC substrate 1, the buffer layer 2, the channel layer 3 made of GaN, Al _0.28 Ga _{0. The} barrier layer 4 made of ₇₂ N and the cap layer forming layer 25 made of GaN (the layer in which the final remaining portion becomes the cap layer 5) are epitaxially grown sequentially from the bottom.

Next, as shown in FIG. 15, using the mask pattern 13 such as a resist pattern as a mask, an implantation dose amount of 1 × 10 ¹³ to 1 is applied to a region immediately below the drain electrode 8 and the source electrode 9 by using an ion implantation method or the like. Under the conditions of × 10 ¹⁷ (cm ⁻² ) and implantation energy of 10 to 1000 (keV), an n-type impurity in a nitride semiconductor such as Si is introduced into a desired region. As a result, the Si implantation region 6 under the drain electrode and the Si implantation region 7 under the source electrode are selectively formed from the upper layer portion of the channel layer 3 to the regions of the barrier layer 4 and the cap layer forming layer 25.

  Then, as shown in FIG. 16, after removing the mask pattern 13, for example, a metal such as Ti, Al, Nb, Hf, Zr, Sr, Sr, Ta, Au, Mo, W, or a multilayer composed of these metals. A drain electrode 8 and a source electrode 9 made of a film are deposited using an evaporation method or a sputtering method, and are formed on the Si implantation region 6 under the drain electrode and the Si implantation region 7 under the source electrode by a lift-off method or the like.

After that, as shown in FIG. 17, the gate electrode formation scheduled region 20 (the gate electrode 10 of the cap layer 5 is formed by a dry etching method using Cl ₂ or the like using the mask pattern 14 such as a resist pattern or an insulating film as a mask. The region to be formed) is removed to form a recess opening. When the Al composition ratio of the cap layer forming layer 25 and the barrier layer 4 is different, in addition to a chlorine-based gas such as Cl ₂ during etching, a fluorine-based gas such as oxygen or SF ₆ is used. Therefore, it becomes possible to selectively etch only the cap layer forming layer 25, and the controllability of the etching depth is improved.

Then, as shown in FIG. 18, the mask pattern 14 used as a mask in the step shown in FIG. 17 is removed by wet etching or the like. Thereafter, patterning is performed, and a metal such as Ti, Al, Pt, Au, Ni, Pd, a silicide such as IrSi, PtSi, NiSi ₂ , a nitride metal such as TiN, WN, or a multilayer film composed of these metals. A gate electrode forming material is deposited by an evaporation method, and the gate electrode 10 is formed by a lift-off method or the like. The method for forming the gate electrode 10 is not limited to the vapor deposition method, and other possible means such as a sputtering method may be used.

  Next, as shown in FIG. 19, a protective film is formed by patterning only in the region of the cap layer 5 to be left (region in the vicinity of the drain direction gate electrode), and the protective film and the umbrella portion of the gate electrode 10 are used as a mask. A position that does not reach the drain electrode 8 in the direction of the drain electrode from the position adjacent to the I-part side surface of the gate electrode 10 (first position) by the dry etching method or the wet etching method (second position; from the drain electrode 8) The cap layer forming layer 25 other than the region in the vicinity of the drain direction gate electrode, which is a region extending to a position separated by a predetermined distance), is removed. As a result, the cap layer 5 having a desired formation width can be formed by the remaining cap layer forming layer 25.

  At this time, the region in the vicinity of the drain-direction gate electrode, which is the formation region of the cap layer 5, has an electric field intensity peak generated in the channel layer 3 at the end of the gate electrode 10 on the drain electrode 8 side as described above. By setting the region where an electric field exceeding 10% is applied, it is possible to obtain a heterojunction FET capable of reducing the on-resistance within a possible range while maintaining the withstand voltage.

  Further, like the cap layers 5B and 5C of the second and third aspects of the second embodiment shown in FIGS. 7 and 8, the width is the widest on the surface in contact with the barrier layer 4, and the distance from the barrier layer 4 increases as the distance from the barrier layer 4 increases. The heterojunction field-effect transistor can be realized in which the breakdown voltage is improved by dispersing the electric field generated in the vicinity of the gate electrode 10 in the direction toward the drain electrode 8 pole side by forming the gate electrode so as to be narrow.

  Finally, as shown in FIG. 20, all of the drain electrode 8, the source electrode 9, and the gate electrode 10 except for a region that should not be insulated, such as a pad electrode provided for forming a wiring. The region is covered with the dielectric film 11 using, for example, an ALD (Atomic Layer Deposition) method. That is, from the drain electrode 8 to the source electrode 9, on the surface and side surface of the Si implantation region 6 under the drain electrode, on the surface of the barrier layer 4, on the side surface and surface of the cap layer 5, and on the side surface, surface and back surface of the gate electrode 10 The dielectric film 11 is formed on the surface and back surface of the umbrella portion of the gate electrode 10, on the surface of the barrier layer 4, and on the side surface and surface of the Si implantation region 7 under the source electrode.

  The main purpose of forming the dielectric film 11 is to prevent the formation of a surface alteration layer due to oxygen or moisture in the atmosphere in order to ensure long-term reliability of the device. Therefore, as a characteristic required for the dielectric film 11, it is better if the dielectric film 11 has a high dielectric breakdown electric field and excellent chemical resistance under the condition that it is an insulating film having excellent moisture resistance and oxidation resistance.

  With the above method, the heterostructure field effect transistor of Embodiment 1 having the structure shown in FIG. 1 can be manufactured. Further, by omitting the step shown in FIG. 20, the structure of the modification of the first embodiment shown in FIG. 2 can be realized. Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device through a formation process of wiring, via holes, and the like.

  In addition, although typical conditions were described above, the heterojunction field effect which consists of a nitride semiconductor with which the effect of this invention is acquired even if it changes with conditions (a)-(g) as shown below Type transistors can be manufactured.

  (A) In the case where the ohmic electrodes (drain electrode 8 and source electrode 9) are not formed in the step shown in FIG. 16, the Si implantation region 6 under the drain electrode and the Si implantation region 7 under the source electrode are also combined in the step shown in FIG. After the removal, the drain electrode 8 and the source electrode 9 are formed by the method shown in FIG. 16, so that Si implantation under the drain electrode formed in the barrier layer 4 as in the fourth embodiment shown in FIG. 9 is performed. The drain electrode 8 and the source electrode 9 are formed on the region 6A and the Si implantation region 7A under the source electrode, or the drain electrode 8 and the source electrode 9 are formed on the barrier layer 4 as in the fifth mode shown in FIG. Thus, the heterojunction FET made of the nitride semiconductor of the fourth and fifth aspects can be manufactured.

  (B) After the steps up to FIG. 19 are completed in the same manner as in (a) above, the regions where the drain electrode 8 and the source electrode 9 are to be formed are patterned and the barrier layer 4 is removed by etching, and then exposed. The drain electrode 8 and the source electrode 9 are formed on the channel layer 3 by the method shown in FIG. 16, whereby the structure of the sixth mode shown in FIG. 11 (the drain electrode 8 and the source electrode 9 are formed on the channel layer 3 is formed. Heterojunction FETs of nitride semiconductors of the structure formed can be produced.

  (C) In the process shown in FIG. 14, when the channel layer 3, the barrier layer 4 and the cap layer 5 are grown, trimethylammonium, trimethylgallium, trimethylindium, ammonia or n-type which is a source gas of the nitride semiconductor By adjusting the pressure, flow rate, temperature, and introduction time of silane as a dopant raw material, and forming the channel layer 3, the barrier layer 4, and the cap layer 5 to have a desired composition, film thickness, and doping concentration, Various types of nitride semiconductor heterojunction FETs shown in the first and second embodiments can be manufactured.

  (D) When the etching shown in FIG. 19 is performed, the shape of the cap layer 5 after processing can be manipulated to some extent by combining a plurality of etching methods for adjusting the etching time and the gas flow rate. A nitride having the structure of the first to third modes as shown in FIGS. 6 to 8 of the second embodiment is formed by forming the desired shape and then performing the process shown in FIG. A semiconductor heterojunction field effect transistor can be manufactured.

  (E) After the process up to FIG. 17 is completed, the process shown in FIG. 19 and the process shown in FIG. 20 are performed without performing the process shown in FIG. By forming the gate electrode 10, the nitride semiconductor heterojunction field effect transistor of the seventh aspect having the structure (MIS structure) as shown in FIG. 12 of the second embodiment can be manufactured.

  (F) After the steps up to FIG. 17 are completed, the step shown in FIG. 19 is performed without performing the step shown in FIG. 18, and then the gate electrode 10 is formed by the method shown in FIG. A nitride semiconductor heterojunction field effect transistor having the gate electrode 10A of the eighth aspect having the structure as shown in FIG. 13 of the second embodiment is formed by forming the dielectric film 11 by the process shown in FIG. Can do.

  In this case, in the process shown in FIG. 19, a protective film is formed by patterning only in a region of the cap layer 5 to be left (region in the vicinity of the drain direction gate electrode), and a dry etching method or a wet etching method is performed using the protective film as a mask. Thus, a position that does not reach the drain electrode 8 in the direction of the drain electrode from the position adjacent to the side surface of the gate electrode formation planned region 20 (first position) (second position; a position that is separated from the drain electrode 8 by a predetermined distance) This is a step of removing the cap layer forming layer 25 other than the region in the vicinity of the drain-direction gate electrode, which is a region extending to).

  (G) It is not necessary to adopt all the processes described above, and the processes may be combined appropriately.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 semi-insulating SiC substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5, 5A to 5C cap layer, 6, 6A Si injection region under drain electrode, 7, 7A Si injection region under source electrode, 8 drain electrode , 9 Source electrode, 10, 10A Gate electrode, 11 Dielectric film, 12 Two-dimensional electron gas.

Claims (9)

A channel layer made of a nitride semiconductor formed above the substrate;
A barrier layer made of a nitride semiconductor different from the channel layer formed on the channel layer;
A gate electrode selectively provided on the barrier layer;
A source electrode and a drain electrode, each of which is independently provided at a predetermined distance while sandwiching the gate electrode above the substrate;
A cap layer made of a nitride semiconductor, selectively provided on the barrier layer between the gate electrode and the drain electrode;
The cap layer is formed only in a region near the drain direction gate electrode, which is a region extending from a first position adjacent to the side surface of the gate electrode to a second position that does not reach the drain electrode in the direction of the drain electrode. It is characterized by
Heterojunction field effect transistor. The heterojunction field effect transistor of claim 1,
The cap layer is
It has a thickness of 28 nm or more,
Heterojunction field effect transistor. A heterojunction field effect transistor according to claim 1 or claim 2, wherein
The region near the drain-direction gate electrode in the cap layer includes a region corresponding to the region of the channel layer that exceeds the electric field strength of 10% of the maximum value on the basis of the maximum value of the electric field strength applied to the channel layer.
Heterojunction field effect transistor. The heterojunction field effect transistor according to any one of claims 1 to 3,
The cap layer is
It is characterized by having a wide barrier layer structure that is widest on the surface in contact with the barrier layer and narrows as the distance from the barrier layer increases.
Heterojunction field effect transistor. A heterojunction field effect transistor according to any one of claims 1 to 4,
A surface protective film formed on the barrier layer and the cap layer between the source electrode and the drain electrode and covering the surface and side surfaces of the barrier layer and having an insulating property;
Heterojunction field effect transistor. (a) forming a channel layer made of a nitride semiconductor above the substrate;
(b) forming a barrier layer made of a nitride semiconductor different from the channel layer on the channel layer;
(c) forming a cap layer forming layer made of a nitride semiconductor on the barrier layer, wherein a central portion of the cap layer is defined as a gate formation scheduled region,
(d) forming a source electrode and a drain electrode above the substrate at a predetermined distance with the gate formation scheduled region interposed therebetween;
(e) forming a gate electrode in the gate formation scheduled region in the cap layer forming layer, and after performing the steps (d) and (e), the source electrode, the drain electrode, and the gate electrode Are formed independently,
(f) With respect to the cap layer forming layer, the gate electrode formation planned region or a region extending from a first position adjacent to the gate electrode to a second position not reaching the drain electrode in the direction of the drain electrode A step of removing a region other than the region near the drain direction gate electrode, and the region near the drain direction gate electrode of the cap layer forming layer remaining after the execution of the step (f) is a cap layer.
A method of manufacturing a heterojunction field effect transistor. A method of manufacturing a heterojunction field effect transistor according to claim 6,
The drain direction gate electrode vicinity region includes a region corresponding to the region of the channel layer exceeding the electric field strength of 10% of the maximum value on the basis of the maximum value of the electric field strength applied to the channel layer.
A method of manufacturing a heterojunction field effect transistor. A method of manufacturing a heterojunction field effect transistor according to claim 6,
The cap layer is
The widest surface on the surface in contact with the barrier layer, and as the distance from the barrier layer, the barrier layer wide structure in which the width is reduced in the direction away from the drain electrode,
A method of manufacturing a heterojunction field effect transistor. A method of manufacturing a heterojunction field effect transistor according to any one of claims 6 to 8,
(g) further comprising a step of forming a surface protective film having an insulating property so as to cover the surface and side surfaces of the barrier layer and the cap layer between the source electrode and the drain electrode;
A method of manufacturing a heterojunction field effect transistor.