JP2014229767A - Heterojunction field effect transistor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a heterojunction field effect transistor having a low on resistance and a high breakdown voltage.SOLUTION: The heterojunction field effect transistor has a barrier layer 4, a source electrode 5, a drain electrode 6, and a gate electrode 7 held by the source electrode 5 and the drain electrode 6, and includes an electrode group provided while being arranged on a first principal surface 40 side of the barrier layer 4, a channel layer 3 provided in contact with a second principal surface 41 facing the first principal surface 40, and having a band gap narrower than the barrier layer 4, and an impurity supply layer 9d provided in contact with the first principal surface 40 while isolated from the gate electrode 7 between the drain electrode 6 and gate electrode 7, and containing impurities of the barrier layer 4.

Description

  The present invention relates to a heterojunction field effect transistor.

  Nitride semiconductors have a high breakdown field strength. Therefore, a nitride semiconductor is expected as a transistor material from the viewpoint of increasing the output of the transistor.

  On the other hand, the heterojunction field effect transistor has a uniformly high electron concentration in the device region. For this reason, the gate leakage current is large, so that it is difficult to obtain a high breakdown voltage.

  The techniques disclosed in Patent Document 1 and Patent Document 2 have a structure in which a part of a barrier layer (functioning as an electron supply layer) under a gate electrode is dry-etched in order to improve a breakdown voltage in a heterojunction field effect transistor. adopt. Such a structure is effective in reducing the electron concentration and increasing the breakdown voltage by dispersing the electric field strength.

  Patent Document 3 discloses the formation of an element isolation region by ion implantation, which will be described later.

JP 2006-286740 A JP 2011-146446 A JP 2004-87587 A

  Etching a portion of the barrier layer requires advanced etching control techniques. Such a need is undesirable from the standpoint of stable production of the product.

  Etching of the barrier layer not only lowers the electron concentration under the gate electrode but also damages the semiconductor layer (including the channel layer serving as the electron transit layer). Such a phenomenon leads to an increase in channel resistance, making it difficult to obtain a large current in the heterojunction field effect transistor.

  Therefore, from the viewpoint of higher output, even if a nitride semiconductor is employed as the material of the transistor, a high output heterojunction field effect transistor cannot be obtained by etching the barrier layer to obtain the above structure. In addition, there is a problem that stable production of products is not easy.

  In view of the above problems, the present invention provides a structure in a heterojunction field-effect transistor that avoids characteristic deterioration due to etching of a region in which an electron supply layer substantially travels with carriers, and thus includes a transistor. An object of the present invention is to provide a technique for increasing the withstand voltage and obtaining a high current.

  A first aspect of the heterojunction field effect transistor according to the present invention includes the following. A first semiconductor layer having a first band gap, a source electrode, a drain electrode, and a gate electrode sandwiched between the source electrode and the drain electrode, and arranged on the first main surface side of the first semiconductor layer An electrode group provided in contact with the second main surface opposite to the first main surface of the first semiconductor layer and having a second band gap narrower than the first band gap And a first impurity supply layer that is provided between the drain electrode and the gate electrode so as to be isolated from the gate electrode and in contact with the first main surface, and includes an impurity of the first semiconductor layer.

  A second aspect of the heterojunction field effect transistor according to the present invention is the first aspect, and is provided in contact with the first main surface between the source electrode and the gate electrode, The semiconductor device further includes a second impurity supply layer containing impurities for one semiconductor layer.

  A third aspect of the heterojunction field effect transistor according to the present invention is the first aspect or the second aspect thereof, wherein the first semiconductor layer is composed of a III-V group compound semiconductor, The impurity for the semiconductor layer is a group IV element.

  A fourth aspect of the heterojunction field effect transistor according to the present invention is any one of the first to third aspects, wherein the gate electrode is at least on the side far from the first semiconductor layer. A ridge extending toward the drain electrode is provided.

  A fifth aspect of the heterojunction field effect transistor according to this invention is any one of the first to fourth aspects, wherein the gate electrode and the first main surface are insulated.

  A first aspect of a method for manufacturing a heterojunction field effect transistor according to the present invention includes the following steps: (a) a first semiconductor layer having a first band gap and a first semiconductor layer having a narrower width than the first band gap. Forming a second semiconductor layer having a band gap of 2; (b) forming a source electrode and a drain electrode on the first semiconductor layer; and the source electrode and the drain on the first semiconductor layer. Forming a gate electrode sandwiched between electrodes; and (c) being provided in contact with the first semiconductor layer so as to be isolated from the gate electrode and between the drain electrode and the gate electrode, Forming a first impurity supply layer containing impurities for the layer;

  A second aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention is the first aspect thereof, and (d) is in contact with the first semiconductor layer between the source electrode and the gate electrode. And a second impurity supply layer including an impurity for the first semiconductor layer.

  A third aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention is the second aspect, and the steps (c) and (d) are performed in parallel. And (e) executed before the steps (c) and (d), between the drain electrode (6) and the gate electrode (7), wherein the source electrode, the drain electrode, and the gate electrode are The method further includes the step of forming an insulating layer (8) provided in a region (S1) in contact with the gate electrode 7 and isolated from the drain electrode in the alignment direction. The insulating layer is Al oxide, nitride, or oxynitride.

  A fourth aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention is the third aspect thereof, wherein in the step (e), the first step is performed after the step (e1) and the step (b). Forming an insulating layer on the semiconductor layer; (e2) covering the region and the end of the gate electrode adjacent to the region, and not covering the end of the gate electrode on the source electrode side A layer is provided by patterning, and the insulating layer is patterned by employing etching using the source electrode, the drain electrode, the gate electrode, and the resist layer as a mask.

  A fifth aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention is the second aspect, and the steps (c) and (d) are performed in parallel. And (e) executed after the steps (c) and (d), between the drain electrode and the gate electrode, in the direction in which the source electrode, the drain electrode, and the gate electrode are arranged. A step of forming an insulating layer in a region in contact with the drain electrode and isolated from the drain electrode. Both the first impurity supply layer and the second impurity supply layer are made of SiN, and etching is employed in the steps (c) and (d).

  A sixth aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention is the fourth aspect, and wet etching is employed for etching the insulating layer.

  A seventh aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention is the fifth aspect, and wet etching is employed for etching the first impurity supply layer and the second impurity supply layer. Is done.

  In the first aspect of the heterojunction field effect transistor according to the present invention and the first aspect of the method for manufacturing the heterojunction field effect transistor according to the present invention, the first semiconductor layer and the second semiconductor layer are each an electron supply layer. , Function as an electronic travel layer. The first impurity supply layer supplies impurities to the first semiconductor layer immediately adjacent to the first impurity supply layer and has a small effect of supplying impurities to the vicinity of the gate electrode. Therefore, the carrier concentration of the first semiconductor layer is low near the gate electrode and high near the drain electrode. Therefore, while increasing the carrier concentration in the vicinity of the drain electrode to reduce the access resistance, the breakdown voltage is increased by suppressing the carrier concentration at the gate electrode end on the drain electrode side where the electric field is concentrated.

  Moreover, it is possible to avoid damage caused by etching on the region where the carrier travels substantially.

  According to the second aspect of the heterojunction field effect transistor according to the present invention and the second aspect of the method for manufacturing the heterojunction field effect transistor according to the present invention, not only the access resistance in the vicinity of the drain electrode but also the source electrode The nearby access resistance is also reduced, which contributes to higher current.

  According to the third aspect of the heterojunction field effect transistor of the present invention, the first semiconductor layer can be an n-type semiconductor. This leads to supply of electrons as carriers that become a two-dimensional electron gas in the second semiconductor layer.

  According to the fourth aspect of the heterojunction field effect transistor of the present invention, the breakdown voltage can be improved.

  According to the fifth aspect of the heterojunction field effect transistor of the present invention, the gate leakage current can be reduced.

  According to the third aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention, the insulating layer can be formed by etching using an alkaline solution that does not increase the resistance of the source electrode, the drain electrode, and the gate electrode.

  According to the fourth aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention, the etching solution for the insulating layer does not infiltrate at the position where the gate electrode and the insulating layer are in contact. This is desirable from the viewpoint of preventing the first impurity supply layer from being inserted into the boundary between the gate electrode and the insulating layer.

  According to the fifth aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention, the patterning accuracy of the first impurity supply layer and the second impurity supply layer is high. Therefore, the manufacturing yield is improved.

  According to the sixth aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention, it is possible to obtain a high-current transistor characteristic excellent in high-frequency characteristics.

  According to the seventh aspect of the method for manufacturing a heterojunction field effect transistor according to the present invention, the transistor has a high breakdown voltage.

1 is a cross-sectional view illustrating the configuration of a heterojunction field effect transistor according to a first embodiment of the invention; It is a graph which shows the horizontal direction dependence of the carrier concentration of a channel layer. It is a graph which shows the horizontal direction dependence of the carrier concentration of a channel layer. It is a graph which shows the horizontal direction dependence of the carrier concentration of a channel layer. It is sectional drawing which illustrates the structure at the time of the 1st process having been completed of the manufacturing method concerning Embodiment 2 of this invention. It is sectional drawing which illustrates the structure at the time of the 2nd process of the manufacturing method concerning Embodiment 2 of this invention having been complete | finished. It is sectional drawing which illustrates the structure at the time of the 3rd process of the manufacturing method concerning Embodiment 2 of this invention having been complete | finished. It is sectional drawing which illustrates the structure at the time of the 4th process of the manufacturing method concerning Embodiment 2 of this invention having been complete | finished. It is sectional drawing which illustrates the structure at the time of finishing the 5th process of the manufacturing method concerning Embodiment 2 of this invention. It is sectional drawing which illustrates the structure at the time of the 6th process of the manufacturing method concerning Embodiment 2 of this invention having been complete | finished. It is sectional drawing which illustrates the desirable structure at the time of the 6th process of the manufacturing method concerning Embodiment 2 of this invention having been complete | finished. It is sectional drawing which illustrates the structure at the time of the 7th process of the manufacturing method concerning Embodiment 2 of this invention having been complete | finished. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 3 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 4 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 4 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 4 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 4 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 5 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 5 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 5 of this invention. It is sectional drawing which illustrates the structure of the heterojunction field effect transistor concerning Embodiment 5 of this invention. 1 is a top view illustrating a configuration of a heterojunction field effect transistor according to a first exemplary embodiment of the present invention; It is a graph which shows the electric field strength in the heterojunction field effect transistor concerning Embodiment 4 of this invention.

Embodiment 1 FIG.
1 is a cross-sectional view illustrating an example of the structure of a heterojunction field effect transistor according to a first embodiment of the present invention, and FIG. 22 is a top view thereof. In these drawings, only the minimum necessary elements that operate as transistors are drawn, and other elements are omitted. For example, an interlayer insulating film covering the electrode group, a via hole provided in the interlayer insulating film, a wiring layer wired to the electrode group through the via hole, and the like are omitted.

  The substrate 1 is, for example, a hexagonal substrate, and the buffer layer 2 is provided on the (0001) plane. Examples of the material of the substrate 1 include sapphire and SiC.

  On the buffer layer 2, a channel layer 3 and a barrier layer 4, both made of semiconductor, are formed in this order. The band gap of the channel layer 3 is smaller than the band gap of the barrier layer 4.

  Therefore, the channel layer 3 and the barrier layer 4 form a so-called heterojunction, and electrons are supplied from the barrier layer 4 to the heterointerface of the channel layer 3. The electrons generate high-concentration carriers called 2-dimensional electron gas and move according to the electric field applied from the outside.

  Therefore, the channel layer 3 and the barrier layer 4 are grasped as a so-called electron transit layer and electron supply layer, respectively. In particular, by using an undoped semiconductor in the channel layer 3, the two-dimensional electron gas has high mobility, and a transistor using the channel layer 3 and the barrier layer 4 can realize high frequency and high current. For example, a III-V compound semiconductor is employed for the channel layer 3 and the barrier layer 4.

Specifically, for example, the channel layer 3, for example, GaN or _{Al z Ga 1-z N (} 0 <z <1), is employed as the barrier layer _{4 In x Al y Ga 1-} x-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) is employed. Since such a nitride semiconductor has a high dielectric breakdown electric field strength, as described above, a transistor employing the nitride semiconductor is expected to have a high output.

  When the material of this example is adopted for the channel layer 3 and the barrier layer 4, for example, a laminated structure of AlN and AlGaN is adopted as the material of the buffer layer 2.

  The following electrodes are arranged and provided on the main surface (hereinafter referred to as “first main surface”) 40 side of the barrier layer 4 opposite to the substrate 1: a source electrode 5, a drain electrode 6, and a source electrode 5. And a gate electrode 7 sandwiched between the drain electrode 6 and the gate electrode 7.

  When the first main surface 40 is grasped as described above, the channel layer 3 is provided in contact with the second main surface 41 of the barrier layer 4, and the second main surface 41 is in contact with the first main surface 40 of the barrier layer 4. It can be understood that they are facing each other.

  Impurity supply layers 9 s and 9 d are provided in contact with the barrier layer 4 on the first main surface 40. The impurity supply layers 9 s and 9 d are insulators and contain impurities for the barrier layer 4.

  For example, when the channel layer 3 and the barrier layer 4 are III-V compound semiconductors, group IV elements are employed as the impurities. The group IV element functions as an n-type impurity with respect to the group III-V compound. Therefore, by adopting such an element as the material of the impurity supply layers 9s and 9d and the barrier layer 4, the barrier layer 4 can be made an n-type semiconductor. This leads to supply of electrons as carriers that become a two-dimensional electron gas in the channel layer 3.

As described above, when In _x Al _y Ga _1-xy N is employed as the barrier layer 4, Si or Ge is employed as the impurity. Examples of the material of the impurity supply layers 9s and 9d include SiN.

  The impurity supply layer 9 s is provided between the source electrode 5 and the gate electrode 7 in contact with the barrier layer 4 on the first main surface 40.

  The impurity supply layer 9 d is provided between the drain electrode 6 and the gate electrode 7, isolated from the gate electrode 7, and in contact with the barrier layer 4 on the first main surface 40.

  In the channel layer 3 and the barrier layer 4, a part of the source electrode 5 opposite to the gate electrode 7 and a part of the drain electrode 6 opposite to the gate electrode 7 are both replaced with the element isolation region 10. A specific replacement method will be described later.

  The impurity supply layers 9 s and 9 d may be provided on the element isolation region 10.

  Si and Ge included in the impurity supply layers 9s and 9d act as n-type dopants for GaN. Therefore, the barrier layer 4 is an n-type semiconductor in the region where the impurity supply layers 9s and 9d are provided. Along with this, the carrier concentration of the channel layer 3 increases at positions facing the impurity supply layers 9s and 9d.

  In the semiconductor device configured as described above, the impurity supply layer 9d supplies impurities to the nearest barrier layer 4 and has little effect of supplying impurities to the barrier layer in the vicinity of the gate electrode 7. Therefore, the carrier concentration of the barrier layer 4 is low near the gate electrode 7 and high near the drain electrode 6 between the drain electrode 6 and the gate electrode 7.

  By applying appropriate voltages to the source electrode 5, the drain electrode 6, and the gate electrode 7, the movement of the two-dimensional electron gas in the channel layer 3 can be controlled. This uses the above configuration as a field effect transistor.

  When the transistor is operated, the carrier concentration in the region where the highest electric field is applied is lowered, so that the gate leakage current can be reduced and the breakdown voltage can be improved.

  That is, according to the semiconductor device of this embodiment, while increasing the carrier concentration in the vicinity of the drain electrode to reduce the access resistance, the carrier concentration is suppressed and increased at the gate electrode end on the drain electrode side where the electric field is concentrated. Withstand pressure.

  Further, the carrier concentration of the channel layer 3 increases at a position facing the impurity supply layer 9s. Therefore, the above structure reduces not only the access resistance in the vicinity of the drain electrode but also the access resistance in the vicinity of the source electrode, which contributes to a large current.

  As described above, the impurity supply layer 9 d is provided between the drain electrode 6 and the gate electrode 7 and is isolated from the gate electrode 7. Between the gate electrode 7 and the impurity supply layer 9d, the insulating layer 8 is provided in contact with the barrier layer 4 on the first main surface 40.

  It can also be understood that the insulating layer 8 and the impurity supply layers 9s and 9d protect the barrier layer 4.

  The insulating layer 8 does not supply impurities to the barrier layer 4 compared to the impurity supply layers 9s and 9d. For example, the insulating layer 8 contains neither Si nor Ge. Therefore, in the above structure, the effect of suppressing the carrier concentration at the gate electrode end on the drain electrode side where the electric field is concentrated is not hindered by the insulating layer 8.

  Further, it does not matter whether the source electrode 5, the drain electrode 6, or the gate electrode 7 supplies impurities to the barrier layer 4. Even if the impurity is supplied from the gate electrode 7 to the barrier layer 4, the carrier concentration at the position facing the impurity supply layers 9s and 9d should be higher than the carrier concentration at the position facing the gate electrode 7 and the insulating layer 8. .

  2 to 4 are graphs showing the lateral dependence of the carrier concentration C of the channel layer 3. Here, the horizontal direction is a direction in which the source electrode 5, the drain electrode 6, and the gate electrode 7 are arranged. In these figures, regions Ss, S2s, Sg, S1, S2d, and Sd are on the first main surface 40 side in the lateral direction, respectively, source electrode 5 (source electrode), impurity supply layer 9s, gate electrode 7 (gate electrode) ), A region where the insulating layer 8, the impurity supply layer 9d, and the drain electrode 6 (drain electrode) are provided.

  FIG. 2 shows a case where the carrier concentration C in the region S1 is equal to the carrier concentration C in the region Sg. Such a distribution of the carrier concentration C is obtained, for example, when neither the gate electrode 7 nor the insulating layer 8 supplies the above-described impurities to the barrier layer 4.

  FIG. 3 shows a case where the carrier concentration C in the region S1 is larger than the carrier concentration C in the region Sg. Such distribution of carrier concentration C is desirable from the viewpoint of reducing access resistance and increasing current.

  FIG. 4 shows a case where the carrier concentration C in the region Sg is larger than the carrier concentration C in the region S1. Such distribution of the carrier concentration C is desirable from the viewpoint of improving the breakdown voltage.

  Since the increase in current and the increase in breakdown voltage are in a trade-off relationship, the magnitude relationship between the carrier concentration C in the region S1 and the carrier concentration C in the region Sg is set in accordance with desired device characteristics. Such setting of the magnitude relationship can be realized by controlling the amount of impurities in the barrier layer 4 in the gate electrode 7 and the insulating layer 8.

Embodiment 2. FIG.
In this embodiment mode, a method for manufacturing the semiconductor device shown in Embodiment Mode 1 will be described.

  FIG. 5 is a cross-sectional view illustrating the configuration at the time when the first step of the method is completed. By applying an epitaxial growth method such as MOCVD method or MBE method on the substrate 1, the buffer layer 2, the channel layer 3, and the barrier layer 4 are formed.

As described in the first embodiment, for example, SiC is used as the material of the substrate 1, a laminated structure of AlN and AlGaN is used as the material of the buffer layer 2, and GaN or Al is used as the material of the channel layer 3, for example. _{z Ga 1-z N (0} <z <1) is adopted, for example, _in x as material of the barrier layer _{4 Al y Ga 1-x-} y N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 < x + y ≦ 1) is adopted.

  FIG. 6 is a cross-sectional view illustrating the configuration at the time when the second step of the method is completed. A metal film of a source electrode 5 and a drain electrode 6 made of metal, for example, Ti / Al, is formed on the barrier layer 4. For example, a metal film made of Ti / Al is deposited on the barrier layer 4 by vapor deposition or sputtering. Then, the metal film is selectively removed by applying a lift-off method or the like. The metal film remaining without being removed is employed as the source electrode 5 and the drain electrode 6.

  FIG. 7 is a cross-sectional view illustrating the configuration when the third step of the method is completed. The element isolation region 10 is formed in the channel layer 3 and the barrier layer 4 outside the region for manufacturing the transistor, that is, outside the region sandwiched between the source electrode 5 and the drain electrode 6 in the above-mentioned “lateral direction”.

  For example, as shown in Patent Document 3, the element isolation region 10 is formed by implanting zinc ions, for example. Since this formation is known from Patent Document 3, the details thereof are omitted here.

  Alternatively, the channel layer 3 and the barrier layer 4 may be etched at a position where the element isolation region 10 is to be formed to form a groove, and an insulator may be embedded in the groove. Such etching of the channel layer 3 and the barrier layer 4 is not easy. However, since it is performed outside the region sandwiched between the source electrode 5 and the drain electrode 6, it is not necessary to consider the above-mentioned adverse effect of reducing the electron concentration under the gate electrode.

  Of course, the formation of the element isolation region 10 by ion implantation is desirable from the viewpoint of improving electrical characteristics as disclosed in Patent Document 3.

  FIG. 8 is a cross-sectional view illustrating the configuration at the time when the fourth step of the method is completed. After the third step is completed, a gate electrode 7 made of metal, for example, Ni / Au is formed. For example, a metal film made of Ni / Al is deposited on the barrier layer 4, the source electrode 5, the drain electrode 6, and the element isolation region 10 by vapor deposition or sputtering. Then, the metal film is selectively removed by applying a lift-off method or the like. The metal film remaining without being removed is employed as the gate electrode 7.

  FIG. 9 is a cross-sectional view illustrating the configuration when the fifth step of the method is completed. In the fifth step, the insulating layer 8 is formed on the barrier layer 4. The thickness of the insulating layer 8 is 50 nm, for example.

  For the formation, for example, a sputtering method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method or the like is used. When the insulating layer 8 is formed, it is not desirable to damage the barrier layer 4 by heat or plasma. It is known that when such damage, for example, a nitrogen atom that is a constituent element of the barrier layer 4 is desorbed, vacancies are generated by the desorption and the vacancies behave as n-type dopants.

  Therefore, as a method for forming the insulating layer 8, it is desirable to use an ALD method in which plasma damage is small at a low temperature (preferably 400 ° C. or less).

As described in the first embodiment (see FIGS. 2 to 4), it is desirable that the carrier concentration of the channel layer 3 is not increased in the portion facing the region S1 than in the portions corresponding to the regions S2s and S2d. Therefore, the insulating layer 8 is desirably formed of a material containing Al, Zr, Hf, and Mg, which are elements that do not function as n-type dopants. For example, Al ₂ O ₃ can be given as the material.

  FIG. 10 is a cross-sectional view illustrating the configuration at the time when the sixth step of the method is completed. 9 with respect to the insulating layer 8 obtained in FIG. 9, the region between the drain electrode 6 and the gate electrode 7 and in contact with the gate electrode 7 in the above-mentioned “lateral direction” is isolated from the drain electrode 6 (FIG. 2). (Corresponding to the region S1 in FIG. 4) is provided. The resist layer 11 is obtained by being once provided on the entire surface of the barrier layer 4, the source electrode 5, the drain electrode 6, the gate electrode 7 and the insulating layer 8 having the structure obtained in FIG.

  The insulating layer 8 is etched using the resist layer 11, the source electrode 5, the drain electrode 6, and the gate electrode 7 as a mask, and only the insulating layer 8 covered with the resist layer 11 is left. Thereby, the barrier layer 4 is exposed at a position not covered with the source electrode 5, the drain electrode 6, the gate electrode 7, and the insulating layer 8.

  As a technique for etching such an insulating layer 8, it is not desirable to use dry etching using plasma. With this method, crystal defects and the like due to plasma damage are formed in the barrier layer 4. Such crystal defects lead to a phenomenon (current collapse) in which the carrier concentration is lowered or the current is reduced during high-frequency driving.

  On the other hand, the use of wet etching with a chemical as a method for etching the insulating layer 8 is particularly desirable when a nitride semiconductor is used as the material of the barrier layer 4. This is because the material generally has a very high chemical stability to chemicals, so that it is hardly etched or crystal defects are generated.

  Therefore, by applying wet etching when patterning the insulating layer 8, it is possible to obtain a high-current transistor characteristic with excellent high-frequency characteristics.

  Moreover, Al oxides, nitrides, or oxynitrides are etched not only into acids but also into alkaline solutions. On the other hand, alkaline solutions are less likely to corrode metals. Therefore, when an insulating material containing Al is used as the insulating layer 8, it is desirable to use an alkaline solution as an etching solution. This is because the insulating layer 8 can be selectively etched without increasing the resistance of the source electrode 5, the drain electrode 6 and the gate electrode 7 made of metal.

  FIG. 11 is a cross-sectional view illustrating a desirable configuration when the sixth step of the method is completed. The resist layer 11 shown in FIG. 10 covered only the insulating layer 8 to be left. On the other hand, the insulating layer 8 is preferably in contact with the end of the gate electrode 7 on the drain electrode 6 side. This is to prevent the impurity supply layer 9d formed later from being inserted into the boundary between the gate electrode 7 and the insulating layer 8.

  Therefore, in consideration of the patterning deviation of the resist layer 11, it is desirable to pattern the resist layer 11 so that the etching solution of the insulating layer 8 does not infiltrate the position where the gate electrode 7 and the insulating layer 8 are in contact with each other. Specifically, as shown in FIG. 11, the resist layer 11 is left at a position covering not only the insulating layer 8 to be left but also the end of the gate electrode 7 adjacent thereto.

  However, in order to remove the insulating layer 8 at the end of the gate electrode 7 on the source electrode 5 side, it is desirable that the resist layer 11 does not cover the end.

  FIG. 12 is a cross-sectional view illustrating the configuration when the seventh step of the method is completed. After removing the resist layer 11 from the configuration shown in FIG. 11, impurity supply layers 9 s and 9 d are formed between the source electrode 5 and the drain electrode 6 in a region excluding the gate electrode 7. The impurity supply layers 9s and 9d are made of, for example, an oxide, oxynitride, or nitride of Si or Ge. The impurity supply layers 9s and 9d are formed in parallel, for example, using a CVD method, a sputtering method, an ALD method, or the like.

  The thicknesses of the impurity supply layers 9s and 9d are both 50 nm, for example. However, it is not necessary to make it equal to the thickness of the insulating layer 8.

  As shown in FIG. 12, the impurity supply layers 9 s and 9 d may be formed on the element isolation region 10. This is because even if impurities (for the barrier layer 4) are supplied from the impurity supply layers 9s and 9d to the element isolation region 10, this does not affect the operation of the heterojunction field effect transistor to be completed later.

  As shown in FIG. 12, the impurity supply layer 9 d may be formed on the insulating layer 8. The carrier concentration of the channel layer 3 is determined by the state of the interface between the barrier layer 4 and the insulating layer 8 or the impurity supply layers 9s and 9d. Therefore, even if the impurity supply layer 9 d is provided for the barrier layer 4 through the insulating layer 8, the insulating layer 8 serves as a mask for the barrier layer 4 with respect to the impurity, and the impurity supply layer 9 d Does not affect carrier concentration.

  By using this shape, it is not necessary to perform processes such as patterning and etching on the impurity supply layers 9s and 9d, and the manufacturing process can be simplified.

  In the configuration shown in FIG. 12, the impurity supply layer 9d is also formed on the insulating layer 8, but the impurity supply layer 9d on the insulating layer 8 may be removed. The heterojunction field effect transistor shown in FIG. 1 has a mode in which the impurity supply layer 9d on the insulating layer 8 is removed.

  In the manufactured transistor, the carrier concentration of the channel layer 3 increases at a position facing the region S2d (see FIGS. 2 to 4) where the impurity supply layer 9d is formed. Therefore, while increasing the carrier concentration in the vicinity of the drain electrode to reduce the access resistance, the breakdown voltage is increased by suppressing the carrier concentration at the gate electrode end on the drain electrode side where the electric field is concentrated.

  Further, the carrier concentration of the channel layer 3 increases at a position facing the region S2s (see FIGS. 2 to 4) where the impurity supply layer 9s is formed. Therefore, not only the access resistance in the vicinity of the drain electrode but also the access resistance in the vicinity of the source electrode is reduced, which contributes to an increase in current of the transistor.

  Thereafter, an interlayer insulating film covering the electrode group, a via hole provided in the interlayer insulating film, a wiring layer to be wired to the electrode group through the via hole, and the like are formed. These formations are not directly related to the present embodiment, and are well-known techniques. Therefore, description of the formation is omitted here.

  In the above manufacturing method, the order of the steps of forming the source electrode 5, the drain electrode 6, the gate electrode 7, and the element isolation region 10 may be changed. For example, the element isolation region 10 may be formed before the source electrode 5 and the drain electrode 6 are formed.

Embodiment 3 FIG.
FIG. 13 is a cross-sectional view illustrating the structure of the heterojunction field effect transistor according to the third embodiment.

  The structure of the heterojunction field effect transistor according to the third embodiment is different from that of the first embodiment in that an insulating layer 8 is also formed on the impurity supply layers 9s and 9d. Such a configuration can be obtained by substituting the following steps for the fifth to seventh steps of the manufacturing method shown in the second embodiment.

  First, with respect to the structure in which the fourth step is completed in the second embodiment (see FIG. 8), an insulating layer, for example, SiN, which is a material of the impurity supply layers 9s and 9d, is formed on the barrier layer 4. The insulating layer is formed using a CVD method, a sputtering method, an ALD method, or the like.

  Next, the insulating layer is patterned by etching to expose the barrier layer 4 in the region S1 (FIGS. 2 to 4) where the insulating layer 8 is to be formed. The remaining insulating layer functions as impurity supply layers 9s and 9d. That is, in this embodiment, it can be understood that the impurity supply layers 9s and 9d are provided in parallel.

  As a method for etching the insulating layer which is a material of the impurity supply layers 9s and 9d, wet etching using hydrofluoric acid or the like is preferable to dry etching using plasma. This is because damage such as crystal defects on the surface of the barrier layer 4 is not formed in the etching. This contributes to increasing the breakdown voltage of the transistor.

Subsequently, the insulating layer 8 is formed on the barrier layer 4 exposed by the etching and the impurity supply layers 9s and 9d. The material of the insulating layer 8 is, for example, Al ₂ O ₃ , and a sputtering method, a CVD method, an ALD method, or the like is adopted for the formation.

  The insulating layer 8 is formed on the barrier layer 4 exposed between the drain electrode 6 and the gate electrode 7. Although the insulating layer 8 is also formed on the impurity supply layers 9s and 9d, the insulating layer 8 does not hinder the supply of impurities onto the barrier layer 4 by the impurity supply layers 9s and 9d at this position.

  In the heterojunction field effect transistor (FIG. 13) thus obtained, the carrier concentration of the channel layer 3 facing the region S1 (see FIGS. 2 to 4) where the insulating layer 8 is formed has an impurity supply layer 9s. , 9d are lower than the carrier concentration of the channel layer 3 facing the regions S2s, S2d (see FIGS. 2 to 4). Therefore, a high output can be obtained from the heterojunction field effect transistor.

  In general, SiN processing technology is highly established as compared with an insulating material containing Al, and it is easy to pattern with good controllability. Therefore, the manufacturing yield can be improved by forming the impurity supply layers 9 s and 9 d before the insulating layer 8.

Embodiment 4 FIG.
14 to 17 are cross-sectional views illustrating the structure of the heterojunction field effect transistor according to the fourth embodiment. These structures all have a common feature added to the heterojunction field effect transistor shown in the first embodiment. The feature is that the gate electrode 7 has a ridge 7 a extending toward at least the drain electrode 6 on the side far from the barrier layer 4.

  In both the configurations shown in FIGS. 14 and 16, the end of the ridge 7 a on the drain electrode 6 side is located on the insulating layer 8. In the configurations shown in FIGS. 15 and 17, the end of the ridge 7 a on the drain electrode 6 side is located on the impurity supply layer 9 d.

  In the configurations shown in FIGS. 14 and 15, the collar 7 a is not provided on the source electrode 5 side. In both the configurations shown in FIGS. 16 and 17, the flange 7 a is also provided on the source electrode 5 side.

  Of course, since the source electrode 5, the drain electrode 6, and the gate electrode 7 are not electrically connected to each other by the structure itself, the ridge 7a does not reach the source electrode 5 and the drain electrode 6.

  The saddle 7a shares the strength of the gate electric field and contributes to reducing the maximum electric field strength.

  FIG. 23 is a graph showing the lateral dependency of the intensity E of the gate electric field. In the graph, for easy understanding, the main part of the structure of the heterojunction field effect transistor is shown in correspondence with the graph in the horizontal direction.

  The intensity E when there is a ridge 7a is indicated by a curve E2. For comparison, the strength E when the ridge 7a is not provided is shown as a curve E1.

  From the curve E1, it can be seen that when the ridge 7a is not provided, the strength of the gate electric field concentrates on the end of the gate electrode 7 on the drain electrode 6 side. On the other hand, from the curve E2, when the ridge 7a is provided, the maximum strength of the strength E of the gate electric field is reduced.

  By such an action of the ridge 7a, the breakdown voltage of the heterojunction field effect transistor can be improved.

  When the strength E of the gate electric field increases, electrons are trapped by trap levels existing near the surface of the barrier layer 4. This constricts the current and causes a current drop phenomenon called current collapse. Therefore, the reduction of the maximum intensity of the intensity E of the gate electric field also brings about an effect of suppressing current collapse.

  As the lateral length of the ridge 7a is longer and closer to the barrier layer 4, the gate electric field can be dispersed and the maximum electric field strength can be reduced. In order to dispose the ridge 7a close to the barrier layer 4, the insulating layer 8 and the impurity supply layers 9s and 9d are thinned.

  However, as the lateral length of the ridge 7a is longer and closer to the barrier layer 4, the capacitance parasitic on the gate electrode 7 increases. This is undesirable because it degrades the high frequency response of the heterojunction field effect transistor.

  Thus, with respect to the size of the ridge 7a, the breakdown voltage and the high frequency response are in a trade-off relationship. Therefore, it is desirable to set the lateral length of the flange 7a and the thicknesses of the insulating layer 8 and the impurity supply layers 9s and 9d in accordance with desired device characteristics.

  Now, a method of manufacturing a heterojunction field effect transistor in the case where the gate electrode 7 has the ridge 7a can be exemplified as follows.

  First, the first to third steps described in the second embodiment are adopted, and the source electrode 5 and the drain electrode 6 are formed on the barrier layer 4 (see FIG. 7). Thereafter, the insulating layer 8 is formed on the barrier layer 4.

  Next, the insulating layers 8 in the regions S2s and S2d for forming the impurity supply layers 9s and 9d and the region Sg (see FIGS. 2 to 4) for forming the gate electrode 7 are removed by etching. Thereby, the barrier layer 4 is exposed in the regions S2s, S2d, and Sg. The material for the impurity supply layers 9s and 9d is once formed in the structure thus obtained, and is selectively removed by etching to expose the barrier layer 4 in the region Sg. Through the steps up to here, a configuration in which the gate electrode 7 is omitted from FIGS. 14 to 17 can be obtained.

  Thereafter, the material shown in FIGS. 14 to 17 can be obtained by once forming the material of the gate electrode 7 and selectively removing it by etching.

  In the configuration shown in FIG. 14, since the gate electrode 7 is not provided on the impurity supply layers 9s and 9d, the impurity supply layers 9s and 9d may be formed prior to the formation of the gate electrode 7. Good.

Embodiment 5 FIG.
18 to 21 are cross-sectional views illustrating the structure of the heterojunction field effect transistor according to the fifth embodiment. These structures all have a common feature added to the heterojunction field effect transistor shown in the first embodiment.

  The feature is that the gate electrode 7 and the first main surface 40 of the barrier layer 4 are insulated. Such a feature brings about an advantage that the gate leakage current can be reduced.

  Hereinafter, as an example for realizing such a feature, an MIS (Metal-Insulator-Semiconductor) structure in which an insulating film is interposed between the barrier layer 4 and the gate electrode 7 will be described.

  The insulating film interposed between the barrier layer 4 and the gate electrode 7 may be used also as a part of the insulating layer 8 (see FIG. 18) or as a part of the impurity supply layer 9s (see FIG. 19). ), Both the insulating layer 8 and the impurity supply layer 9s may be used (FIG. 20).

  Alternatively, the impurity supply layer 9s immediately below the gate electrode 7 may be replaced with the insulating layer 12 (FIG. 21). Examples of the material of the insulating layer 12 include oxides, nitrides, and oxynitrides of Si, Al, Zr, Hf, and Mg.

  The production method for obtaining these configurations is exemplified below. First, the first to third steps described in the second embodiment are adopted, and the source electrode 5 and the drain electrode 6 are formed on the barrier layer 4 (see FIG. 7). Thereafter, an insulating layer 8 and impurity supply layers 9s and 9d (further, the insulating layer 12 in the configuration of FIG. 21) are formed on the barrier layer 4 with patterning. Subsequently, the gate electrode 7 is formed.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5 source electrode, 6 drain electrode, 7 gate electrode, 8 insulating layer, 9s, 9d impurity supply layer, 11 resist layer, 40 1st main surface, 41 1st 2 main faces.

Claims (12)

A first semiconductor layer having a first band gap;
An electrode group having a source electrode, a drain electrode, and a gate electrode sandwiched between the source electrode and the drain electrode, and arranged on the first main surface side of the first semiconductor layer;
A second semiconductor layer provided in contact with a second main surface opposite to the first main surface of the first semiconductor layer and having a second band gap narrower than the first band gap; and the drain electrode; A heterojunction field-effect transistor comprising a first impurity supply layer that is provided in contact with the first main surface, is isolated from the gate electrode, and includes an impurity for the first semiconductor layer . 2. The heterojunction field effect according to claim 1, further comprising a second impurity supply layer provided in contact with the first main surface between the source electrode and the gate electrode and including an impurity for the first semiconductor layer. Type transistor. The first semiconductor layer is composed of a III-V compound semiconductor,
The heterojunction field effect transistor according to claim 1, wherein the impurity of the first semiconductor layer is a group IV element.   4. The heterojunction field-effect transistor according to claim 1, wherein the gate electrode has a ridge extending toward at least the drain electrode on a side far from the first semiconductor layer. 5.   The heterojunction field effect transistor according to claim 1, wherein the gate electrode and the first main surface are insulated. (A) forming a first semiconductor layer having a first band gap and a second semiconductor layer having a second band gap narrower than the first band gap;
(B) forming a source electrode and a drain electrode on the first semiconductor layer;
Forming a gate electrode sandwiched between the source electrode and the drain electrode on the first semiconductor layer;
(C) forming a first impurity supply layer that is provided between and in contact with the first semiconductor layer between the drain electrode and the gate electrode, and is in contact with the first semiconductor layer; And a process of
A method for manufacturing a heterojunction field effect transistor. The hetero of claim 6, further comprising a second impurity supply layer provided in contact with the first semiconductor layer between the source electrode and the gate electrode and including an impurity for the first semiconductor layer. A method of manufacturing a junction field effect transistor. The steps (c) and (d) are performed in parallel,
(E) Performed prior to the steps (c) and (d), between the drain electrode and the gate electrode, in the direction in which the source electrode, the drain electrode, and the gate electrode are aligned, Further comprising a step of forming an insulating layer in contact with and isolated from the drain electrode;
8. The method of manufacturing a heterojunction field effect transistor according to claim 7, wherein the insulating layer is an oxide, nitride, or oxynitride of Al. In the step (e),
(E1) forming an insulating layer on the first semiconductor layer after the step (b);
(E2) A resist layer is provided by patterning at a position that covers the region and the end of the gate electrode adjacent to the region and does not cover the end of the gate electrode on the source electrode side,
(E3) patterning the insulating layer by employing etching using the source electrode, the drain electrode, the gate electrode, and the resist layer as a mask;
A method for manufacturing a heterojunction field effect transistor according to claim 8. The steps (c) and (d) are performed in parallel,
(E) Performed after the steps (c) and (d), between the drain electrode and the gate electrode, in the direction in which the source electrode, the drain electrode, and the gate electrode are aligned, Further comprising the step of forming an insulating layer in contact with and isolated from the drain electrode;
8. The manufacture of a heterojunction field effect transistor according to claim 7, wherein the first impurity supply layer and the second impurity supply layer are both made of SiN and etching is employed in the steps (c) and (d). Method.   The method of manufacturing a heterojunction field effect transistor according to claim 9, wherein wet etching is employed for etching the insulating layer.   The method of manufacturing a heterojunction field effect transistor according to claim 10, wherein wet etching is employed for etching the first impurity supply layer and the second impurity supply layer.

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