JP5504660B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In recent years, development of electronic devices (compound semiconductor devices) in which a GaN layer and an AlGaN layer are sequentially formed on a substrate made of sapphire, SiC, GaN, Si, or the like and the GaN layer is used as an electron transit layer has been active. The band gap of GaN is 3.4 eV, which is larger than 1.4 eV of GaAs. For this reason, this compound semiconductor device is expected to operate at a high breakdown voltage.

  Examples of such a compound semiconductor device include a high electron mobility transistor (HEMT) suitable for a high-frequency amplifier, and a GaN-based HEMT suitable for a power device such as an inverter switch. The GaN-based HEMT has a horizontal structure in which a source electrode and a drain electrode are arranged in parallel with the surface of the substrate, and a vertical structure in which the source electrode and the drain electrode are arranged with the substrate interposed therebetween. Can be mentioned. The vertical structure can reduce the chip area and the cost as compared with the horizontal structure.

  FIG. 1 is a cross-sectional view showing a conventional GaN-based HEMT having a vertical structure. In a conventional GaN-based HEMT having a vertical structure, a drain electrode 121 d is formed on the back surface of an n-type n-GaN substrate 101. An n-type n-GaN layer 102 is formed on the n-GaN substrate 101 as a vertical electron transit layer. In the n-GaN layer 102, an AlN layer 103 is provided as a current confinement layer that limits a portion through which a current flows. On the n-GaN layer 102, an n-type n-AlGaN layer 106 is formed as a lateral current supply layer. On the n-AlGaN layer 106, a source electrode 121s is formed above the AlN layer 103, and a gate electrode 121g is formed above the opening of the AlN layer 103. A SiN film 114 is formed between the source electrode 121s and the gate electrode 121g.

  In the conventional vertical GaN-based HEMT configured as described above, a two-dimensional electron gas layer (2DEG) is generated in the surface layer portion of the n-GaN layer 102, and the source electrode 121s and the drain electrode 121d are connected via the 2DEG. Current flows between the two.

  However, the conventional vertical GaN-based HEMT has a problem that the on-resistance is high and the loss of electric energy due to heat generation at the time of on-state is large.

JP 2006-165207 A

  An object of the present invention is to provide a compound semiconductor device capable of reducing the on-resistance in a HEMT having a vertical structure and a method for manufacturing the same.

One aspect of the compound semiconductor device includes a substrate, an electron supply layer and an electron transit layer formed above the substrate, a source electrode and a gate electrode formed above the electron supply layer and the electron transit layer, and And a drain electrode formed on the back surface of the substrate. At least a part of the electron supply layer and at least a part of the electron transit layer are in contact with each other with a plane inclined from a plane parallel to the surface of the substrate as a boundary. A hole is formed in the electron transit layer, and the gate electrode enters the hole.

In one aspect of the method for manufacturing a compound semiconductor device, the electron supply layer and the electron transit layer are disposed above the substrate, and at least a part of the electron supply layer and at least a portion of the electron transit layer are on the surface of the substrate. Formed so as to be in contact with each other with a plane inclined from a parallel plane as a boundary, a hole is formed in the electron transit layer, and a source electrode and a gate electrode are formed above the electron supply layer and the electron transit layer. A drain electrode is formed on the back surface of the substrate. The gate electrode is formed so as to enter the hole.

  According to the above compound semiconductor device or the like, 2DEG is generated even in a plane inclined from a plane parallel to the surface of the substrate, so that the on-resistance in the direction perpendicular to the surface of the substrate can be reduced.

It is sectional drawing which shows the conventional GaN-type HEMT of a vertical structure. 1 is a cross-sectional view showing a structure of a GaN-based HEMT (compound semiconductor device) according to a first embodiment. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 1st Embodiment following FIG. 3A. FIG. 3B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3B. 3C is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3C. FIG. 3D is a cross-sectional view showing a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3D. FIG. 3E is a cross-sectional view showing a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3E. FIG. 3F is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3F. FIG. 3G is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3G. FIG. 3H is a cross-sectional view showing a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3H. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3I. FIG. 3J is a cross-sectional view showing a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3J. FIG. 3K is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3K. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3L. FIG. 3C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3M. FIG. 3D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 3N. It is sectional drawing which shows the structure of GaN-type HEMT (compound semiconductor device) which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT (compound semiconductor device) which concerns on 3rd Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT (compound semiconductor device) which concerns on 4th Embodiment. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 4th Embodiment. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment following FIG. 7A. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 7B.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 2 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the first embodiment.

In the first embodiment, an undoped i-GaN layer 2 and an n-type n-AlGaN layer 4 having a thickness of about 0.2 μm to 10 μm (for example, 1 μm) are laterally placed on an n-type n-GaN substrate 1. Alternatingly arranged in the direction. The i-GaN layer 2 functions as a vertical electron transit layer, and the n-AlGaN layer 4 functions as a vertical electron supply layer and an electron block layer. The direction perpendicular to the surface of the n-GaN substrate 1 is inclined from the c-axis direction of the GaN crystal. The surface of the n-GaN substrate 1 is, for example, an a-plane, m-plane or r-plane. The composition of the n-AlGaN layer 4 is represented by, for example, Al _0.25 Ga _0.75 N. Further, the n-AlGaN layer 4 is doped with, for example, Si of about 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ (for example, 4 × 10 ¹⁸ cm ⁻³ ). The electron affinity of the n-AlGaN layer 4 is smaller than that of the i-GaN layer 2.

On the i-GaN layer 2 and the n-AlGaN layer 4, a non-doped i-GaN layer 5 having a thickness of about 0.01 μm to 1 μm (for example, 0.1 μm) is formed as a lateral electron transit layer. On the i-GaN layer 5, an n-type n-AlGaN layer 6 having a thickness of about 5 nm to 30 nm (for example, 10 nm) is formed as a lateral electron supply layer. The composition of the n-AlGaN layer 6 is represented by, for example, Al _0.25 Ga _0.75 N. The n-AlGaN layer 6 is doped with, for example, Si of about 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ (for example, 4 × 10 ¹⁸ cm ⁻³ ). The electron affinity of the n-AlGaN layer 6 is smaller than the electron affinity of the i-GaN layer 5. An n-type n-GaN layer 7 having a thickness of about 2 nm to 10 nm (for example, 7 nm) is formed on the n-AlGaN layer 6 as a protective layer. The n-GaN layer 7 is doped with, for example, Si of about 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ (for example, 5 × 10 ¹⁸ cm ⁻³ ). For example, the band gap of the i-GaN layer 5 and the i-GaN layer 2 is narrower than the band gap of the n-AlGaN layer 4, and the band gap of the n-AlGaN layer 6 is the band gap of the i-GaN layer 5. Wider than.

  A source electrode opening 7a is formed in a portion of the n-GaN layer 7 located above the n-AlGaN layer 4, and a source electrode 21s extending above the opening 7a is formed in the opening 7a. Is formed. Further, the n-AlGaN layer 6, the i-GaN layer 5, and the n-AlGaN layer 4 have an element isolation region 11 that extends from the interface with the source electrode 21 s of the n-AlGaN layer 6 to an intermediate depth of the n-AlGaN layer 4. Is formed.

  On the n-GaN layer 7, a SiN film (silicon nitride film) 14 is formed to cover the source electrode 21s. The thickness of the SiN film 14 is about 10 nm to 100 nm (for example, 40 nm).

  In the SiN film 14, the n-GaN layer 7, the n-AlGaN layer 6, the i-GaN layer 5, and the i-GaN layer 2, a hole 16 extending from the surface of the SiN film 14 to a midway depth of the i-GaN layer 2 is formed. Has been. A gate electrode 21 g extending above the hole 16 is formed in the hole 16.

  On the SiN film 14, an SiN film 17 covering the gate electrode 21g is formed. The thickness of the SiN film 17 is about 20 nm to 1000 nm (for example, 400 nm). The SiN film 17 and the SiN film 14 are formed with an opening 17s exposing a part of the source electrode 21s, and the SiN film 17 is formed with an opening 17g exposing a part of the gate electrode 21g.

  A drain electrode 21 d is formed on the entire back surface of the n-GaN substrate 1.

  In the first embodiment, electrons are induced in the vicinity of the interface between the i-GaN layer 5 and the n-AlGaN layer 6 due to the piezo effect caused by lattice mismatch. As a result, a two-dimensional electron gas layer (2DEG) spreading in the lateral direction (direction parallel to the surface of the n-GaN substrate 1) appears. In addition, electrons are also induced in the vicinity of the interface between the i-GaN layer 2 and the n-AlGaN layer 4 due to a similar piezo effect. As a result, 2DEG spreading in the vertical direction (direction perpendicular to the surface of the n-GaN substrate 1) appears. The 2DEG spreading in the vertical direction is in contact with the n-GaN substrate 1 while being inclined (orthogonal) from the surface thereof.

In the conventional vertical GaN-based HEMT, the n-type GaN layer functions as an electron supply layer in the vertical direction, so the electron mobility is as low as about 100 cm ² / V · s, and the on-resistance is high. ing. On the other hand, in the present embodiment, since 2DEG spreading in the vertical direction exists, the electron mobility can be improved.

  Further, since the gate electrode 21g is also present on the side of the interface between the i-GaN layer 2 and the n-AlGaN layer 4, the vicinity of the interface between the i-GaN layer 2 and the n-AlGaN layer 4 is turned off. Even so, 2DEG hardly exists on the side of the gate electrode 21g. For this reason, the drain leakage current at the time of OFF is suppressed.

  Actually, when the inventors of the present application verified by simulation, the results shown in Table 1 below were obtained. In this verification, a simulation of the conventional GaN-based HEMT shown in FIG. 1 was also performed for comparison. In the simulation of the switching time, the response time was verified when the gate electrode voltage was controlled and changed from OFF to ON in a state where the total gate width was 40 mm and 100 V was applied to the drain electrode.

According to the first embodiment, an electron mobility of about 1000 cm ² / V · s (10 times that of the prior art) can be obtained, so that the on-resistance can be significantly reduced as shown in Table 1. In addition, the switching time can be shortened. By shortening the switching time, it is possible to improve the operation efficiency when used in a switching circuit, and it is possible to reduce the size of peripheral circuits such as coils.

  In controlling the operation of the first embodiment, for example, the source electrode 21s is grounded. When off, 300 V is applied to the drain electrode 21d, and 0 V or a negative voltage is applied to the gate electrode 21g. On the other hand, a positive voltage is applied to the gate electrode 21g and the drain electrode 21d when turned on.

  Note that a resistor, a capacitor, and the like may be mounted to form a monolithic microwave integrated circuit (MMIC). The same applies to the second to fourth embodiments described later.

  Next, a method for manufacturing a GaN-based HEMT (compound semiconductor device) according to the first embodiment will be described. 3A to 3O are cross-sectional views showing a method of manufacturing a GaN-based HEMT (compound semiconductor device) according to the first embodiment in the order of steps.

  In the first embodiment, first, as shown in FIG. 3A, an i-GaN layer 2 is formed on an n-GaN substrate 1 by, for example, a metal organic vapor phase epitaxy (MOVPE) method. For example, trimethyl gallium is used as the Ga material and ammonia is used as the N material. The pressure is 100 Torr and the growth temperature is 1050 ° C.

Next, as shown in FIG. 3B, the SiO ₂ film 3 is formed on the i-GaN layer 2 by, for example, a thermal chemical vapor deposition (CVD) method. Thereafter, a resist film is formed on the SiO ₂ film 3, and the resist film is exposed and developed to form a resist pattern 51 having an opening 51 a that opens a portion corresponding to the n-AlGaN layer 4.

Subsequently, as shown in FIG. 3C, the n-GaN substrate 1 is exposed by performing wet etching of the SiO ₂ film 3 and dry etching of the i-GaN layer 2 using the resist pattern 51 as a mask. As this dry etching, for example, dry etching using a chlorine-based gas is performed. Then, the resist pattern 51 is removed.

Next, as shown in FIG. 3D, the n-AlGaN layer 4 is formed in the opening of the i-GaN layer 2 by, for example, the MOVPE method until it has the same height as the i-GaN layer 2. At this time, the SiO ₂ film 3 functions as a mask for suppressing the growth of the n-AlGaN layer 4 on the i-GaN layer 2. For example, trimethylgallium is used as the Ga material, ammonia is used as the N material, and trimethylaluminum is used as the Al material. Then, the SiO ₂ film 3 is removed.

  Thereafter, as shown in FIG. 3E, an i-GaN layer 5, an n-AlGaN layer 6, and an n-GaN layer 7 are formed in this order on the i-GaN layer 2 and the n-AlGaN layer 4. In this case, these layers can be formed continuously by selecting a source gas. As a raw material of Si contained as an impurity in the n-AlGaN layer 6 and the n-GaN layer 7, for example, silane can be used.

  Subsequently, a resist film is formed on the n-GaN layer 7, and a resist pattern for element isolation formation is formed by exposing and developing the resist film, and Ar is ion-implanted using the resist pattern as a mask. To do. As a result, the element isolation region 11 is formed as shown in FIG. 3F. Then, the resist pattern is removed.

  Next, a new resist film is formed on the n-GaN layer 7, and a resist pattern for forming a source electrode is formed by exposing and developing the resist film. Using this resist pattern as a mask, n-GaN Layer 7 is dry etched. As this dry etching, for example, dry etching using a chlorine-based gas is performed. As a result, an opening 7a is formed as shown in FIG. 3G. In addition, regarding the depth of the opening 7a, a part of the n-GaN layer 7 may be left, or a part of the n-AlGaN layer 6 may be removed. That is, the depth of the opening 7 a does not need to match the thickness of the n-GaN layer 7. Then, the resist pattern is removed.

  Thereafter, as shown in FIG. 3H, a Ta film 21a, an Al film 21b, and a Ta film 21c are formed in this order in the opening 7a by a lift-off method. That is, a new resist pattern is formed, Ta, Al, and Ta are vapor-deposited, and then Ta, Al, and Ta adhering to the resist pattern are removed together with the resist pattern. The thicknesses of the Ta film, Al film, and Ta film are, for example, about 10 nm, about 280 nm, and about 10 nm from the bottom.

Subsequently, heat treatment is performed at 400 ° C. to 1000 ° C., for example, 550 ° C. for 1 minute under a nitrogen atmosphere using a rapid thermal annealing (RTA) apparatus. By this heat treatment, TaAl ₃ is generated at the interface between the Ta film 21a and the Al film 21b and at the interface between the Al film 21b and the Ta film 21c, and the source electrode 21s is formed as shown in FIG. 3I. Also, as a result of this heat treatment, ohmic characteristics are established.

  Next, as shown in FIG. 3J, a SiN film 14 is formed on the entire surface by plasma enhanced chemical vapor deposition (PE-CVD). Thereafter, a resist film is formed on the SiN film 14, and this resist film is exposed and developed to form a resist pattern 15 having an opening 15a for forming a gate electrode.

  Subsequently, as shown in FIG. 3K, the SiN film 14 is dry-etched using the resist pattern 15 as a mask. As this dry etching, for example, dry etching using a chlorine-based gas is performed.

  Further, as shown in FIG. 3L, the n-GaN layer 7, the n-AlGaN layer 6, the i-GaN layer 5, and the i-GaN layer 2 are dry-etched using the resist pattern 15 as a mask. As this dry etching, for example, dry etching using a chlorine-based gas is performed. Further, the amount of this dry etching is, for example, about 0.15 μm in depth. As a result, a hole 16 extending to a midway depth of the i-GaN layer 2 is formed.

  Next, as shown in FIG. 3M, the resist pattern 15 is removed. Thereafter, a gate electrode 21g is formed in the hole 16 by a lift-off method. In the formation of the gate electrode 21g, a resist pattern that opens a region for forming the gate electrode 21g, for example, a two-layer resist pattern is formed, Ni and Au are deposited, and then the Ni and Au attached on the resist pattern are resisted. Remove the entire pattern. The thicknesses of the Ni film and the Au film are, for example, about 10 nm and about 200 nm, respectively.

  Subsequently, as shown in FIG. 3N, a SiN film 17 is formed on the entire surface by, eg, plasma CVD. Next, an opening 17 s exposing a part of the source electrode 21 s is formed in the SiN film 17 and the SiN film 14, and an opening 17 g exposing a part of the gate electrode 21 g is formed in the SiN film 17.

  Thereafter, as shown in FIG. 3O, the back surface of the n-GaN substrate 1 is polished so that the thickness of the n-GaN substrate 1 is about 100 μm. At this time, all of the n-GaN substrate 1 may be removed. This is because the on-resistance increases when electrons run on the n-GaN substrate 1. Subsequently, a drain electrode 21 d is formed on the back surface of the n-GaN substrate 1. In the formation of the drain electrode 21d, a Ta film, an Al film, and a Ta film are formed in this order on the back surface of the n-GaN substrate 1. Also, these thicknesses are, for example, about 10 nm, about 280 nm, and about 10 nm in order from the n-GaN substrate 1 side. Subsequently, heat treatment is performed for 1 minute at 400 ° C. to 1000 ° C., for example, 550 ° C. under a nitrogen atmosphere using an RTA apparatus. By this heat treatment, the drain electrode 21d is formed. Also, as a result of this heat treatment, ohmic characteristics are established.

  With such a manufacturing method, a GaN-based HEMT having the structure shown in FIG. 2 can be obtained.

  Note that the gate length of the gate electrode 21g, that is, the length in the direction connecting the two source electrodes 21s is about 0.2 μm to 2 μm (for example, 0.5 μm). The unit gate width, that is, the width of the region in which the concentration of 2DEG is controlled by the gate electrode 21g is about 100 μm to 4000 μm (for example, 300 μm).

(Second Embodiment)
Next, a second embodiment will be described. FIG. 4 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the second embodiment.

In the second embodiment, a Ta ₂ O ₅ film (tantalum oxide film) 18 is formed along the inner surface of the hole 16. The thickness of the Ta ₂ O ₅ film 18 is about 2 nm to 40 nm (for example, 10 nm). The Ta ₂ O ₅ film 18 is further interposed between the SiN film 14 and the SiN film 17.

  That is, the gate of the first embodiment has a Schottky gate structure, whereas the gate of the second embodiment has an insulated gate structure. Other configurations are the same as those of the first embodiment.

  The effect similar to 1st Embodiment can be acquired also by such 2nd Embodiment. Further, since the insulated gate structure is adopted, there is no gate leakage in the forward direction. Therefore, the gate voltage can be set to 5 V or more, the maximum current can be increased, and the power device is more suitable.

  Actually, when the inventors of the present application verified by the same simulation as in the first embodiment, the results shown in Table 2 below were obtained.

  As shown in Table 2, the maximum current can be increased by 30% or more compared to the first embodiment. In addition, the switching time can be further shortened.

When manufacturing the GaN-based HEMT according to the second embodiment, after the formation of the holes 16 in the first embodiment, the Ta ₂ O ₅ film 18 is formed by 300 atomic layer deposition (ALD), for example. What is necessary is just to form at about degreeC. Then, after forming the Ta ₂ O ₅ film 18, annealing is performed at about 600 ° C. for 1 minute, whereby internal hydrogen is desorbed, the internal electron trap density is reduced, and the quality of the Ta ₂ O ₅ film 18 is improved. To do.

The material of the insulating film used for the insulating gate structure is not particularly limited, but the dielectric constant is preferably 10 or more, for example, and HfO ₂ insulating film, Al ₂ O ₃ insulating film, etc. have good performance. Indicates. Also, an HfON film can be used as the oxynitride film. In this case, the film may be formed by the ALD method using NH ₃ or N ₂ plasma as the N source.

(Third embodiment)
Next, a third embodiment will be described. FIG. 5 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the third embodiment.

  In the third embodiment, an n-AlGaN layer 31 in which the concentrations of Al and Ga change in the depth direction is provided instead of the n-AlGaN layer 4 in the second embodiment. In the n-AlGaN layer 31, the closer to the n-GaN substrate 1, the higher the Al concentration and the lower the Ga concentration. For example, near the interface between the n-AlGaN layer 31 and the n-GaN substrate 1, the Al concentration and the Ga concentration are 50%, and near the interface with the i-GaN layer 5, the Al concentration is 5% and the Ga concentration is 50%. 95%. Here, the Al concentration and the Ga concentration are the ratios of Al and Ga to the total amount of Al and Ga.

  Other configurations are the same as those of the second embodiment.

  The effect similar to 2nd Embodiment is acquired also by such 3rd Embodiment. Further, the Al concentration in the vicinity of the interface between the n-AlGaN layer 31 and the i-GaN layer 5 is low, and there is almost no 2DEG at the interface between the i-GaN layer 2 and the low Al concentration portion. For this reason, normally-off operation becomes more reliable and the threshold voltage can be increased.

  Actually, when the inventors of the present application verified by the same simulation as in the first embodiment, the results shown in Table 3 below were obtained.

  As shown in Table 3, a threshold voltage of + 2V is obtained. In addition, the switching time can be further shortened.

  When manufacturing the GaN-based HEMT according to the third embodiment, instead of forming the n-AlGaN layer 4 in the second embodiment, the Al concentration is reduced while adjusting the flow rate of the source gas. The n-AlGaN layer 31 may be formed while increasing the Ge concentration.

  Note that the same Schottky gate structure as in the first embodiment may be adopted.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 6 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) according to the fourth embodiment.

  In the fourth embodiment, i-GaN layers 2 and n-AlGaN layers 4 are alternately arranged in the lateral direction on an n-type n-GaN substrate 1 as in the first embodiment. In the i-GaN layer 2, an element isolation region 11 extending from the interface to a midway depth is formed. A source electrode 21 s is formed on the i-GaN layer 2. On the i-GaN layer 2 and the n-AlGaN layer 4, a SiN film 14 covering the source electrode 21s is formed. In addition, the n-AlGaN layer 4 is formed with a hole 16 extending from its surface to a halfway depth. A gate electrode 21 g extending above the hole 16 is formed in the hole 16. Furthermore, an SiN film 17 is formed on the SiN film 14 so as to cover the gate electrode 21g. The SiN film 17 and the SiN film 14 are formed with an opening 17s exposing a part of the source electrode 21s, and the SiN film 17 is formed with an opening 17g exposing a part of the gate electrode 21g.

  A drain electrode 21 d is formed on the entire back surface of the n-GaN substrate 1.

  In the fourth embodiment, electrons are also induced in the vicinity of the interface between the i-GaN layer 2 and the n-AlGaN layer 4 due to the piezoelectric effect caused by lattice mismatch. As a result, 2DEG spreading in the vertical direction appears. On the other hand, unlike the first to third embodiments, 2DEG spreading in the lateral direction does not appear. That is, the current path is simplified. For this reason, the on-resistance is lower than in the first to third embodiments.

  Actually, when the inventors of the present application verified by the same simulation as in the first embodiment, the results shown in Table 4 below were obtained.

  As shown in Table 4, the on-resistance is extremely low and the maximum current is extremely high. In addition, the switching time can be further shortened.

  In the fourth embodiment, an insulated gate structure may be employed as in the second and third embodiments. Further, as in the third embodiment, an n-AlGaN layer 31 in which the concentrations of Al and Ga change may be used instead of the n-AlGaN layer 4.

  Next, a method for manufacturing a GaN-based HEMT (compound semiconductor device) according to the fourth embodiment will be described. 7A to 7C are cross-sectional views showing a method of manufacturing a GaN-based HEMT (compound semiconductor device) according to the fourth embodiment in the order of steps.

  In the fourth embodiment, first, as shown in FIG. 7A, an i-GaN layer 2 and an n-AlGaN layer 4 are formed on an n-GaN substrate 1 as in the first embodiment. Next, the element isolation region 11 is formed in the i-GaN layer 2.

  Thereafter, as illustrated in FIG. 7B, the source electrode 21 s is formed on the i-GaN layer 2 and the element isolation region 11.

  Subsequently, as shown in FIG. 7C, a SiN film 14 is formed. Next, an opening 14 a is formed above the n-AlGaN layer 4 of the SiN film 14, and a hole 16 is formed in the n-AlGaN layer 4. Then, a gate electrode 21 g is formed in the hole 16.

  Thereafter, the SiN film 17 is formed in the same manner as in the first embodiment.

  With such a manufacturing method, a GaN-based HEMT having the structure shown in FIG. 6 can be obtained.

  In any of the embodiments, the material, thickness, impurity concentration, and the like of the substrate and each layer are not particularly limited. For example, instead of the n-GaN substrate 1, a conductive silicon substrate, a sapphire substrate, a conductive SiC substrate, or the like may be used. However, it is assumed that at least a part of 2DEG generated in the vicinity of the interface between the electron transit layer and the electron supply layer can spread in a plane inclined from a plane parallel to the surface of the substrate. For example, the above-mentioned a-plane, m-plane or r-plane n-GaN substrate, and sapphire substrate may be mentioned. Therefore, if a part of the electron supply layer and a part of the electron transit layer are in contact with a plane inclined from a plane parallel to the surface of the substrate, this surface does not need to be perpendicular to the surface of the substrate, There is no need for 2DEG to extend perpendicular to the surface of the substrate. Moreover, the electroconductive silicon substrate whose surface Miller index is (100) or (110) is also mentioned. In the case of a sapphire substrate, for example, by removing all the sapphire substrate by polishing or the like and directly forming the drain electrode on the GaN crystal layer, the same effect as in the present embodiment can be obtained. When using another substrate, the entire substrate may be peeled off.

  In addition, other compound semiconductors may be used as materials such as an electron transit layer and an electron supply layer, but nitride semiconductors are particularly preferable. For example, an AlGaInN layer or an InAlN layer may be used instead of the n-AlGaN layer 6 functioning as a lateral electron supply layer and the n-AlGaN layer 4 functioning as a vertical electron supply layer and an electron block layer. In this case, the band gap of these layers can be adjusted by the composition ratio of In, and the HEMT threshold value can be changed. Further, the Al concentration may be changed as in the third embodiment.

  The structures of the gate electrode 21g, the source electrode 21s, and the drain electrode 21d are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Moreover, these formation methods are not limited to the lift-off method. Further, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode 21s and the drain electrode 21d may be omitted. Further, heat treatment may be performed on the gate electrode 21g.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A substrate,
An electron supply layer and an electron transit layer formed above the substrate;
A source electrode and a gate electrode formed above the electron supply layer and the electron transit layer;
A drain electrode formed on the back surface of the substrate;
Have
At least a part of the electron supply layer and at least a part of the electron transit layer are in contact with each other with a plane inclined from a plane parallel to the surface of the substrate as a boundary.

(Appendix 2)
2. The compound semiconductor device according to appendix 1, wherein the substrate is a conductive GaN substrate, conductive SiC or sapphire substrate having an m-plane, a-plane, or r-plane surface.

(Appendix 3)
The compound semiconductor device according to appendix 1, wherein the substrate is a conductive silicon substrate having a mirror index of (100) or (110) on the surface.

(Appendix 4)
A two-dimensional electron gas layer is present in a portion of the electron transit layer in contact with the electron supply layer;
4. The compound semiconductor device according to claim 1, wherein the two-dimensional electron gas layer is in contact with the substrate while being inclined from a plane parallel to the surface of the substrate.

(Appendix 5)
A first compound semiconductor layer formed above the electron supply layer and the electron transit layer, the band gap of which is the same as or narrower than the narrower one of the band gaps of the electron supply layer and the electron transit layer;
A second compound semiconductor layer formed on the first compound semiconductor layer, the band gap of which is wider than the band gap of the first compound semiconductor layer;
5. The compound semiconductor device according to any one of appendices 1 to 4, wherein:

(Appendix 6)
6. The compound semiconductor device according to any one of appendices 1 to 5, wherein the electron supply layer includes Al and N, and further includes at least one of Ga and In.

(Appendix 7)
The compound semiconductor device according to any one of appendices 1 to 6, wherein the gate electrode is embedded in the electron transit layer.

(Appendix 8)
An electron supply layer and an electron transit layer are provided above the substrate, with at least a part of the electron supply layer and at least a portion of the electron transit layer being inclined from a plane parallel to the surface of the substrate. Forming to contact each other;
Forming a source electrode and a gate electrode above the electron supply layer and the electron transit layer;
Forming a drain electrode on the back surface of the substrate;
A method for producing a compound semiconductor device, comprising:

(Appendix 9)
The method of manufacturing a compound semiconductor device according to appendix 8, wherein a conductive GaN substrate, conductive SiC or sapphire substrate having an m-plane, a-plane or r-plane surface is used as the substrate.

(Appendix 10)
9. The method of manufacturing a compound semiconductor device according to appendix 8, wherein a conductive silicon substrate having a surface mirror index of (100) or (110) is used as the substrate.

1: n-GaN substrate 2: i-GaN layer 4: n-AlGaN layer 5: i-GaN layer 6: n-AlGaN layer 7: n-GaN layer 18: Ta ₂ O ₅ film 21d: drain electrode 21g: gate Electrode 21s: Source electrode 31: n-AlGaN layer

Claims (5)

A substrate,
An electron supply layer and an electron transit layer formed above the substrate;
A source electrode and a gate electrode formed above the electron supply layer and the electron transit layer;
A drain electrode formed on the back surface of the substrate;
Have
At least a part of the electron supply layer and at least a part of the electron transit layer are in contact with each other with a plane inclined from a plane parallel to the surface of the substrate as a boundary ,
A hole is formed in the electron transit layer,
The compound semiconductor device, wherein the gate electrode enters the hole .   2. The compound semiconductor device according to claim 1, wherein the substrate is a conductive GaN substrate, a conductive SiC, or a sapphire substrate having an m-plane, a-plane, or r-plane surface.   2. The compound semiconductor device according to claim 1, wherein the substrate is a conductive silicon substrate having a mirror index (100) or (110) on the surface. A two-dimensional electron gas layer is present in a portion of the electron transit layer in contact with the electron supply layer;
4. The compound semiconductor device according to claim 1, wherein the two-dimensional electron gas layer is in contact with the substrate while being inclined from a plane parallel to the surface of the substrate. 5. An electron supply layer and an electron transit layer are provided above the substrate, with at least a part of the electron supply layer and at least a portion of the electron transit layer being inclined from a plane parallel to the surface of the substrate. Forming to contact each other;
Forming a hole in the electron transit layer;
Forming a source electrode and a gate electrode above the electron supply layer and the electron transit layer;
Forming a drain electrode on the back surface of the substrate;
I have a,
The method of manufacturing a compound semiconductor device, wherein the gate electrode is formed so as to enter the hole .

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