JP2011198837A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device which can suppress hysteresis caused by a charge trap while reducing an interface level, and to provide a method of manufacturing the same.SOLUTION: The semiconductor device 200 includes a substrate (a semiconductor substrate 100) having a semiconductor layer 101 containing GaN on at least a part of its surface, a first gate insulation layer (an AlOfilm 114) arranged on the semiconductor substrate 100 to be in contact with the semiconductor layer 101 and formed of an metal oxide layer containing no nitrogen but Al, a second gate insulation layer (an SiOfilm 116) arranged on the AlOfilm 114 and containing Si and O, and a gate electrode 118 arranged on the SiOfilm 116. A lower surface of the gate electrode 118 is in contact with the SiOfilm 116. A thickness of the AlOfilm 114 is smaller than that of the SiOfilm 116.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, wide band gap semiconductors typified by group III-V nitrides have high potential for use as power electronic devices because of their high breakdown voltage and high electron mobility. Among them, there is a field effect transistor (FET) that uses an aluminum gallium nitride / gallium nitride (AlGaN / GaN) laminated structure as a channel. This FET can form a two-dimensional electron gas having high electron mobility and carrier density by the piezoelectric effect of AlGaN.

As the FET, a MISFET has been proposed in addition to a Schottky FET. The Schottky FET has a structure in which a gate electrode is directly formed on the above laminated structure. On the other hand, the MISFET has a structure in which a gate electrode is formed on the laminated structure via a gate insulating film. This MISFET can suppress a leakage current to the gate, and can increase the threshold value of the FET to realize a normally-off operation. For example, in Patent Document 1, as a MISFET, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), or the like is used as a gate insulating film, and an AlGaN / GaN heterostructure and a gate are used. A structure in which an aluminum nitride (AlN) film is formed between the insulating film and the insulating film is described. In the technique described in this document, since the source electrode and the drain electrode are in contact only with the AlN film, the AlN film substantially functions as a semiconductor layer rather than a part of the gate insulating film. It is thought that SiO ₂ is used as

Patent Document 2 describes a structure in which an aluminum nitride (AlN) film is formed as an underlayer of a gate insulating film and an aluminum oxide (Al ₂ O ₃ ) film is formed as an upper layer of a gate insulating film as an MISFET. Yes. According to this document, AlN is a polycrystalline or amorphous insulator.

In Patent Document 3, as the MISFET, from the AlGaN side, a first gate insulating film made of a silicon nitride film (SiN) and a second gate insulating film made of a material having a higher dielectric breakdown strength than the SiN film are provided. A stacked structure is described. This document describes a silicon oxide film (SiO ₂ ) or an alumina film (Al ₂ O ₃ ) as the second gate insulating film.

  Patent Document 4 discloses a semiconductor in which a first insulating film and a second insulating film having an opening are stacked on a GaN substrate, and a gate electrode inside the opening is in direct contact with the first insulating film. An apparatus is described. In this document, even when an opening is formed in the second gate insulating film, the surface of the GaN substrate covered with the first insulating film is not exposed. It is described that defects can be suppressed.

JP 2000-252458 A JP 2006-32552 A JP 2008-103408 A JP 2009-59946 A

  According to the knowledge of the present inventor, in the MISFET type device having the GaN-based semiconductor layer described in the above document, depending on the material of the gate insulating film formed on the GaN-based semiconductor layer, (i) the GaN-based semiconductor layer It has been found that control of the threshold value may be difficult due to an increase in the interface state between them or (ii) trapping of charges in the gate insulating film.

That is, in the technique of Patent Document 1, since SiO ₂ in contact with the GaN-based semiconductor layer contains oxygen atoms in the film and Ga is more easily oxidized than Si, Ga and oxygen are combined on the semiconductor layer side. GaO is formed. This GaO increases the interface state of the semiconductor layer. In Al ₂ O ₃ , Al is more easily oxidized than Ga. Therefore, even if oxygen is contained in the film, a GaO bond is not easily formed. However, charges may be trapped in the Al ₂ O ₃ film. For this reason, when the charge is trapped during the operation of the element, the threshold value largely fluctuates.

Further, in Patent Document 1, Si ₃ N ₄ is used as a gate insulating film, and since this Si ₃ N ₄ does not contain oxygen, formation of GaO can be avoided. Similarly, in Patent Documents 2 and 3, nitride containing no oxygen is used as a gate insulating film on the interface side with the AlGaN semiconductor layer.

However, the use of a layer containing nitrogen for the gate insulating film has the following disadvantages. That is, according to the knowledge of the present inventor, the film containing nitrogen as described above has very many charge traps. Therefore, when a film containing nitrogen is used as the gate insulating film, it becomes difficult to suppress hysteresis due to charge trapping, and in addition, discontinuity at the interface with the upper oxide insulating film such as SiO ₂ or Al ₂ O _{3 is} difficult. Occurs, and defects at the interface are likely to occur. In addition, when SiN is used, the film stress varies greatly depending on the film forming conditions. For this reason, the variation in the characteristics of the GaN-based MISFET using the piezoelectric charge may increase.

According to the present invention,
A substrate having a semiconductor layer containing GaN on at least a part of its surface;
A first gate insulating layer which is provided on the substrate so as to be in contact with the semiconductor layer and which is made of a metal oxide layer not containing nitrogen and containing Al;
A second gate insulating layer provided on the first gate insulating layer and containing Si and O;
A gate electrode provided on the second gate insulating layer,
A lower surface of the gate electrode is in contact with the second gate insulating layer;
A semiconductor device is provided in which the film thickness of the first gate insulating layer is thinner than the film thickness of the second gate insulating layer.

Moreover, according to the present invention,
A substrate having a semiconductor layer containing GaN on at least a part of its surface;
A first gate insulating layer which is provided on the substrate so as to be in contact with the semiconductor layer and which includes a metal oxide layer which does not include nitrogen and includes a trivalent transition metal including Y (yttrium) or a lanthanoid;
A second gate insulating layer provided on the first gate insulating layer and containing Si and O;
A gate electrode provided on the second gate insulating layer,
A lower surface of the gate electrode is in contact with the second gate insulating layer;
A semiconductor device is provided in which the film thickness of the first gate insulating layer is thinner than the film thickness of the second gate insulating layer.

Moreover, according to the present invention,
Forming a substrate having a semiconductor layer containing GaN on at least a portion of the surface;
Forming a first gate insulating layer made of a metal oxide layer not containing nitrogen and containing Al on the substrate so as to be in contact with the semiconductor layer;
Forming a second gate insulating layer containing Si and O on the first gate insulating layer;
Forming a gate electrode on the second gate insulating layer,
The step of forming the gate electrode includes forming the lower surface of the gate electrode in contact with the second gate insulating layer,
The step of forming the first gate insulating layer provides a method for manufacturing a semiconductor device, wherein the first gate insulating layer is formed so that the thickness of the first gate insulating layer is thinner than the thickness of the second gate insulating layer. Is done.

Moreover, according to the present invention,
Forming a substrate having a semiconductor layer containing GaN on at least a portion of the surface;
Forming a first gate insulating layer made of a metal oxide layer containing a trivalent transition metal made of Y (yttrium) or lanthanoid on the substrate so as to be in contact with the semiconductor layer;
Forming a second gate insulating layer containing Si and O on the first gate insulating layer;
Forming a gate electrode on the second gate insulating layer,
The step of forming the gate electrode includes forming the lower surface of the gate electrode in contact with the second gate insulating layer,
The step of forming the first gate insulating layer provides a method for manufacturing a semiconductor device, wherein the first gate insulating layer is formed so that the thickness of the first gate insulating layer is thinner than the thickness of the second gate insulating layer. Is done.

In the present invention, the first gate insulating layer is used as the interface layer in contact with the semiconductor layer containing GaN. The first gate insulating layer is made of a metal oxide layer containing a trivalent transition metal made of Al, Y (yttrium), or lanthanoid, which is more easily oxidized than Ga. For this reason, the oxidation of Ga in the semiconductor layer can be avoided. Thereby, the interface state produced between the interface layer and the semiconductor layer can be reduced.
On the other hand, the second insulating layer is made of a material containing Si and O. For this reason, the amount of charge traps generated is small in the second insulating layer. In addition, the thickness of the first gate insulating layer is made thinner than that of the second gate insulating layer. For this reason, compared with the case where the film thickness of the 1st gate insulating layer is the same as the film thickness of the 2nd gate insulating layer, the amount of electric charge traps generated in the 1st gate insulating layer decreases. For this reason, since the amount of charge traps in the entire insulating layer is reduced, hysteresis due to charge traps can be suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the structure of the semiconductor device which can suppress the hysteresis resulting from a charge trap, and its manufacturing method are provided, reducing an interface state.

It is sectional drawing which shows typically the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 schematically shows a cross-sectional view of a semiconductor device 200 of the present embodiment.
A semiconductor device 200 according to the present embodiment is provided on a semiconductor substrate 100 so as to be in contact with the substrate (semiconductor substrate 100) having a semiconductor layer 101 containing GaN in at least a part of its surface, and nitrogen. A first gate insulating layer (Al ₂ O ₃ film 114) made of a metal oxide layer containing Al and a second gate containing Si and O provided on the Al ₂ O ₃ film 114 An insulating layer (SiO ₂ film 116) and a gate electrode 118 provided on the SiO ₂ film 116 are provided. The lower surface of the gate electrode 118 is in contact with the SiO ₂ film 116, and the Al ₂ O ₃ film 114 The film thickness is smaller than the film thickness of the SiO ₂ film 116.
The semiconductor device 200 is a GaN-based MISFET semiconductor device (GaN-based MIS transistor) that uses a semiconductor laminated structure containing GaN as a main component for a channel and has a gate insulating layer thereon.

The configuration of the gate insulating layer of this embodiment is based on the inventors' new knowledge as follows.
The inventor conducted a detailed investigation on using the Al ₂ O ₃ film as a lower gate insulating film and using the SiO ₂ film as an upper gate insulating film. As a result, although (i) the Al ₂ O ₃ film has a small interface state generated at the interface with the GaN-based semiconductor layer, hysteresis may occur due to trapping of charges in the film, (ii) It was newly found that the SiO ₂ film has a large interface state generated at the interface with the GaN-based semiconductor layer, but has a small number of charge traps in the film. Then, by using an Al ₂ O ₃ film as an interface layer with the GaN-based semiconductor layer, generation of interface states is suppressed, and an SiO ₂ film with few traps is formed thereon, and Al ₂ O ₃ We have devised a new structure that reduces hysteresis by reducing the film thickness. Since this gate insulating layer does not use nitride, the harmful effects of nitrogen in the gate insulating layer can be removed. Here, the fact that the gate insulating layer does not contain a nitrogen component allows a nitrogen component inevitably mixed into the gate insulating layer during the manufacturing process.

  As described above, in the semiconductor device of this embodiment, the gate insulating layer on the stacked structure of the semiconductor containing GaN as a main component has a structure with few interface states and little trapping of charges in the film. As a result, fluctuations in the threshold can be suppressed.

First, Al ₂ O ₃ contains Al having a high affinity for oxygen, so that oxidation of Ga is suppressed, Al is composed of the same group III element as Ga (semiconductor), and has a close electronegativity. . Thereby, it is considered that the interface state between Al ₂ O ₃ and the GaN-based semiconductor layer is reduced. Therefore, in addition of Al ₂ O ₃ is as an interface layer, affinity for oxygen is high, and the group III element, in oxide of trivalent transition metal consisting of lanthanoid elements such as Y and La, Al ₂ It is thought that there is an effect similar to O ₃ .

As the interface layer, aluminum silicate (AlSiO) added with Si can be used. Thereby, since crystallization of Al ₂ O ₃ by a high temperature process can be avoided, a low interface state can be realized even under a high temperature process.

As shown in FIG. 1, the semiconductor layer 101 has a stacked structure of a GaN layer 102 and an AlGaN layer 104. An interlayer insulating layer 110 is formed on the AlGaN layer 104. The interlayer insulating layer 110 has an opening (concave portion 112) through which the surface of the AlGaN layer 104 is exposed. A gate insulating layer is formed so as to fill the recess 112. Therefore, the gate electrode 118 is formed on the recessed gate insulating layer. The bottom of the gate electrode 118 is convex downward.
The gate insulating layer has a multilayer structure of an Al ₂ O ₃ film 114 and an SiO ₂ film 116. The entire lower surface of the gate electrode 118 is in contact with the SiO ₂ film 116. Thus, the gate stack structure is the Al ₂ O ₃ film 114, the SiO ₂ film 116, and the gate electrode 118. Near the surface of the semiconductor layer 101 on both sides of the gate stack structure, an n-type source diffusion layer region 106 and an n-type drain diffusion layer region 108 are formed. A source electrode 120 and a drain electrode 122 are formed on these source / drain diffusion layer regions. These source / drain electrodes are formed so as to cover the side walls of the interlayer insulating layer 110, the Al ₂ O ₃ film 114, and the SiO ₂ film 116. The source / drain electrodes are in ohmic contact.

As described above, in the present embodiment, as the gate insulating film used as the upper layer of the interface layer, a metal silicate film having a high dielectric constant such as HfSiO with few charge traps in the film is used as in the case of SiO _2. Is possible.

Next, a method for manufacturing the semiconductor device 200 of the present embodiment will be described.
2 and 3 show process cross-sectional views of the manufacturing procedure of the semiconductor device 200 of the present embodiment.
In the method for manufacturing the semiconductor device 200 according to the present embodiment, a step of forming a substrate (semiconductor substrate 100) having a semiconductor layer 101 containing GaN on at least a part of the surface, and the semiconductor substrate 100 on the semiconductor substrate 100 so as to be in contact therewith. Forming a first gate insulating layer (Al ₂ O ₃ film 114) made of a metal oxide layer that does not contain nitrogen and contains Al; and a first gate insulating layer containing Si and O on the Al ₂ O ₃ film 114. 2 forming a gate insulating layer (SiO ₂ film 116) and forming a gate electrode 118 on the SiO ₂ film 116. The step of forming the gate electrode 118 includes a lower surface of the gate electrode 118. but with formed so as to be in contact with the SiO ₂ film 116, to form an _Al 2 _{O 3} film 114, the film thickness of the _Al 2 _{O 3} film 114 is thinner than the film thickness of the SiO ₂ film 116 It forms so that it may become.

  First, as shown in FIG. 2A, a semiconductor substrate 100 (P-type silicon substrate) is used as a support substrate, and a GaN layer 102 and an AlGaN layer 104 are formed on the semiconductor substrate 100 via a buffer layer (not shown). Epitaxial growth. As the semiconductor substrate 100, a sapphire substrate, a SiC substrate, or the like can be used in addition to a P-type silicon substrate. In addition, the metalorganic vapor phase epitaxy (MOCVD) method can be used for the epitaxial growth, but it is not limited to the MOCVD method, and other methods such as a hydride vapor phase epitaxy (HVPE) method, a molecular beam epitaxy (MBE) method, etc. Alternatively, the growth method may be used. The film thickness of the GaN layer 102 can typically be 200 nm to 2 μm. The film thickness of the AlGaN layer 104 can typically be 1 nm to 50 nm.

As shown in FIG. 2B, a resist is applied on the AlGaN layer 104, and this resist exposure and development are performed to form a resist pattern (not shown). Using this resist pattern as a mask, ion implantation is performed to form a source diffusion layer region 106 and a drain diffusion layer region 108 in the semiconductor layer. At this time, for example, Si is ion-implanted as an n-type dopant and activated at 1150 ° C. to 1260 ° C. The dopant concentration can be, for example, 10 ¹⁹ atoms / cm ³ to 10 ²⁰ atoms / cm ³ .

  After removing the resist, an interlayer insulating layer 110 is formed on the AlGaN layer 104. A silicon nitride film (SiN) can be used as the interlayer insulating layer 110. The interlayer insulating layer 110 is formed using, for example, a Chemical Vapor Deposition (CVD) method. The film thickness of the interlayer insulating layer 110 can be set to, for example, 30 nm to 100 nm.

  Subsequently, as shown in FIG. 2C, a resist pattern (not shown) is formed on the interlayer insulating layer 110. The interlayer insulating layer 110 is etched using this resist pattern as a mask. Thereby, an opening (recess 112) is formed in the interlayer insulating layer 110. The surface of the AlGaN layer 104 is exposed at the bottom of the recess 112. At this time, the etching condition may be a condition that an opening is not formed on the surface of the AlGaN layer 104, or a condition that an opening is formed on the surface of the AlGaN layer 104 so as to embed the gate insulating layer. As the etching, either wet etching or dry etching may be used. From the viewpoint of reducing damage to the semiconductor layer, wet etching can be used.

  Subsequently, the exposed surface of the AlGaN layer 104 is cleaned. A method of rinsing with a liquid is used for cleaning. Although it does not specifically limit as a liquid, Appropriate chemical | medical solutions, such as a hydrofluoric acid and hydrochloric acid, are used.

As shown in FIG. 3A, an Al ₂ O ₃ film 114 is formed as an interface layer on the entire surface of the substrate and inside the recess 112. Subsequently, a SiO ₂ film 116 is formed on the entire surface of the Al ₂ O ₃ film 114. Thereby, the gate insulating layer has a concave shape. As a method for forming the interface layer, for example, an atomic layer deposition (ALD) method can be used. Further, as a method for forming the SiO ₂ film 116, for example, a plasma CVD method can be used.
In addition, the substrate temperature at the time of forming the Al ₂ O ₃ film 114 and the SiO ₂ film 116 is not particularly limited, but can be set to 600 ° C. or lower in any case from the viewpoint of realizing a low interface state.

The film thickness of the interface layer (Al ₂ O ₃ film 114) is made thinner than the film thickness of the SiO ₂ film 116.
In addition, in an electronic device for a power device, a usage environment in which the voltage applied to the gate is 10 V or higher is assumed. In this case, the total film thickness of the gate insulating layer is set to be thicker than about 15 nm. At this time, the thickness of the interface layer (Al ₂ O ₃ film 114) is not less than 0.5 nm and not more than 5 nm, more preferably not less than 1 nm and not more than 4 nm. On the other hand, the thickness of the SiO ₂ film 116 is not particularly limited, but can be 10 nm or more and 100 nm or less.

Next, as shown in FIG. 3B, a gate electrode 118 is selectively formed on the SiO ₂ film 116 so as to fill the recess 112. _Two gate insulating layers (Al ₂ O ₃ film 114 and SiO ₂ film 116) are formed over the entire surface under the gate electrode 118 in the recess 112. In other words, as viewed from above, two gate insulating layers are always formed in the region where the gate electrode 118 is formed in the recess 112.
As the gate electrode 118, an Au / Ni laminated structure can be used. A method for forming the gate electrode 118 is not particularly limited, and a lift-off method can be used.

Subsequently, as shown in FIG. 3C, a resist pattern (not shown) is formed on the SiO ₂ film 116. By selective etching using the resist pattern as a mask, the interlayer insulating layer 110, the Al ₂ O ₃ film 114, and the SiO ₂ film 116 are removed to form an opening. The source diffusion layer region 106 and the drain diffusion layer region 108 are exposed at the bottom of the opening. The source electrode 120 and the drain electrode 122 are selectively formed so as to fill the opening. As the source electrode 120 and the drain electrode 122, for example, an Au / Ni / Al / Ti stacked structure can be used. A method for forming the source / drain electrodes is not particularly limited, and a lift-off method can be used.
Thereafter, by performing heat treatment, the connection between the source electrode 120 and the source diffusion layer region 106 and the connection between the drain electrode 122 and the drain diffusion layer region 108 can be in ohmic contact. The substrate temperature at the time of forming the ohmic contact is not particularly limited, but can be set to 600 ° C. or less from the viewpoint of realizing a low interface state.

Next, the effect of this Embodiment is demonstrated.
In this embodiment, the first gate insulating layer (Al ₂ O ₃ film 114) is used as the interface layer in contact with the semiconductor layer 101 containing GaN. The first gate insulating layer is made of a metal oxide layer containing Al that is more easily oxidized than Ga. For this reason, the oxidation of Ga in the semiconductor layer 101 can be avoided, and the electronegativity between Al and Ga becomes close. Thereby, the interface state generated at the interface between the interface layer and the semiconductor layer 101 can be reduced.
On the other hand, the second insulating layer is made of a material containing Si and O. For this reason, the amount of charge traps generated is small in the second insulating layer. In addition, the thickness of the first gate insulating layer is made thinner than that of the second gate insulating layer. For this reason, compared with the case where the film thickness of the 1st gate insulating layer is the same as the film thickness of the 2nd gate insulating layer, the amount of electric charge traps generated in the 1st gate insulating layer decreases. For this reason, since the amount of charge traps in the entire insulating layer is reduced, hysteresis due to charge traps can be suppressed.
Therefore, according to the present embodiment, it is possible to suppress the hysteresis caused by the charge trap while reducing the interface state, so that the threshold value can be easily controlled. Thereby, a highly reliable semiconductor device can be realized.

In this embodiment, the first gate insulating layer does not contain nitrogen. For this reason, the trap of the electric charge resulting from a nitrogen component can be reduced, and a hysteresis can be suppressed. In addition, defects due to discontinuity can be suppressed at the interface with the oxide insulating film such as SiO _{2 on} the first gate insulating layer. In addition, since the fluctuation of the film stress due to the film forming condition is small, the variation in the characteristics of the GaN-based MISFET using the piezoelectric charge can be suppressed to be small.

  In this embodiment mode, two insulating layers of the first gate insulating layer and the second gate insulating layer are always formed in the region immediately below the gate electrode. Therefore, in this embodiment, the amount of trapped charges can be reduced as compared with the case where the second gate insulating layer is not formed in part of the region immediately below the gate electrode. Therefore, in this embodiment mode, hysteresis can be suppressed as compared with the case where the gate electrode and the first insulating layer are in direct contact with each other, so that variation in threshold value can be further reduced.

In the present embodiment, the AlGaN layer 104 of the GaN-based semiconductor layer and the SiO ₂ film 116 are not directly in contact with each other through the interface layer (Al ₂ O ₃ film 114). In other words, in the present embodiment, the AlGaN layer 104 is formed so that the interface layer (Al ₂ O ₃ film 114) is in direct contact therewith. As a result, an interface having a small interface state is formed between the AlGaN layer 104 and the Al ₂ O ₃ film 114.

On the other hand, the amount of charge trapping in the Al ₂ O ₃ film 114 can be reduced by making the thickness of the interface layer (Al ₂ O ₃ film 114) thinner than that of the SiO ₂ film 116. In other words, the SiO ₂ film 116 is thicker than the interface layer (Al ₂ O ₃ film 114). Since the SiO ₂ film 116 has few charge traps in the film, most of the gate voltage is applied to the SiO ₂ film 116, but charge traps generated by applying a high voltage can be reduced. Therefore, in this embodiment, the variation in threshold value can be suppressed low.

In addition, in an electronic device for a power device, a usage environment in which the voltage applied to the gate is 10 V or higher is assumed. In this case, the total film thickness of the gate insulating layer is set to be thicker than about 15 nm. At this time, the thickness of the interface layer (Al ₂ O ₃ film 114) can be set to 0.5 nm or more and 5 nm or less. When the thickness of the Al ₂ O ₃ film 114 is 5 nm or less, the influence of traps in the Al ₂ O ₃ film 114 can be significantly reduced. On the other hand, when the thickness of the Al ₂ O ₃ film 114 is 0.5 nm or more, the Al ₂ O ₃ film 114 and the AlGaN layer 104 are in contact with each other due to the interface state when the SiO ₂ layer and the AlGaN layer are in contact with each other. The interface state can be reduced.
The thickness of the SiO ₂ film 116 is not particularly limited, but can be 10 nm or more and 100 nm or less. By setting the thickness of the SiO ₂ film 116 within the above range, the amount of charge traps can be reduced. Thereby, the fluctuation | variation of a threshold value can be suppressed low.

The SiO ₂ film 116 may be a gate insulating film with few charge traps in the film. In the present embodiment, a metal silicate film such as hafnium silicate (HfSiOx) may be used instead of the SiO ₂ film 116. In particular, the oxide film equivalent film thickness can be reduced by using a high dielectric constant metal silicate film. Thereby, the control power of the gate can be increased and the on-current can be increased.

As the interface layer (Al ₂ O ₃ film 114), the interface state between the GaN-based semiconductor layer (AlGaN layer 104 / GaN layer 102) is the interface state when the SiO ₂ layer and the AlGaN layer are in contact with each other. The gate insulating film may be smaller than that. In this embodiment, instead of the Al ₂ O ₃ film 114, the affinity for oxygen is higher than that of Ga, and Y ₂ O ₃ that is an oxide of the same group III element as Ga, La ₂ O ₃ , etc. Lanthanoid oxides can be used. That is, the effect of the present embodiment can be obtained even when a trivalent transition metal made of a lanthanoid element such as Y or La is used instead of Al.

Furthermore, as the interface layer, aluminum silicate added with Si (AlSiO) can be used. Thereby, since crystallization of Al ₂ O ₃ by a high temperature process can be avoided, a low interface state can be realized even under a high temperature process.

Example 1
Hereinafter, although this Embodiment is described in detail with reference to an Example, this Embodiment is not limited to description of these Examples at all.
The structure and manufacturing method of Example 1 will be described with reference to FIGS.

A P-type silicon substrate was used as the semiconductor substrate 100. A 2 μm GaN layer 102 and a 30 nm AlGaN layer 104 were epitaxially grown on the semiconductor substrate 100 via a buffer layer (not shown) (FIG. 2A). Subsequently, after covering the region other than the source / drain formation region with a resist, Si was ion-implanted and activated at 1100 ° C. Thereby, the source diffusion layer region 106 and the drain diffusion layer region 108 were formed (FIG. 2B). Subsequently, after removing the resist, a 60 nm silicon nitride film was formed as the interlayer insulating layer 110. Then, the interlayer insulating layer 110 in the region where the gate stack structure is to be formed is removed by etching, and a recess 112 is formed so that the surface of the AlGaN layer 104 is exposed (FIG. 2C). After the surface of the AlGaN layer 104 was washed with an appropriate chemical solution, a 2 nm Al ₂ O ₃ film 114 (interface layer) was formed on the entire surface of the substrate and inside the recess 112 by the ALD method. Subsequently, a 30 nm SiO ₂ film 116 was formed by plasma CVD on the entire surface of the substrate and inside the recess 112 (FIG. 3A). At this time, the substrate temperature at the time of forming the Al ₂ O ₃ film 114 and the SiO ₂ film 116 was set to 550 ° C. or lower in any case. An Au / Ni laminated structure was formed as a gate electrode by a lift-off method so as to bury the recess 112 on the Al ₂ O ₃ film 114 (FIG. 3B). Subsequently, the gate insulating film (Al ₂ O ₃ film 114, SiO ₂ film 116) and the interlayer insulating layer 110 on the source diffusion layer region 106 and the drain diffusion layer region 108 were opened. A source electrode 120 and a drain electrode 122 having an Au / Ni / Al / Ti laminated structure were formed by a lift-off method so as to fill the opening. Then, ohmic contact was formed by performing heat treatment (FIG. 3C). The heat treatment for forming the ohmic contact was 550 ° C. or lower. As described above, the FET (MIS transistor) of Example 1 was manufactured.

(Example 2)
An FET of Example 2 was fabricated in the same manner as Example 1 except that the Al ₂ O ₃ film thickness of the interface layer was changed to 5 nm.

(Comparative Example 1)
A FET of Comparative Example 1 was fabricated in the same manner as Example 1 except that the interface layer Al ₂ O ₃ was not formed.

(Measurement of CV characteristics)
Example 1 _(Al 2 _{O 3} film thickness is 2nm of the interface layer), _(Al 2 _{O 3} film thickness is 5nm interface layers) Example 2, CV characteristics of Comparative Example 1 (without _Al 2 _{O 3} interface layer) Were measured and compared. As a result, compared to Comparative Example 1 in which the interface layer does not have Al ₂ O ₃ , Example 1 and Example 2 can reduce the interface state density at the interface between Al ₂ O ₃ and AlGaN to about 1/10. It was found. Further, when measuring the CV characteristics, the hysteresis was measured when the gate bias was measured by double sweep when the gate bias was from negative to positive and from positive to negative. As a result, it was confirmed that the hysteresis width can be reduced to 100 mV or less in Example 1 while it is about 300 mV or more in Example 2. From the above, it was confirmed that traps in the film could be dramatically reduced by setting the Al ₂ O ₃ film thickness of the interface layer to 5 nm or less. In the present example, it was described that the effect of suppressing the hysteresis was larger at 2 nm than when the Al ₂ O ₃ film thickness was 2 nm and 5 nm. This indicates that the hysteresis increases as the Al ₂ O ₃ film thickness increases, and the effect is always relative. That is, since the Al ₂ O ₃ film thickness is 5 nm, the effect of reducing the hysteresis is not necessarily obtained, and the effect of the present invention is exhibited as compared with a device having Al ₂ O ₃ thicker than 5 nm.

The above results indicate that the presence of thin Al ₂ O ₃ in the interface layer makes it possible to realize a low interface state density at the interface with AlGaN, and the trapping of charges in the Al ₂ O ₃ film. This shows that it is possible to reduce the generated hysteresis. In this embodiment, the formation temperature of Al ₂ O ₃ and SiO ₂ constituting the gate insulating film and the subsequent ohmic contact formation temperature are both 550 ° C. or lower. Such heat treatment effectively suppresses an increase in interface state.

(Example 3)
The structure and manufacturing method of Example 3 will be described with reference to FIG.
Example 3 was the same as Example 1 except that the AlGaN layer 104 directly under the gate was recess-etched to reduce the thickness of the AlGaN layer 104 to about 4 nm.

That is, the same processes as those in Example 1 were performed until the etching of the SiN layer (interlayer insulating layer 110) in FIG. After the SiN layer was removed by etching, the AlGaN layer 104 was removed by etching to a thickness of 4 nm to form a recess 124 (FIG. 4A). The AlGaN layer 104 is exposed at the bottom and side walls of the recess 124. Subsequently, the surface of the AlGaN layer 104 was cleaned with an appropriate chemical solution. Thereafter, a gate insulating layer made of an Al ₂ O ₃ film 114 (interface layer) and a SiO ₂ film 116 was formed on the entire surface of the substrate and inside the recess 124. In the subsequent steps, the same process as in Example 1 was performed again to produce the FET shown in FIG.

In Example 3, the gate insulating layer (Al ₂ O ₃ film 114 and SiO ₂ film 116) is formed in the channel region so as to embed the surface of the GaN-based semiconductor layer (AlGaN layer 104) on the substrate. That is, a gate insulating layer is formed in part of the channel region. For this reason, since the threshold value (Vth) of the FET increases, the normally-on FET characteristics can be normally off. Therefore, according to the present embodiment, an appropriate threshold value can be given as a power device.

In the above embodiment, the case where Al ₂ O ₃ is used as the interface layer and SiO ₂ is used as the upper layer of the interface layer has been described as a typical example, but Y ₂ O ₃ or La ₂ O ₃ is used as the interface layer. Similar effects were obtained with trivalent lanthanoid oxides such as. Furthermore, even when a high dielectric constant metal silicate film such as HfSiO or ZrSiO is used instead of SiO ₂ , a low level of hysteresis can be realized. In addition, by using such a high dielectric constant film, it was possible to increase the breakdown voltage of the gate insulating layer.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  For example, in the present embodiment, an AlGaN / GaN laminated structure is used as a semiconductor as a typical example, but other laminated structures such as a p-GaN / AlGaN / GaN structure having a p-type GaN structure on the outermost surface, for example. Even so, the same effect as the present embodiment can be obtained.

  In this embodiment, Au / Ni by lift-off method is used as the gate electrode, but a metal gate that can be processed by reactive ion etching such as TiN is used without departing from the spirit of the present invention. May be. For the source / drain contact, for example, Al may be used as an electrode used instead of Au.

100 Semiconductor substrate 101 Semiconductor layer 102 GaN layer 104 AlGaN layer 106 Source diffusion layer region 108 Drain diffusion layer region 110 Interlayer insulating layer 112 Recess 114 Al ₂ O ₃ film 116 SiO ₂ film 118 Gate electrode 120 Source electrode 122 Drain electrode 124 Recess 200 Semiconductor device

Claims (10)

A substrate having a semiconductor layer containing GaN on at least a part of its surface;
A first gate insulating layer which is provided on the substrate so as to be in contact with the semiconductor layer and which is made of a metal oxide layer not containing nitrogen and containing Al;
A second gate insulating layer provided on the first gate insulating layer and containing Si and O;
A gate electrode provided on the second gate insulating layer,
A lower surface of the gate electrode is in contact with the second gate insulating layer;
The semiconductor device, wherein the first gate insulating layer is thinner than the second gate insulating layer. A substrate having a semiconductor layer containing GaN on at least a part of its surface;
A first gate insulating layer which is provided on the substrate so as to be in contact with the semiconductor layer and which includes a metal oxide layer which does not include nitrogen and includes a trivalent transition metal including Y (yttrium) or a lanthanoid;
A second gate insulating layer provided on the first gate insulating layer and containing Si and O;
A gate electrode provided on the second gate insulating layer,
A lower surface of the gate electrode is in contact with the second gate insulating layer;
The semiconductor device, wherein the first gate insulating layer is thinner than the second gate insulating layer. The semiconductor device according to claim 1, wherein the second gate insulating layer includes a SiO ₂ film or a metal silicate film.   4. The semiconductor device according to claim 1, wherein a film thickness of the first gate insulating layer is 0.5 nm or more.   5. The semiconductor device according to claim 1, wherein the first gate insulating layer has a thickness of 5 nm or less.   The semiconductor device according to claim 1, wherein the semiconductor layer containing GaN has a stacked structure made of AlGaN and GaN.   The semiconductor device according to claim 1, wherein the first gate insulating layer contains Si. Forming a substrate having a semiconductor layer containing GaN on at least a portion of the surface;
Forming a first gate insulating layer made of a metal oxide layer not containing nitrogen and containing Al on the substrate so as to be in contact with the semiconductor layer;
Forming a second gate insulating layer containing Si and O on the first gate insulating layer;
Forming a gate electrode on the second gate insulating layer,
The step of forming the gate electrode includes forming the lower surface of the gate electrode in contact with the second gate insulating layer,
The step of forming the first gate insulating layer is a method for manufacturing a semiconductor device, wherein the film thickness of the first gate insulating layer is formed to be thinner than the film thickness of the second gate insulating layer. Forming a substrate having a semiconductor layer containing GaN on at least a portion of the surface;
Forming a first gate insulating layer made of a metal oxide layer containing a trivalent transition metal made of Y (yttrium) or lanthanoid on the substrate so as to be in contact with the semiconductor layer;
Forming a second gate insulating layer containing Si and O on the first gate insulating layer;
Forming a gate electrode on the second gate insulating layer,
The step of forming the gate electrode includes forming the lower surface of the gate electrode in contact with the second gate insulating layer,
The step of forming the first gate insulating layer is a method for manufacturing a semiconductor device, wherein the film thickness of the first gate insulating layer is formed to be thinner than the film thickness of the second gate insulating layer.   10. The method according to claim 8, wherein the step of forming the first gate insulating layer, the step of forming the second gate insulating layer, and the step of forming the gate electrode are performed under conditions of 600 ° C. or lower. A method for manufacturing a semiconductor device.

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