JP7167793B2 - Semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device made of a Group III nitride semiconductor.

2. Description of the Related Art In manufacturing a semiconductor device made of a group III nitride semiconductor, it is necessary to go through a large number of resist mask formation and stripping steps, such as patterning of a gate insulating film, formation of trenches, and film formation of electrodes.

Patent document 1 describes a trench gate type vertical HFET. A vertical HFET has a laminate in which a drift layer made of n ⁻ -GaN, a p-GaN layer, and a cap layer made of n ⁺ -GaN are sequentially laminated on a GaN substrate. Further, it has a trench penetrating the cap layer and the p-GaN layer to reach the drift layer, and a regrowth layer continuously provided in the form of a film on the trench bottom surface, the side surface, and the cap layer surface, and the regrowth layer is It is described that it is composed of an electron transit layer made of i-GaN and an electron supply layer made of AlGaN. Further, it is described that a groove is provided through the regrowth layer and the cap layer to reach the p-GaN layer, a p-side electrode is provided on the bottom surface of the groove, and a source electrode is provided on the p-side electrode and the regrowth layer. It is

Further, in Patent Document 1, a groove for forming the p-portion electrode is formed by dry etching using a resist mask, then the resist mask is removed, another resist mask is provided, vapor deposition is performed, and lift-off is performed to form the p-portion electrode. Forming electrodes is described. After that, a resist mask is further provided, and a source electrode is formed on the p-side electrode and the regrown layer by vapor deposition and lift-off. In this way, it is described that the formation and peeling of the resist mask are repeated multiple times.

Patent Document 2 describes suppressing the adhesion between the insulating film and the resist mask by forming a resist mask on the insulating film without subjecting the surface of the insulating film to a hydrophobic surface treatment or the like. ing. Then, when the insulating film exposed in the opening of the resist mask is removed by wet etching, the insulating film is thinned by introducing an etchant into the gap between the insulating film and the resist mask from the side surface.

JP 2011-82397 A JP 2016-162786 A

In the manufacture of a semiconductor device, a resist mask is formed over an insulating film, dry etching or wet etching is performed using the resist mask, the resist mask is removed, and then another resist mask is formed over the insulating film. Then, a step of wet-etching the insulating film using the resist mask may be included. In the second wet etching using the resist mask, the etchant enters between the resist mask and the insulating film, causing the insulating film to be abnormally side-etched, resulting in etching of portions that should remain.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to prevent abnormal side etching when a resist mask is formed again on an insulating film and the insulating film is wet-etched in a method of manufacturing a semiconductor device.

A first aspect of the present invention comprises a first step of forming a first insulating film made of a material containing Si as a constituent element on a semiconductor layer; a second step of forming one resist mask; a third step of removing the first resist mask; and a fourth step of forming a second insulating film made of a material containing Si as a constituent element on the first insulating film. a fifth step of forming a second resist mask made of resist and having an opening on the second insulating film; and wet-etching the first insulating film and the second insulating film exposed in the opening of the second resist mask. and a sixth step.

In the first aspect of the present invention, after the second step and before the third step, the first insulating film exposed in the opening of the first resist mask is removed by wet etching to expose the surface of the semiconductor layer. forming a first metal film on the semiconductor layer and on the first resist mask; may be removed to leave the first metal film on the semiconductor layer.

Further, in the first aspect of the present invention, after the sixth step, a second metal film is formed on the second resist mask and on the bottom surface of the opening of the second resist mask, and the second resist mask is removed. 2 The method may further include a step of removing the second metal film on the resist mask and leaving the second metal film on the bottom of the opening of the second resist mask.

Moreover, in the first aspect of the present invention, the first insulating film and the second insulating film may be SiO ₂ , and the fourth step may be a step of forming the second insulating film by ALD. Further, after the fourth step and before the fifth step, a step of subjecting the surface of the second insulating film to HMDS treatment may be included.

A second aspect of the present invention comprises a first step of forming a first insulating film made of a material that does not contain Si as a constituent element on a semiconductor layer; a second step of forming a second insulating film consisting of a second insulating film, a third step of forming a first resist mask made of resist and having an opening on the second insulating film, and a fourth step of removing the first resist mask a fifth step of forming a third insulating film made of a material containing Si as a constituent element on the second insulating film; and forming a second resist mask made of a resist and having an opening on the third insulating film. and a seventh step of wet etching the first insulating film, the second insulating film, and the third insulating film exposed in the opening of the second resist mask. manufacturing method.

In the second aspect of the present invention, after the third step and before the fourth step, the first insulating film exposed in the opening of the first resist mask is removed by wet etching to expose the surface of the semiconductor layer. forming a first metal film on the semiconductor layer and the first resist mask; and removing the first resist mask in the fourth step to form the first metal film on the first resist mask may be removed to leave the first metal film on the semiconductor layer.

In the second aspect of the present invention, after the seventh step, a second metal film is formed on the second resist mask and on the bottom surface of the opening of the second resist mask, and the second resist mask is removed to form the second metal film. A step of removing the second metal film on the resist mask and leaving the second metal film on the bottom of the opening of the second resist mask may be further included.

Moreover, in the second aspect of the present invention, the first insulating film may be Al ₂ O ₃ , and the second insulating film and the third insulating film may be SiO ₂ . The second step may be a step of forming the second insulating film by ALD, and the fifth step may be a step of forming the third insulating film by ALD. Further, after the fifth step and before the sixth step, a step of subjecting the surface of the third insulating film to HMDS treatment may be included.

In the present invention, the adhesion of the second resist mask to the insulating film can be improved, and abnormal side etching of the insulating film can be prevented.

1 is a diagram showing a configuration of a semiconductor device of Example 1; FIG. 4A and 4B are diagrams showing a manufacturing process of the semiconductor device of Example 1; 4A and 4B are diagrams showing a manufacturing process of the semiconductor device of Example 1; 4A and 4B are diagrams showing a manufacturing process of the semiconductor device of Example 1; 4A and 4B are diagrams showing a manufacturing process of the semiconductor device of Example 1; 4A and 4B are diagrams showing a manufacturing process of the semiconductor device of Example 1;

Specific examples of the present invention will be described below with reference to the drawings, but the present invention is not limited to the examples.

FIG. 1 is a diagram showing the configuration of the semiconductor device of Example 1. FIG. As shown in FIG. 1, the semiconductor device of Example 1 is a trench gate type vertical FET, and includes a substrate 110, a first n-layer 120, a p-layer 130, a second n-layer 140, a trench It has T1, recess R1, insulating film F1, gate electrode G1, source electrode S1, body electrode B1, and drain electrode D1. The insulating film F1 corresponds to the first insulating film and the second insulating film of the invention.

The substrate 110 is a 300-μm-thick planar substrate made of Si-doped n-GaN with a c-plane as the principal surface. Si concentration is 1×10 ¹⁸ /cm ³ . In addition to n-GaN, a substrate of any material that has conductivity and can serve as a growth substrate for a Group III nitride semiconductor can be used. For example, ZnO, Si, etc. can also be used. However, from the viewpoint of lattice matching, it is desirable to use a GaN substrate as in this embodiment.

The first n-layer 120 is a Si-doped n-GaN layer laminated on the substrate 110 (one surface 100a of the substrate 110) and having the c-plane as the main surface. The first n-layer 120 has a thickness of 10 μm and a Si concentration of 1×10 ¹⁶ /cm ³ .

The p-layer 130 is stacked on the first n-layer 120 and is a Mg-doped p-GaN layer having the c-plane as the main surface. The p-layer 130 has a thickness of 1.0 μm and a Mg concentration of 2×10 ¹⁸ /cm ³ .

The second n-layer 140 is stacked on the p-layer 130 and is a Si-doped n-GaN layer having the c-plane as the main surface. The second n-layer 140 has a thickness of 0.2 μm and a Si concentration of 1×10 ¹⁸ /cm ³ .

Trench T1 is a groove formed at a predetermined position on the surface of second n-layer 140 and has a depth that reaches first n-layer 120 through second n-layer 140 and p-layer 130 . First n-layer 120 is exposed at bottom surface T1a of trench T1, and first n-layer 120, p-layer 130 and second n-layer 140 are exposed at side surface T1b of trench T1. The side surface of the p layer 130 exposed to the side surface T1b of the trench T1 is the region that operates as the channel of the FET of the first embodiment. Moreover, the side surface T1b of the trench T1 is an a-plane, and the a-plane is provided with fine unevenness. The unevenness widens the area of the side surface T1b of the trench T1, thereby improving the electrical characteristics of the semiconductor device.

The insulating film F1 is continuously provided in a film shape over the bottom surface T1a of the trench T1, the side surface T1b, and the surface of the second n layer 140 (excluding the formation region of the source electrode S1). The insulating film F1 serves as both a gate insulating film and a passivation film. The passivation film is provided to suppress current leakage on the surface of the second n-layer 140 .

The insulating film F1 is composed of three layers in which a first insulating film F1A made of Al ₂ O ₃ , a second insulating film F1B made of SiO ₂ , and a third insulating film F1C made of SiO ₂ are laminated in this order. The second insulating film F1B and the third insulating film F1C are layers necessary for enhancing adhesion with a resist mask used when forming the body electrode B1 and the source electrode S1. Details will be described in the section of the manufacturing method to be described later.

The thickness of the first insulating film F1A is 100 nm. The thickness of the first insulating film F1A is not limited to this, and may be any thickness necessary for the gate insulating film and passivation film. The thickness of the second insulating film F1B and the third insulating film F1C is 10 nm. Although the thicknesses of the second insulating film F1B and the third insulating film F1C are not limited to this, they are preferably 2 to 20 nm. Within this range, coverage is sufficient, and the precision of patterning of the insulating film F1 by wet etching can be improved. More preferably, it is 5 to 15 nm.

Insulating materials other _{than Al2O3} such as _ZrON , AlON, ZrO2, HfO2, HfON, SiOF, SiOC, and _SiO2 can be used as the material of the _first insulating film F1A. The first insulating film F1A may be composed of a plurality of layers. If a material containing Si as a constituent element is used as the outermost layer of the first insulating film F1A, the second insulating film F1B need not be provided. The reason will be explained in the stage of the manufacturing method.

As the material of the second insulating film F1B and the third insulating film F1C, any insulating material containing Si as a constituent element can be used other than SiO ₂ . For example, SiOF, SiOC, and SiON can be used. . In particular, as in Example 1, SiO ₂ is preferred. This is because it can be formed using the ALD method, which has excellent step coverage.

Although the insulating film F1 serves as both the gate insulating film and the passivation film in the first embodiment, it may serve only as the passivation film and the gate insulating film may be provided separately.

The gate electrode G1 is provided in the form of a film continuously on the bottom surface T1a of the trench T1, the side surface T1b, and the upper surface of the trench T1 via the insulating film F1. The gate electrode G1 is made of Al.

The recess R1 is a groove provided at a predetermined position on the surface of the second n-layer 140 and has a depth reaching the p-layer 130 through the second n-layer 140 . The p-layer 130 is exposed at the bottom of the recess R1, and the p-layer 130 and the second n-layer 140 are exposed at the side. The side surface of the recess R1 is an m-plane.

Body electrode B1 is provided on the bottom surface of recess R1. The body electrode B1 is made of Pd.

Source electrode S1 is continuously provided over body electrode B1 and second n layer 140 . The source electrode S1 is made of Ti/Al.

The drain electrode D1 is provided on the back surface of the substrate 110 (the surface 100b opposite to the side on which the first n-layer 120 is provided). The drain electrode D1 is made of the same material as the source electrode S1, namely Ti/Al.

Next, a method for manufacturing the semiconductor device of Example 1 will be described with reference to FIGS. 3 to 6 show the region near the recess R1.

First, a substrate 110 made of n-GaN having a c-plane as a principal surface is prepared, and a first n-layer 120, a p-layer 130, and a second n-layer 140 are sequentially formed by MOCVD (FIG. 2(a)). )reference). In the MOCVD method, the nitrogen source is ammonia, the Ga source is trimethylgallium (Ga( _CH3 ) ₃ :TMG), the In source is trimethylindium (In( _CH3 ) ₃ :TMI), and the Al source is trimethylaluminum. (Al( _CH3 ) ₃ :TMA). The n-type dopant gas is silane (SiH ₄ ), and the p-type dopant gas is cyclopentadienylmagnesium (Mg(C ₅ H ₅ ) ₂ :CP ₂ Mg). Carrier gas is hydrogen or nitrogen.

Next, trenches T1 are formed by dry etching predetermined positions on the surface of the second n-layer 140 (see FIG. 2B). Dry etching is performed until the first n-layer 120 is exposed. A chlorine-based gas is used for dry etching. Examples are _Cl2 , _SiCl4 , _CCl4 . Any method such as ICP etching can be used for dry etching.

Next, wet etching is performed on the side surface T1b of the trench T1 using a TMAH (tetramethylammonium hydroxide) aqueous solution. The TMAH aqueous solution can wet-etch the group III nitride semiconductor other than the c-plane, and the wet-etching progresses until the m-plane is exposed. As a result, a layer damaged by dry etching can be removed. Moreover, the side surface T1b can be made perpendicular to the surface of the second n-layer 140, and the breakdown voltage can be improved. Moreover, the side surface T1b of the trench T1 is an a-plane. Therefore, the side surface T1b of the trench T1 is etched into a sawtooth-like notch formed by m-planes. The sawtooth shape increases the area of the side surface T1b of the trench T1, thereby improving the electrical characteristics of the semiconductor device. As the wet etching solution, NaOH (sodium hydroxide), KOH (potassium hydroxide), _{H3PO4 (} phosphoric acid), etc. can be used in addition to TMAH.

Next, a predetermined position on the surface of the second n-layer 140 is dry-etched to form a recess R1 (see FIG. 2(c)). Etching is performed until the p-layer 130 is exposed. The etching gas is the same as that for forming the trench T1.

Although the recess R1 is formed after forming the trench T1 in the first embodiment, the recess R1 may be formed first and then the trench T1 may be formed.

After forming the recess R1, the side surface of the recess R1 may be wet-etched. A layer damaged by dry etching can be removed, and the pattern of the recess R1 can be formed with higher accuracy. The wet etching solution at this time is the same as that used in the wet etching of the side surface T1b of the trench T1.

Next, the p-layer 130 is made p-type by heating in a nitrogen atmosphere. Since hydrogen is efficiently released from the p-layer 130 exposed by the bottom surface of the recess R1, Mg in the p-layer 130 can be efficiently activated.

Next, a first insulating film F1A made of Al ₂ O ₃ is formed by ALD continuously on the bottom surface T1a and side surfaces T1b of the trench T1 and the surface of the second n-layer 140 (see FIG. 3A). . By using the ALD method, the first insulating film F1A can be formed with a uniform thickness even if there is a step due to the trench T1. Although the first insulating film F1A is formed using the ALD method because of its high step coverage in the first embodiment, it may be formed by sputtering, CVD, or the like.

Next, a second insulating film F1B made of SiO ₂ is formed on the first insulating film F1A by ALD (see FIG. 3B). The second insulating film F1B is provided to improve adhesion with the first resist mask RM1 to be formed in the next step. Since the first insulating film F1A is made of Al ₂ O ₃ and does not contain Si as a constituent element, the adhesion to the resist is low even after the HMDS treatment. Therefore, by sandwiching a second insulating film F1B made of SiO ₂ , which is a material containing Si as a constituent element, the adhesion with the first resist mask RM1 is improved. When the material of the first insulating film F1A is a material containing Si as a constituent element, the adhesion between the first insulating film F1A and the first resist mask RM1 is sufficient. can be omitted.

The reason why the ALD method is used to form the second insulating film F1B is to uniformly cover the entire surface of the first insulating film F1A. If the second insulating film F1B is not formed to have a uniform and sufficient thickness, there may be a region not covered with the second insulating film F1B on part of the surface of the first insulating film F1A. As a result, a region having low adhesion to the first resist mask RM1 to be formed in the next process is generated, and the patterning of the first insulating film F1A and the second insulating film F1B in the subsequent process may not be performed with high accuracy. For this reason, the thickness of the second insulating film F1B is preferably 2 to 20 nm, more preferably 5 to 15 nm.

The second insulating film F1B may be formed continuously after forming the first insulating film F1A. Further, in the first embodiment, the second insulating film F1B is formed using the ALD method because of its high step coverage, but it may be formed by sputtering, CVD, or the like.

Next, the surface of the second insulating film F1B is subjected to HMDS processing, and a first resist mask RM1 is formed on the second insulating film F1B by photolithography (see FIG. 4A). The first resist mask RM1 is a pattern that is open so as to include the recess R1 and its vicinity in plan view. A positive photoresist is used for the first resist mask RM1.

Next, the first insulating film F1A and the second insulating film F1B exposed in the opening of the first resist mask RM1 are removed by wet etching, and the bottom (p layer 130) and side surfaces of the recess R1 and the second n layer 140 are removed. A region of the surface near the recess R1 is exposed (see FIG. 4B). Hydrofluoric acid (HF), for example, is used as the wet etchant.

Next, a first metal film M1 to be the body electrode B1 is formed on the first resist mask RM1 and on the bottom of the opening of the first resist mask RM1 (the bottom of the recess R1, the side surface, the region near the recess R1 in the surface of the n layer 140). is formed (see FIG. 4(c)). The first metal film M1 is formed by vapor deposition or sputtering.

Next, the first resist mask RM1 is removed using a stripping solution, and the remaining first resist mask RM1 is removed by ashing using oxygen plasma. The first metal film M1 on the first resist mask RM1 is removed, leaving the first metal film M1 formed on the bottom of the opening of the first resist mask RM1. Thus, the first metal film M1 is patterned by the lift-off method to form the body electrode B1 (see FIG. 4D).

Next, a third insulating film F1C made of SiO ₂ is formed continuously on the body electrode B1 and the second insulating film F1B by ALD (see FIG. 5).

The reason why the third insulating film F1C is provided is to make the outermost surface of the insulating film F1 free from resist application history. A first resist mask RM1 is formed and removed from the surface of the second insulating film F1B. Therefore, the surface condition of the second insulating film F1B has changed, and adhesion is poor when a resist mask is provided again on the surface of the second insulating film F1B. The surface state of the second insulating film F1B is not recovered even if the surface of the second insulating film F1B is subjected to HMDS processing. Therefore, by providing the third insulating film F1C on the second insulating film F1B, the outermost surface of the insulating film F1 is reset to a state in which there is no resist coating history, and the second resist is formed on the third insulating film F1C in the next step. Good adhesion is obtained when the mask RM2 is formed.

The reason why the ALD method is used as the method of forming the third insulating film F1C is to form it so as to uniformly cover the entire surface of the second insulating film F1B. If the third insulating film F1C is not formed uniformly and with a sufficient thickness, there may be a region not covered with the third insulating film F1C on a part of the surface of the second insulating film F1B. Such a region is a region with a resist coating history, and is a region with low adhesion to the second resist mask RM2 to be formed in the next step. Therefore, abnormal side etching may occur in wet etching of the first insulating film F1A, the second insulating film F1B, and the third insulating film F1C in the post-process. For this reason, the thickness of the third insulating film F1C is preferably 2 to 20 nm, more preferably 5 to 15 nm.

Next, the surface of the third insulating film F1C is subjected to HMDS processing, and a second resist mask RM2 is formed on the third insulating film F1C by photolithography (see FIG. 6A). The second resist mask RM2 is a pattern that is open so as to include the body electrode B1 and its vicinity in plan view. A positive photoresist is used for the second resist mask RM2.

Next, the first insulating film F1A, the second insulating film F1B, and the third insulating film F1C exposed in the opening of the second resist mask RM2 are removed by wet etching, and the body electrode B1 and the surface of the second n layer 140 are removed. Of these, the region near the body electrode B1 is exposed (see FIG. 6B). Hydrofluoric acid (HF), for example, is used as the wet etchant.

Here, since the second resist mask RM2 is provided on the surface of the third insulating film F1C that has no resist coating history, it has good adhesion to the third insulating film F1C, and the wet etching solution can be used as the second resist mask RM2. It does not enter between the third insulating films F1C. Therefore, abnormal side etching is prevented, the amount of side etching is small, and the first insulating film F1A, the second insulating film F1B, and the third insulating film F1C are wet-etched in a pattern substantially identical to the opening pattern of the second resist mask RM2. can do.

Next, on the second resist mask RM2 and on the bottom surface of the opening of the second resist mask RM2 (on the body electrode B1 and on the surface of the second n layer 140 near the recess R1), a second metal film M2 that becomes the source electrode S1 is formed. forming (see FIG. 6(c)). The second metal film M2 is formed by vapor deposition or sputtering.

Next, the second resist mask RM2 is removed using a stripping solution, and the remaining second resist mask RM2 is removed by ashing using oxygen plasma. The second metal film M2 on the second resist mask RM2 is removed, leaving the second metal film M2 formed on the bottom of the opening of the second resist mask RM2. Thus, the second metal film M2 is patterned by the lift-off method to form the source electrode S1 (see FIG. 6D).

Next, a lift-off method is used to form a gate electrode G1, and a lift-off method is used to form a drain electrode D1 on the rear surface of the substrate 110. Next, as shown in FIG. As described above, the semiconductor device of Example 1 shown in FIG. 1 is manufactured.

As described above, in the method of manufacturing a semiconductor device according to the first embodiment, the third insulating film F1C is formed on the second insulating film F1B having a resist coating history, the surface is made to have no resist coating history, and the resist is applied. A second resist mask RM2 is formed over the third insulating film F1C with no history. Therefore, it is possible to prevent abnormal side etching from occurring when wet-etching the first insulating film F1A, the second insulating film F1B, and the third insulating film F1C using the second resist mask RM2.

Next, experimental results regarding the semiconductor device of Example 1 will be described.

(Experiment 1)
A sample 1 up to the stage of manufacturing the second resist mask RM2 was manufactured by the manufacturing process of the semiconductor device of the first embodiment. That is, this is the step of removing the first resist mask RM1, forming the third insulating film F1C on the second insulating film F1B, and further forming the second resist mask RM2 having an opening on the third insulating film F1C. . The first insulating film F1A was made of Al ₂ O ₃ with a thickness of 100 nm, and the second insulating film F1B and the third insulating film F1C were made of SiO ₂ with a thickness of 10 nm. Sample 1 thus produced was subjected to wet etching using hydrofluoric acid for 5 minutes.

As a result, no penetration of the wet etchant was observed between the second resist mask RM2 and the third insulating film F1C, side etching was 100 nm, and no abnormal side etching was observed.

(Experiment 2)
A second insulating film F1B is formed by the manufacturing process of the semiconductor device of Example 1, and a second resist mask RM2 having an opening on the second insulating film F1B is formed. The materials and thicknesses of the first insulating film F1A and the second insulating film F1B are the same as in Experiment 1. Sample 2 thus produced was subjected to wet etching using hydrofluoric acid for 5 minutes.

As a result, penetration of the wet etchant was observed between the second resist mask RM2 and the second insulating film F1B, and floating and displacement of the second resist mask RM2 occurred. In addition, penetration of the wet etchant was observed up to a position of 10 μm or more from the opening of the second resist mask RM2. As described above, abnormal side etching occurred in the sample 2 in which the third insulating film F1C was not formed.

(Experiment 3)
A sample 3 was produced in the same manner as in Experiment 2, except that the thickness of the second insulating film F1B was changed from 10 nm to 50 nm.

As a result, as in Experiment 2, abnormal side etching occurred.

From the results of Experiments 1 to 3, it can be seen that abnormal side etching is not a problem of the thickness of the insulating film, but the presence or absence of resist coating history on the surface of the insulating film is important. , it was found that it is necessary to form a resist mask on an insulating film that has no history of resist coating.

(Modification)
Although the first embodiment uses the present invention to continuously form the body electrode B1 and the source electrode S1, the present invention is not limited to this. The present invention can be applied to any method of manufacturing a semiconductor device that includes steps of forming a resist mask again on an insulating film and wet-etching the insulating film.

In addition, the present invention is applicable not only to semiconductor devices made of Group III nitride semiconductors, but also to methods of manufacturing semiconductor devices made of any semiconductor material.

The present invention can be used to manufacture various semiconductor devices such as FETs and diodes.

110: substrate 120: first n-layer 130: p-layer 140: second n-layer F1: insulating film F1A: first insulating film F1B: second insulating film F1C: third insulating film G1: gate electrode S1: source Electrode B1: body electrode D1: drain electrode T1: trench R1: recess RM1: first resist mask RM2: second resist mask M1: first metal film M2: second metal film

Claims (13)

a first step of forming a first insulating film made of a material containing Si as a constituent element on a semiconductor layer;
a second step of forming a first resist mask made of resist and having an opening on the first insulating film;
a third step of removing the first resist mask;
a fourth step of forming a second insulating film made of a material containing Si as a constituent element on the first insulating film;
a fifth step of forming a second resist mask made of resist and having an opening on the second insulating film;
a sixth step of wet etching the first insulating film and the second insulating film exposed in the opening of the second resist mask;
A method of manufacturing a semiconductor device, comprising: After the second step and before the third step, the first insulating film exposed in the opening of the first resist mask is removed by wet etching to expose the surface of the semiconductor layer, and the exposed semiconductor layer is removed. a step of forming a first metal film on the top and on the first resist mask;
The third step is a step of removing the first metal film on the first resist mask and leaving the first metal film on the semiconductor layer by removing the first resist mask.
2. The method of manufacturing a semiconductor device according to claim 1, wherein: After the sixth step, a second metal film is formed on the second resist mask and on the bottom surface of the opening of the second resist mask, and the second resist mask is removed to form a metal film on the second resist mask. removing the second metal film and leaving the second metal film on the bottom of the opening of the second resist mask;
3. The method of manufacturing a semiconductor device according to claim 1, wherein: 4. The method of manufacturing a semiconductor device according to claim 1, wherein said first insulating film and said second insulating film are made of _SiO2 . 5. The method of manufacturing a semiconductor device according to claim 1, wherein said fourth step is a step of forming said second insulating film by an ALD method. 6. The semiconductor device according to claim 1, further comprising a step of subjecting the surface of said second insulating film to HMDS processing after said fourth step and before said fifth step. manufacturing method. a first step of forming a first insulating film made of a material that does not contain Si as a constituent element on the semiconductor layer;
a second step of forming a second insulating film made of a material containing Si as a constituent element on the first insulating film;
a third step of forming a first resist mask made of resist and having an opening on the second insulating film;
a fourth step of removing the first resist mask;
a fifth step of forming a third insulating film made of a material containing Si as a constituent element on the second insulating film;
a sixth step of forming a second resist mask made of resist and having an opening on the third insulating film;
a seventh step of wet etching the first insulating film, the second insulating film, and the third insulating film exposed in the opening of the second resist mask;
A method of manufacturing a semiconductor device, comprising: After the third step and before the fourth step, the first insulating film exposed in the opening of the first resist mask is removed by wet etching to expose the surface of the semiconductor layer, and the exposed semiconductor layer is removed. a step of forming a first metal film on the top and on the first resist mask;
The fourth step is a step of removing the first metal film on the first resist mask and leaving the first metal film on the semiconductor layer by removing the first resist mask.
8. The method of manufacturing a semiconductor device according to claim 7, wherein: After the seventh step, a second metal film is formed on the second resist mask and on the bottom surface of the opening of the second resist mask, and the second resist mask is removed to form a metal film on the second resist mask. removing the second metal film and leaving the second metal film on the bottom of the opening of the second resist mask;
9. The method of manufacturing a semiconductor device according to claim 7, wherein: 10. The method of manufacturing a semiconductor device according to claim ₇ , wherein said first insulating film is made of _Al2O3 . 11. The method of manufacturing a semiconductor device according to claim 7, wherein said second insulating film and said third insulating film are made of _SiO2 . The second step is a step of forming the second insulating film by an ALD method,
The fifth step is a step of forming the third insulating film by an ALD method,
12. The method of manufacturing a semiconductor device according to claim 7, wherein: 13. The semiconductor device according to claim 7, further comprising a step of subjecting the surface of said third insulating film to HMDS processing after said fifth step and before said sixth step. manufacturing method.

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