KR102087944B1 - Power Semiconductor Device - Google Patents

Abstract

The power semiconductor device of the embodiment includes a substrate, an epi layer disposed on the substrate, a passivation layer disposed on the epi layer, a gate electrode disposed on the epi layer while passing through the passivation layer, and a top and side portions of the gate electrode. And a contact electrode spaced apart from the gate metal layer and over the epitaxial layer.

Description

Power semiconductor device

Embodiments relate to a power semiconductor device.

Gallium nitride (GaN) materials with wide energy bandgap properties are suitable for power semiconductor device applications such as power switches such as excellent forward characteristics, high break down voltage and low intrinsic carrier density.

Examples of power semiconductor devices include Schottky barrier diodes, metal semiconductor field effect transistors, and high electron mobility transistors (HEMTs).

In the case of such a power semiconductor device, a high resistance of the gate electrode requires a large amount of driving energy, a delay time occurs in a state transition between turn-on and turn-off, and a breakdown voltage is low due to leakage current. There is a problem losing.

Embodiments provide a power semiconductor device in which leakage current is reduced to not only have a high breakdown voltage but also a switching delay time.

The power semiconductor device according to the embodiment includes a substrate; An epitaxial layer disposed on the substrate; A passivation layer disposed on the epitaxial layer; A gate electrode disposed on the epitaxial layer while passing through the passivation layer; A gate metal layer disposed on top and sides of the gate electrode; And a contact electrode spaced apart from the gate metal layer and disposed on the epitaxial layer.

The power semiconductor device may further include a gate insulating layer disposed between the gate electrode and the epi layer, between the gate electrode and the passivation layer, and between the gate metal layer and the passivation layer.

The gate electrode may include a gate penetrating portion penetrating the passivation layer in a first direction; And a gate wing extending from the gate through portion in a second direction different from the first direction and disposed on the passivation layer.

The gate insulating layer may be disposed between the bottom surface of the gate through portion and the top surface of the epi layer, between the bottom surface of the gate wing portion and the top surface of the passivation layer, and between the side surface and the passivation layer of the gate through portion.

The contact electrode penetrating the passivation layer and contacting the epi layer; And a contact wing extending from the contact through portion and disposed on the passivation layer.

The bottom surface of the contact wing may directly contact the top surface of the passivation layer or the top surface of the gate insulating layer.

The power semiconductor device may include an intermediate insulating layer disposed to cover upper and side portions of the gate metal layer; And a contact pad penetrating the intermediate insulating layer and electrically connected to the contact electrode.

The gate metal layer and the contact electrode may include the same material.

The gate metal layer may include a material having a resistance lower than that of TiN.

The gate metal layer may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), and gold (Au) in a single layer or a multilayer structure.

The thickness of the gate metal layer may be the same as the thickness of the contact electrode. For example, the gate metal layer may have a thickness of 2000 kPa to 4000 kPa.

In the power semiconductor device according to the embodiment, because the gate metal layer having a lower resistance than TiN is disposed on the gate electrode, the specific resistance decreases and the cross-sectional area increases to decrease the resistance, so that the energy required for driving the power semiconductor device decreases and is turned. The switching delay time due to the state transition between off and turn-on is reduced, and the absence of an intermediate insulating layer protecting the gate electrode improves the characteristics of the leakage current, which can result in breakdown voltage as high as 600 volts, the manufacturing process is simple, and the manufacturing process Cost can be reduced.

1 is a sectional view of a power semiconductor device according to an embodiment.
2 is a cross-sectional view according to an embodiment of the epi layer shown in FIG. 1.
3 illustrates a cross-sectional view of an embodiment of the gate metal layer illustrated in FIG. 1.
4A to 4M are cross-sectional views illustrating a method of manufacturing the power semiconductor device according to the embodiment.
5A to 5D show cross-sectional views of a power semiconductor device of another embodiment.
6 is a graph showing the leakage current when the power semiconductor element includes the first intermediate insulating layer and when it is not.

Hereinafter, the present invention will be described in detail with reference to examples, and detailed description will be made with reference to the accompanying drawings to help understanding of the present invention. However, embodiments according to the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

In the description of the present embodiment, when described as being formed on "on or under" of each element, the above (up) or below (down) ( on or under includes both that two elements are in direct contact with one another or one or more other elements are formed indirectly between the two elements.

In addition, when expressed as "up" or "on (under)", it may include the meaning of the downward direction as well as the upward direction based on one element.

Furthermore, the relational terms used below, such as "first" and "second," "upper" and "lower" and the like, do not necessarily require or imply any physical or logical relationship or order between such entities or elements. It may be used only to distinguish one entity or element from another entity or element.

1 is a sectional view of a power semiconductor device according to an embodiment.

The power semiconductor device illustrated in FIG. 1 includes a substrate 110, an epi layer 120, a passivation layer 130, an intermediate insulation layer 140, and contact pads 152 and 154. And contact electrodes 160 and 180, gate electrode 170, and gate metal layer 172.

The substrate 110 may be a silicon substrate, a silicon carbide substrate, a GaN substrate, or a sapphire substrate, but the embodiment is not limited to the type of the substrate 110.

In addition, the substrate 110 may be defined by being divided into an isolation area (IA) and an active area (AA). The active area AA of the substrate 110 is an area in which the epi layer 120 is disposed, and the device isolation area IA is an area that electrically separates adjacent power semiconductor devices from each other.

The epi layer 120 is disposed on the substrate 110. In the case of FIG. 1, the epi layer 120 is shown only in the active region AA of the substrate 110 and not in the device isolation region IA, but the embodiment is not limited thereto. For example, unlike the example illustrated in FIG. 1, the epi layer 120 may be disposed in both the isolation region IA and the active region AA. In this case, impurities may be doped into the epitaxial layer 120 disposed in the device isolation region IA to electrically isolate adjacent power semiconductor devices.

2 is a cross-sectional view according to an embodiment of the epi layer 120 shown in FIG.

1 and 2, the epi layer 120 disposed on the substrate 110 in the active region AA includes a transition layer 122, a buffer layer (or a first nitride semiconductor layer) 124. ) And a barrier layer (or second nitride semiconductor layer) 126.

The buffer layer 124 is disposed on the substrate 110. The buffer layer 124 may be an undoped semiconductor layer. The buffer layer 124 may be formed of a semiconductor compound. It can be implemented with compound semiconductors, such as group 3-5 or 2-6. For example, it may include a semiconductor material having a compositional formula of Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). The buffer layer 124 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP, but is not limited thereto.

The channel layer 124A may be formed on the buffer layer 124 adjacent to the barrier layer 126. That is, the channel layer 124A is disposed above the buffer layer 124 below the boundary between the barrier layer 126 and the buffer layer 124.

In addition, the transition layer 122 may be further disposed between the substrate 110 and the buffer layer 124. The transition layer 122 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like, but embodiments are not limited thereto, and the transition layer 122 may be omitted.

The barrier layer 126 is disposed over the buffer layer 124. The barrier layer 126 is a layer arranged to help the formation of the channel layer 124A, and serves to bend the band gap energy. The barrier layer 126 is a layer having a larger band width than the channel layer 124A, and may have a uniform polarization density throughout the layer, and different band gap energy between the barrier layer 126 and the buffer layer 124. By heterojunction having a two-dimensional electron gas (2DEG: 2-Dimensional Electron Gas) can be generated in the channel layer 124A.

For example, the barrier layer 126 may be implemented with a compound semiconductor, such as Groups 3-5 or 2-6. For example, it may include a semiconductor material having a compositional formula of Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). The barrier layer 126 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP.

The thickness of the barrier layer 126 may be 20 nm or less, but embodiments are not limited to the thickness of this barrier layer 126.

The passivation layer 130 is disposed on the epi layer 120. In the case of FIG. 1, the passivation layer 130 is illustrated as being disposed not only on the top of the epi layer 120 but also on the substrate 110 of the device isolation region IA, but the embodiment is not limited thereto. For example, unlike shown in FIG. 1, the passivation layer 130 may not be disposed on the side of the epi layer 120, but may be disposed only on the epi layer 120.

The passivation layer 130 is a type of etching prevention layer to prevent the epi layer 120 from being etched in the process of forming the gate electrode 170, the source contact 160, and the drain contact 180 by a metal etching method. Protection). The passivation layer 130 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD.

Meanwhile, the gate electrode 170 is disposed on the epitaxial layer 120 while passing through the passivation layer 130. In some embodiments, the gate electrode 170 may include a gate penetrating portion 170-1 and gate wing portions 170-2 and 170-3. The gate through part 170-1 may pass through the passivation layer 130 in the first direction. The gate wings 170-2 and 170-3 may extend from the gate through part 170-1 in a second direction different from the first direction and be disposed on the passivation layer 130. Here, the first direction is the x-axis direction and the second direction may be perpendicular to each other as the y-axis direction, but embodiments are not limited thereto.

The gate electrode 170 may include a metal material. For example, the gate electrode 170 may be a refractory metal or a mixture of such refractory metals. Alternatively, the gate electrode 170 may include at least one of Ta (Tantalum), TaN (Tantalum Nitride), TiN (Titanium Nitride), Pd (Palladium), W (tungsten), or WSi ₂ (Tungstem silicide). have.

In an embodiment, the gate metal layer 172 is disposed on the upper portion 170A and the side portion 170B of the gate electrode 170. For example, the gate metal layer 172 covers and covers the upper portion 170A and the side portion 170B of the gate electrode 170.

The gate metal layer 172 may include the same material as the material of the contact electrodes 160 and 180. This is because the gate metal layer 172 may also be formed when the contact electrodes 160 and 180 are formed, as described below. As such, when the gate metal layer 172 is formed together with the contact electrodes 160 and 180, the first thickness t1 of the gate metal layer 172 is equal to the second thickness t2 of the contact electrodes 160 and 180. May be the same. If the second thickness t2 of the contact electrodes 160 and 180 is smaller than 2000 kV or larger than 4000 kV, the ohmic contact of the contact electrodes 160 and 180 may not be formed. Therefore, the second thickness t2, that is, the first thickness t1 of the gate metal layer 172 may be 2000 kPa to 4000 kPa.

However, according to another embodiment, the gate metal layer 172 may include a material different from that of the contact electrodes 160 and 180.

The gate metal layer 172 described above may include a material having a resistance lower than that of TiN. For example, the gate metal layer 172 may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), and gold (Au). Can be formed.

3 illustrates a cross-sectional view of an embodiment of the gate metal layer 172 illustrated in FIG. 1.

Referring to FIG. 3, the gate metal layer 172 may take a form in which Ti 172-1, Al 172-2, and Ti 172-3 are sequentially stacked from the bottom up, for example. Embodiments are not so limited.

In addition, as illustrated in FIG. 1, the side surfaces 170B of the gate wings 170-2 and 170-3 of the gate electrode 170 and the side portions 172A of the gate metal layer 172 have a first angle θ 1. It may be formed to be inclined by. Here, the first angle θ1 may be a positive number of 0 ° or more.

Generally, a method for suppressing leakage current of a GaN-based power semiconductor device includes a floating gate, a field-modulating plate, an overlapping gate structure, and a source expansion field plate. Various field concentration mitigation structures, such as extended field pallets and multiple field plates, have been developed. For example, a field plate (not shown) is disposed to relieve electric field concentration at edges of the gate electrode 170.

However, in the power semiconductor device according to the embodiment, since the gate wings 170-2 and 170-3 of the gate electrode 170 serve as the field plates, it is not necessary to form a separate field plate. As such, since the gate wings 170-2 and 170-3 serve as field plates, concentration of an electric field may be alleviated and thus the breakdown voltage of the power semiconductor device may be improved. That is, the electric field concentrated at the edge of the gate through part 170-1 may be dispersed by the gate wings 170-2 and 170-3.

In addition, according to the embodiment, since the gate metal layer 172 is disposed to surround the gate electrode 170, the gate metal layer 172 adjacent to the gate wings 170-2 and 170-3 serves as a field plate. You can also reinforce it.

In general, the resistance R1 of the gate electrode 170 may be expressed by Equation 1 below.

Here, p represents a specific resistance, L represents the length of the gate electrode 170, A represents the cross-sectional area of the gate electrode 170.

In general, the gate electrode 170 is implemented with TiN. In this case, TiN is 20 mA / sq and has higher resistance than other metal materials. As described above, when the resistance of the gate electrode 170 is high, the resistance at the end of the gate electrode 170 increases from several kV to several hundred kV. As a result, a large amount of energy may be required when the power semiconductor device is driven, and the switching time required for the state transition between the turn-off and turn-on of the power semiconductor device may be increased. .

However, according to the embodiment, the gate metal layer 172 is disposed to surround the gate electrode 170, and the sum of the resistance R1 of the gate electrode 170 and the resistance R2 of the gate metal layer 172 (RT). ) Is shown in Equation 2 below.

Referring to Equation 2, since the gate metal layer 172 having a resistance lower than that of TiN is disposed on the gate electrode 170, the specific resistance ρ 'of Equation 2 is greater than that of Equation 1 ρ. It decreases and the cross-sectional area (A ') of the equation (2) is increased than the cross-sectional area (A) of the equation (1). Therefore, as compared with when only the gate electrode 170 is disposed without the gate metal layer 172, the sum RT of the resistors becomes smaller than the resistor R1. As a result, energy required for driving the power semiconductor device may be reduced, and switching time for switching the state between the turn-off and turn-on of the power semiconductor device may be reduced.

The contact electrodes 160 and 180 are spaced apart from the gate metal layer 172 in the horizontal direction, for example, in the y-axis direction, and disposed on the epitaxial layer 120. The contact electrodes 160 and 180 may include a source contact 160 and a drain contact 180. The source contact 160 is spaced apart from one side of the gate metal layer 172 and disposed on the epi layer 120, and the drain contact 160 is spaced apart from the other side of the gate metal layer 172 and disposed on the epi layer 120. In this case, the source contact 160 and the drain contact 180 may pass through the passivation layer 130 to be in electrical contact with the epi layer 120.

Each of the source contact 160 and the drain contact 180 may include a contact through portion and a contact wing portion. For example, referring to FIG. 1, the source contact 160 may include a contact through portion 160-1 and contact wing portions 160-2 and 160-3. The contact penetrating portion 160-1 penetrates the passivation layer 130 in the third direction to contact the epi layer 120, and the contact wing portions 160-2 and 160-3 are contact penetrating portions 160-1. May extend from the third direction to a fourth direction different from the third passivation layer 130. Here, the third direction may be the x-axis direction and the fourth direction may be perpendicular to each other as the y-axis direction, but embodiments are not limited thereto.

Each of the source contact 160 and the drain contact 180 may be formed of a metal. As described above, each of the source contact 160 and the drain contact 180 may include the same material as the gate metal layer 172 or the gate electrode 170 or may include another material. Source and drain contacts 160 and 180 may be formed of a reflective electrode material having ohmic characteristics. For example, each of the source and drain contacts 160 and 180 may include at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), and gold (Au). It may be formed in a single layer or a multilayer structure. For example, each of the source contact 160 and the drain contact 180 may have a form in which TiN is further stacked on the Ti 172-3 illustrated in FIG. 3.

In addition, as illustrated in FIG. 1, the side surfaces (eg, 160-2B) of the contact vanes (eg, 160-2, 160-3) of the contact electrodes 160, 180 may have a second angle ( It may be formed to be inclined by θ2). Here, the second angle θ2 may be a positive number of 0 ° or more.

Meanwhile, the power semiconductor device illustrated in FIG. 1 may further include a gate insulating layer 190, but embodiments are not limited thereto. According to another embodiment, unlike in FIG. 1, the power semiconductor device may not include the gate insulating layer 190.

Referring to FIG. 1, the gate insulating layer 190 may pass between the gate electrode 170 and the epi layer 120, between the gate electrode 170 and the passivation layer 130, and passivation with the gate metal layer 172. It may be disposed between the layers 130. Specifically, the gate insulating layer 190 is disposed between the bottom surface 170-1A of the gate through part 170-1 and the top surface 120A of the epi layer 120, and the gate wings 170-2 and 170. -3) disposed between the bottom surfaces 170-2A and 170-3A and the top surfaces 130A and 130B of the passivation layer 130, and passivating the side surfaces 170-1B of the gate through portions 170-1. May be disposed between layers 130.

Gate insulating layer 190 is Al ₂ O ₃ The same may be an aluminum oxide layer, a silicon oxide layer such as SiO ₂ , or a silicon nitride layer. For example, the aluminum oxide layer may have a thickness of 100 μs to 300 μs, but embodiments are not limited thereto.

In addition, each of the source contact 160 and the drain contact 180 may pass through the gate insulating layer 190 as well as the passivation layer 130 to be in electrical contact with the epi layer 120.

In addition, the gate insulating layer 190 is disposed between the bottom surfaces 160-2A and 160-3A of the contact wings 160-2 and 160-3 and the top surfaces 130A and 130C of the passivation layer 130. In this case, the bottom surfaces 160-2A and 160-3A of the contact wing portions 160-2 and 160-3 may be disposed in direct contact with the top surface of the gate insulating layer 190. If the gate insulating layer 190 is omitted, the bottom surfaces 160-2A and 160-3A of the contact wings 160-2 and 160-3 are electrically connected to the top surfaces 130A and 130C of the passivation layer 130. It can be placed in direct contact with.

The intermediate insulating layer 140 may be disposed to surround the upper portion 172B and the side portion 172A of the gate metal layer 172. The intermediate insulating layer 140 may include the same material as the passivation layer 130, but is not limited thereto. For example, the intermediate insulating layer 140 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD.

The contact pads 152 and 154 are electrically connected to the source contact 160 and the drain contact 180 through the intermediate insulating layer 140, respectively. The contact pads include source and drain pads 152 and 154, and may be formed by at least one of gold (Au), aluminum (Al), or copper (Cu), although embodiments may include such source and drain pads 152. , 154).

Hereinafter, a method of manufacturing the power semiconductor device illustrated in FIG. 1 will be described as follows with reference to FIGS. 4A to 4M, but embodiments are not limited thereto, and the power illustrated in FIG. Of course, the semiconductor device can be manufactured.

4A to 4M are cross-sectional views illustrating a method of manufacturing the power semiconductor device according to the embodiment.

Referring to FIG. 4A, an epitaxial layer 120 is formed on the substrate 110. The substrate 110 may be formed using silicon, silicon carbide, GaN or sapphire. As illustrated in FIG. 2, the epitaxial layer 120 may be formed by sequentially stacking the transition layer 122, the buffer layer 124, and the barrier layer 126 on the substrate 110.

The transition layer 122 may be formed using aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like. The buffer layer 124 may be an undoped semiconductor layer.

The buffer layer 124 may be formed of a semiconductor compound, and may be implemented as a compound semiconductor, such as Groups 3-5 or 2-6. For example, the buffer layer 124 may be formed using a semiconductor material having a compositional formula of Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Can be formed. The buffer layer 124 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP, but is not limited thereto.

The barrier layer 126 may be formed using a compound semiconductor, such as group 3-group 5 or group 2-group 6. For example, a semiconductor material having a compositional formula of Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), or GaN, InN, The barrier layer 126 may be formed of any one or more of AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP.

Subsequently, referring to FIG. 4B, the epitaxial layer 120 of the device isolation region IA of the substrate 110 is etched and removed using a conventional photolithography process, but embodiments are not limited thereto. . For example, the etching of the epi layer 120 may use dry etching. In another embodiment, impurity ions may be implanted into the epitaxial layer 120 of the device isolation region without etching the epitaxial layer 120 of the device isolation region of the substrate 110.

Subsequently, referring to FIG. 4C, the passivation layer 130 is formed on the side and the top of the epi layer 120 shown in FIG. 4B, but the embodiment is not limited thereto. For example, in another embodiment, the passivation layer 130 may be formed only on the epi layer 120. The passivation layer 130 may include metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), PECVD, LPCVD, molecular beam epitaxy (MBE), inductively coupled plasma chemical vapor deposition (MBE). (ICPCVD: Inductively Coupled Plasma Chemical Vapor Deposition), Hydride Vapor Phase Epitaxy (HVPE), and the like, and the like, but are not limited thereto.

Subsequently, referring to FIG. 4D, the passivation layer 130 is etched using a conventional photolithography process, whereby a gate insulating layer 190 is disposed and a gate through portion 170-1 of the gate electrode 170 is formed. The area 210 to be exposed is exposed.

Subsequently, referring to FIG. 4E, the gate insulating layer 190 is formed on the passivation layer 130B including the region 210 where the epi layer 120 is exposed. In another embodiment, the gate insulating layer 190 may be omitted. The gate insulating layer 190 may be formed to have a thickness of, for example, 15 nm by an aluminum oxide layer, a silicon oxide layer, or a silicon nitride layer, but embodiments are not limited thereto. For example, the gate insulating layer 190 may be formed of an aluminum oxide layer (Al ₂ O ₃ ) by atomic layer deposition.

4F, a metal layer 170 is formed on the gate insulating layer 190, and then a photoresist pattern 220 covering the region where the gate electrode 170 is to be formed is formed. The metal layer 170 may be formed using e-beam evaporation or metal sputter. When the metal layer 170 is formed on the gate insulating layer 190 by the metal sputter, the metal layer 170 may be formed better than the electron beam deposition method. After the metal layer 170 is formed, subsequent heat treatment may be performed. For example, rapid thermal annealing may be performed at 400 ° C. for 10 minutes. Here, the metal layer 170 may be a refractory metal or a mixture of such refractory metals. Alternatively, the metal layer 170 may include at least one of Ta (Tantalum), TaN (Tantalum Nitride), TiN (Titanium Nitride), Pd (Palladium), W (tungsten), or WSi ₂ (Tungstem silicide). .

Subsequently, referring to FIG. 4G, the gate layer 170 may be formed by etching the metal layer 170 using an inductively coupled plasma (ICP) etching method using the photoresist pattern 220 as an etching mask. Thereafter, the photoresist pattern 220 is removed by ashing and / or stripping.

In addition, since the passivation layer 130 is etched instead of the epi layer 120 after the gate insulating layer 190 is etched while the metal layer 170 is etched using the photoresist pattern 220 as an etch mask, the epi layer is etched. 120 may be protected from etching of the metal layer 170. As described above, the passivation layer 130 serves as an etch stop layer to protect the epi layer 120, in particular, the barrier layer 126 from the etching of the metal layer 170.

Subsequently, referring to FIG. 4H, the photoresist pattern 230 exposing the regions 211 and 212 where the source contact 160 and the drain contact 180 are to be formed is provided with the gate electrode 170 and the gate insulating layer 190. Form on top.

4I, the gate insulating layer 190 and the passivation layer 130 of the exposed regions 211 and 212 are etched using the photoresist pattern 230 as an etching mask. At this time, for example, the barrier layer 126 may be further etched into some of the epi layer 120, but embodiments are not limited to this etch depth. For example, the barrier layer 126 of the epi layer 120 may be etched to 150 kPa. Thereafter, the photoresist pattern 230 is removed.

Subsequently, referring to FIG. 4J, the metal layer 240 is formed on the exposed epitaxial layer 120, the gate electrode 170, and the gate insulating layer 170. Here, the metal layer 240 may be formed in a single layer or a multilayer structure including at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), and gold (Au). have. Thereafter, photoresist patterns 250-1 and 250-2 covering the regions where the contact electrodes 160 and 180 are to be formed are formed on the metal layer 240. In particular, according to the embodiment, a photoresist pattern 250-3 covering the region where the gate metal layer 172 is to be formed is formed on the metal layer 240.

4K, the photoresist patterns 250-1, 250-2, and 250-3 are used as etching masks, and the metal layer 240 is etched by, for example, inductively coupled plasma (ICP) etching. The contact electrodes 160 and 180 and the gate metal layer 172 are simultaneously formed. After the contact electrodes 160 and 180 are formed, heat treatment is performed at a temperature of 700 ° C. for the ohmic characteristics of the contact electrodes 160 and 180. Thereafter, the photoresist patterns 250-1, 250-2, and 250-3 are removed.

5A to 5D show cross-sectional views of a power semiconductor device of another embodiment.

After forming the gate electrode 170 as shown in FIG. 4G, instead of forming the contact electrodes 160 and 180 using the process shown in FIGS. 4H-4K, shown in FIGS. 5A-5D. The process may use a process to form the source contact 360 and the drain contact 380.

That is, referring to FIG. 5A, the first intermediate insulating layer 310 is formed on the gate electrode 170 and the gate insulating layer 190 shown in FIG. 4G. The first intermediate insulating layer 310 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD. Thereafter, a photoresist pattern 320 is formed on the first intermediate insulating layer 310 to expose regions 332 and 334 on which the source contact 360 and the drain contact 380 are to be formed.

Subsequently, referring to FIG. 5B, the barrier of the first intermediate insulating layer 310, the gate insulating layer 190, the passivation layer 130, and the epi layer 120 using the photoresist pattern 320 as an etching mask. The layer 126 is etched to expose the epi layer 120. Thereafter, the photoresist pattern 320 is removed.

Subsequently, referring to FIG. 5C, a metal layer 340 is formed on the exposed epitaxial layer 120 and the first intermediate insulating layer 310. Thereafter, a photoresist pattern 350 is formed on the metal layer 340 to cover a region where the source contact 360 and the drain contact 380 are to be formed.

Subsequently, referring to FIG. 5D, the metal layer 340 is etched using the photoresist pattern 350 as an etch mask to form the source contact 360 and the drain contact 380. Thereafter, the photoresist pattern 350 is removed.

Here, as shown in FIG. 5D, the first intermediate insulating layer 310 serves to protect the gate electrode 170 from the process of etching the metal layer 340 to form the contact electrodes 360 and 380. . However, as shown in FIG. 5D, after forming the source contact 360 and the drain contact 380, during heat treatment at a temperature of about 700 ° C. to improve the ohmic properties of these 360, 380, Material characteristics of the power semiconductor device may be deteriorated, such as a material change in the first intermediate insulating layer 310 to generate a leakage current. If a leakage current occurs, it may be difficult to implement a power semiconductor device having a desired breakdown voltage.

However, as shown in FIGS. 4H to 4K, when the contact electrodes 160 and 180 are formed, the first intermediate insulating layer 310 is unnecessary. Therefore, since the first intermediate insulating layer 310 to be deformed in the heat treatment process after the contact electrodes 160 and 180 are formed as shown in FIG. 4K does not exist, generation of a leakage current is prevented, resulting in high breakdown voltage. A power semiconductor device having can be implemented.

In addition, when the contact electrodes 160 and 180 are formed as illustrated in FIGS. 4H to 4K, the first intermediate insulating layer 310 may not be formed as illustrated in FIGS. 5A to 5D. The process can be simplified and manufacturing costs can be reduced.

4L, a second intermediate insulating layer 140 is formed on the contact electrodes 160 and 180, the gate electrode 170, and the gate insulating layer 190. The second intermediate insulating layer 140 may be formed of the same material as the passivation layer 130, but embodiments are not limited thereto. The second intermediate insulating layer 140 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD. Thereafter, the photoresist pattern 260 exposing the second intermediate insulating layer 140 regions 215 and 216 of the upper portions 160A and 180A of the contact electrodes 160 and 180 to be in contact with the contact pads 152 and 154. To form.

4M, the second intermediate insulating layer 140 is etched using the photoresist pattern 260 as an etch mask to expose the top surfaces 160A and 180A of the contact electrodes 160 and 180. The photoresist pattern 260 is removed. Thereafter, the metal layer 150 is formed on the upper surfaces 160A and 180A of the exposed contact electrodes 160 and 180 and the second intermediate insulating layer 140. Thereafter, a photoresist pattern 270 is formed on the metal layer 150 to cover a region where the contact pads 152 and 154 are to be disposed. Thereafter, the metal layer 150 is etched using the photoresist pattern 270 as an etching mask to form contact pads 152 and 154. Thereafter, the photoresist pattern 270 is removed to complete the power semiconductor device illustrated in FIG. 1.

In the above-described embodiment, the photolithography method is used as an example for the etching process, but the embodiment is not limited thereto, and the etching process may be performed by the e-bem lithography method or the nano-imprinted lithography method.

Hereinafter, the magnitude of the leakage current when the power semiconductor device includes the first intermediate insulating layer 310 and when it is not, will be described as follows.

FIG. 6 is a graph illustrating leakage current when the power semiconductor device includes the first intermediate insulating layer 310 (410) or not (420). Here, the horizontal axis represents the drain voltage (V), and the vertical axis represents the leakage current.

Referring to FIG. 6, when the power semiconductor device includes the first intermediate insulation layer 310 (410), a material change is caused in the first intermediate insulation layer 310 to increase the leakage current generated in the power semiconductor element. Can be.

However, when the power semiconductor device does not include the first intermediate insulating layer 310 (420), it can be seen that the leakage current generated in the power semiconductor device is reduced (430). As a result, it is possible to implement a power semiconductor device having a desired breakdown voltage.

Although described above with reference to the embodiments, which are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should not be exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to these modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

110: substrate 120 epi layer
122: transition layer 124: buffer layer
126: barrier layer 130: passivation layer
140: intermediate insulation layer (or second intermediate insulation layer)
152 and 154: contact pads 160 and 180: contact electrodes
170: gate electrode 172: gate metal layer
310: first intermediate insulating layer 340: metal layer
360: source contact 380: drain contact

Claims (12)

Board;
An epitaxial layer disposed on the substrate;
A passivation layer disposed on the epitaxial layer;
A gate electrode disposed on the epitaxial layer while passing through the passivation layer;
A gate metal layer on top and sides of the gate electrode; And
A contact electrode spaced apart from the gate metal layer and disposed on the epitaxial layer,
And a resistance of the gate metal layer is lower than that of the gate electrode. The power semiconductor device of claim 1, further comprising a gate insulating layer disposed between the gate electrode and the epi layer, between the gate electrode and the passivation layer, and between the gate metal layer and the passivation layer. . The method of claim 1, wherein the gate electrode
A gate through part penetrating the passivation layer in a first direction; And
And a gate vane extending from the gate penetrating portion in a second direction different from the first direction and disposed on the passivation layer. delete The method of claim 2, wherein the contact electrode is
A contact through part penetrating the passivation layer and in contact with the epi layer; And
And a contact vane extending from the contact through portion and disposed on the passivation layer. delete The method of claim 1, wherein the power semiconductor device
An intermediate insulating layer surrounding the upper and side portions of the gate metal layer; And
And a contact pad penetrating the intermediate insulating layer and electrically connected to the contact electrode. delete delete delete delete delete

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