KR20150030371A - Power Semiconductor Device - Google Patents

Abstract

A power semiconductor device of an embodiment comprises: a substrate; an epitaxial layer disposed on the substrate; a passivation layer disposed on the epitaxial layer; a gate electrode disposed on the epitaxial layer while passing through the passivation layer; a gate metal layer disposed on a side part or an upper part of the gate electrode; and a contact electrode disposed on the epitaxial layer as placed apart from the gate metal layer.

Description

[0001] Power Semiconductor Device [0002]

An embodiment relates to a power semiconductor device.

Gallium nitride (GaN) materials with broad energy bandgap characteristics are suitable for power semiconductor devices such as power switches, such as excellent forward characteristics, high breakdown voltage, and low intrinsic carrier density.

Schottky barrier diodes, metal semiconductor field effect transistors, and high electron mobility transistors (HEMTs) are known as power semiconductor devices.

In the case of such a power semiconductor device, since the resistance of the gate electrode is high, a large amount of driving energy is required and a delay time occurs in the state transition between turn-on and turn-off, and the breakdown voltage is low due to leakage current .

Embodiments provide a power semiconductor device in which the leakage current is reduced to have a high breakdown voltage as well as a reduced switching delay time.

A power semiconductor device according to an embodiment includes: a substrate; An epi layer disposed on the substrate; A passivation layer disposed over the epilayer; A gate electrode disposed on the epi layer through the passivation layer; A gate metal layer disposed on top and sides of the gate electrode; And a contact electrode spaced from the gate metal layer and disposed over the epi layer.

The power semiconductor device may further include a gate insulating layer disposed between the gate electrode and the epi layer, between the gate electrode and the passivation layer, and between the gate metal layer and the passivation layer.

Wherein the gate electrode comprises: a gate penetration portion penetrating the passivation layer in a first direction; And a gate wing portion extending from the gate penetration portion in a second direction different from the first direction and disposed on the passivation layer.

The gate insulating layer may be disposed between the bottom surface of the gate penetration portion and the top surface of the epi layer, between the bottom surface of the gate wing portion and the top surface of the passivation layer, and between the side surface of the gate penetration portion and the passivation layer.

The contact electrode may include a contact penetration portion that penetrates the passivation layer and contacts the epi layer; And a contact wing extending from the contact penetration portion and disposed on the passivation layer.

The bottom surface of the contact wing portion directly contacts the upper surface of the passivation layer or the upper surface of the gate insulating layer.

Wherein the power semiconductor device comprises: an intermediate insulating layer disposed over and over the gate metal layer; And a contact pad electrically connected to the contact electrode through the intermediate insulating layer.

The gate metal layer and the contact electrode may comprise the same material.

The gate metal layer may comprise a material having a resistance lower than the resistance of TiN.

The gate metal layer may include at least one of aluminum (Al), titanium (Ti), chrome (Cr), nickel (Ni), copper (Cu), and gold (Au)

The thickness of the gate metal layer may be the same as the thickness of the contact electrode. For example, the thickness of the gate metal layer may be 2000 Å to 4000 Å.

In the power semiconductor device according to the embodiment, since the resistivity is decreased and the cross-sectional area is increased and the resistance is decreased because the gate metal layer having a lower resistance than TiN is disposed on the gate electrode, the energy required for driving the power semiconductor device is decreased, Switching delay time due to switching between off and turn-on is reduced and there is no intermediate insulating layer for protecting the gate electrode. Thus, leakage current characteristics are improved, and a breakdown voltage of about 600 volts can be obtained. Cost can be reduced.

1 is a cross-sectional view of a power semiconductor device according to an embodiment.
Figure 2 shows a cross-sectional view of an embodiment of the epi layer shown in Figure 1;
Figure 3 shows a cross-sectional view of an embodiment of the gate metal layer illustrated in Figure 1;
4A to 4M are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
5A to 5D show a process sectional view of a power semiconductor device in another embodiment.
6 is a graph showing the leakage current in the case where the power semiconductor element includes the first intermediate insulating layer and in the case where the power semiconductor element includes the first intermediate insulating layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the present embodiment, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) on or under includes both the two elements being directly in contact with each other or one or more other elements being indirectly formed between the two elements.

Also, when expressed as "on" or "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

It is also to be understood that the terms "first" and "second", "upper" and "lower", etc., as used below, do not necessarily imply or imply any physical or logical relationship or order between such entities or elements And may be used only to distinguish one entity or element from another entity or element.

1 is a cross-sectional view of a power semiconductor device according to an embodiment.

The power semiconductor device illustrated in Figure 1 includes a substrate 110, an epi layer 120, a passivation layer 130, an intermediate insulating layer 140, contact pads 152 and 154, Contact electrodes 160 and 180, a gate electrode 170, and a gate metal layer 172. As shown in FIG.

The substrate 110 may be a silicon substrate, a silicon carbide substrate, a GaN substrate, or a sapphire substrate, but the embodiment is not limited to the type of the substrate 110.

In addition, the substrate 110 may be defined as being divided into an isolation region (IA) and an active region (AA). The active region AA of the substrate 110 is an area where the epi layer 120 is disposed and the element isolation region IA is an area that electrically isolates adjacent power semiconductor elements from each other.

An epi layer 120 is disposed over the substrate 110. In the case of FIG. 1, although the epi layer 120 is shown only in the active region AA of the substrate 110 and not in the element isolation region IA, the embodiment is not limited thereto. For example, unlike the example illustrated in FIG. 1, the epi layer 120 may be disposed in both the element isolation region IA and the active region AA. In this case, in order to electrically isolate adjacent power semiconductor elements from each other, the epitaxial layer 120 disposed in the element isolation region IA may be doped with impurities.

FIG. 2 shows a cross-sectional view of an embodiment of the epi layer 120 shown in FIG.

1 and 2, an epi layer 120 disposed on a substrate 110 in an active region AA includes a transition layer 122, a buffer layer (or a first nitride semiconductor layer) 124 And a barrier layer (or a second nitride semiconductor layer) 126.

The buffer layer 124 is disposed on the substrate 110. The buffer layer 124 may be an undoped semiconductor layer. The buffer layer 124 may be formed of a semiconductor compound. 3-group-5 or group-6-group compound semiconductors. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1). The buffer layer 124 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

The channel layer 124A may be formed on top of the buffer layer 124 adjacent to the barrier layer 126. [ That is, the channel layer 124A is disposed above the buffer layer 124 below the interface between the barrier layer 126 and the buffer layer 124. [

In addition, a transition layer 122 may be further disposed between the substrate 110 and the buffer layer 124. The transition layer 122 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and the like, but the embodiment is not limited thereto and the transition layer 122 may be omitted.

The barrier layer 126 is disposed over the buffer layer 124. The barrier layer 126 is a layer disposed to assist in forming the channel layer 124A, and serves to warp band gap energy. The barrier layer 126 may have a uniform bandgap energy of the barrier layer 126 and the buffer layer 124. The barrier layer 126 may have a higher band gap than the channel layer 124A, 2-Dimensional Electron Gas (2DEG) can be generated in the channel layer 124A by the heterojunction with the heterojunction.

For example, the barrier layer 126 may be implemented with compound semiconductors such as Group 3-Group 5 or Group 2-Group 6. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1). The barrier layer 126 may be formed of one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

The thickness of the barrier layer 126 may be 20 nm or less, but the embodiment is not limited to this thickness of the barrier layer 126.

A passivation layer 130 is disposed over the epi layer 120. In the case of FIG. 1, the passivation layer 130 is shown as being disposed on the substrate 110 of the element isolation region IA as well as covering the upper portion and the side of the epi layer 120, but the embodiment is not limited thereto. 1, the passivation layer 130 may not be disposed on the side of the epi layer 120 but may be disposed only on the top of the epi layer 120. [

The passivation layer 130 may be formed as an etch stop layer to prevent the epitaxial layer 120 from being etched in the process of forming the gate electrode 170, the source contact 160, and the drain contact 180 by a metal etching method, Protection). The passivation layer 130 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD.

On the other hand, the gate electrode 170 is disposed on the epi-layer 120 while passing through the passivation layer 130. According to the embodiment, the gate electrode 170 may include the gate penetration portion 170-1 and the gate wing portions 170-2 and 170-3. The gate penetration portion 170-1 may penetrate the passivation layer 130 in the first direction. The gate wing portions 170-2 and 170-3 may extend from the gate penetration portion 170-1 in a second direction different from the first direction and may be disposed on the passivation layer 130. [ Here, the first direction may be the x-axis direction and the second direction may be perpendicular to each other as the y-axis direction, but the embodiment is not limited to this.

The gate electrode 170 may comprise a metallic material. For example, the gate electrode 170 may be a refractory metal or a mixture of such refractory metals. Alternatively, the gate electrode 170 may comprise at least one of Ta (Tantalum), TaN (Tantalum Nitride), TiN (Titanium Nitride), Pd (Palladium), W (tungsten) or WSi ₂ (Tungstem silicide) have.

According to the embodiment, a gate metal layer 172 is disposed on top 170A and side 170B of gate electrode 170. [ For example, the gate metal layer 172 covers the upper portion 170A and the side portion 170B of the gate electrode 170. [

The gate metal layer 172 may comprise the same material as the material of the contact electrodes 160 and 180. [ This is because, as described later, a gate metal layer 172 can also be formed when the contact electrodes 160 and 180 are formed. As such, when the gate metal layer 172 is formed with the contact electrodes 160 and 180, the first thickness t1 of the gate metal layer 172 is greater than the second thickness t2 of the contact electrodes 160 and 180, Can be the same. If the second thickness t2 of the contact electrodes 160 and 180 is less than 2000 angstroms or greater than 4000 angstroms, the ohmic contact of the contact electrodes 160 and 180 may not be formed. Thus, the second thickness t2, i. E., The first thickness t1 of the gate metal layer 172 may be 2000 A to 4000 A.

However, according to another embodiment, the gate metal layer 172 may comprise a material different from the material of the contact electrodes 160 and 180.

The aforementioned gate metal layer 172 may comprise a material having a lower resistance than the resistance of TiN. For example, the gate metal layer 172 may include a single layer or a multilayer structure including at least one of aluminum (Al), titanium (Ti), chrome (Cr), nickel (Ni), copper (Cu) .

FIG. 3 shows a cross-sectional view of an embodiment of the gate metal layer 172 illustrated in FIG.

3, the gate metal layer 172 may take the form of, for example, sequentially stacking Ti (172-1), Al (172-2) and Ti (172-3) The embodiment is not limited to this.

1, the side surface 170B of the gate wing portions 170-2 and 170-3 of the gate electrode 170 and the side portion 172A of the gate metal layer 172 are formed at the first angle? 1 ). ≪ / RTI > Here, the first angle [theta] 1 may be a positive number of 0 degrees or more.

BACKGROUND ART Generally, as a method for suppressing a leakage current of a GaN-based power semiconductor device, a floating gate, a field-modulating plate, an overlapping gate structure, a source extension field plate extended field palettes, and multiple field plates are being developed. For example, a field plate (not shown) is disposed to alleviate the electric field concentration at the edge of the gate electrode 170.

However, in the case of the power semiconductor device according to the embodiment, since the gate wings 170-2 and 170-3 of the gate electrode 170 serve as a field plate, it is not necessary to form a separate field plate. In this manner, the gate wing portions 170-2 and 170-3 serve as the field plates, so that the concentration of the electric field can be relaxed and the breakdown voltage of the power semiconductor device can be improved. That is, the electric field concentrated on the edge of the gate penetration portion 170-1 can be dispersed by the gate wing portions 170-2 and 170-3.

According to the embodiment, since the gate metal layer 172 is disposed so as to surround the gate electrode 170, the gate metal layer 172 adjacent to the gate wing portions 170-2 and 170-3 functions as a field plate May be further reinforced.

In general, the resistance R1 of the gate electrode 170 can be expressed by the following equation (1).

Where L represents the length of the gate electrode 170 and A represents the cross sectional area of the gate electrode 170. [

Generally, the gate electrode 170 is implemented as TiN. In this case, TiN is 20 Ω / sq, which is higher than other metal materials. As described above, when the resistance of the gate electrode 170 is high, the resistance at the end of the gate electrode 170 increases from several k [Omega] k to several hundred k [Omega]. This may require a lot of energy in driving the power semiconductor device and may increase the switching time required to switch the state between the turn-off and turn-on of the power semiconductor device .

However, according to the embodiment, the gate metal layer 172 is arranged to surround the gate electrode 170, and the total sum of the resistance R1 of the gate electrode 170 and the resistance R2 of the gate metal layer 172 (RT Is expressed by the following equation (2).

Referring to Equation 2, since the gate metal layer 172 having a lower resistance than the resistance of TiN is disposed on the gate electrode 170, the resistivity rho 'in Equation 2 is less than the resistivity rho in Equation 1 And the cross-sectional area A 'of the formula (2) becomes larger than the cross-sectional area (A) of the formula (1). Therefore, the total resistance (RT) of the resistors becomes smaller than the resistance (R1) when compared to when only the gate electrode 170 is disposed without the gate metal layer 172. As a result, the energy required for driving the power semiconductor device is reduced, and the switching time required for switching the state between turning-on and turning-on of the power semiconductor device can be reduced.

On the other hand, the contact electrodes 160 and 180 are disposed on the epi-layer 120 from the gate metal layer 172 in the horizontal direction, for example, in the y-axis direction. The contact electrodes 160 and 180 may include a source contact 160 and a drain contact 180. The source contact 160 is disposed above the epi layer 120 away from one side of the gate metal layer 172 and the drain contact 160 is disposed above the epi layer 120 away from the other side of the gate metal layer 172. The source contact 160 and the drain contact 180 may be in electrical contact with the epi layer 120 through the passivation layer 130.

Each of the source contact 160 and the drain contact 180 may include a contact penetration portion and a contact wing portion. For example, referring to FIG. 1, the source contact 160 may include a contact penetration portion 160-1 and contact wing portions 160-2 and 160-3. The contact penetration portion 160-1 penetrates the passivation layer 130 in the third direction and contacts the epi layer 120. The contact wing portions 160-2 and 160-3 contact the contact penetration portion 160-1, And extend in a fourth direction different from the third direction and may be disposed on the passivation layer 130. Here, the third direction may be the x-axis direction and the fourth direction may be perpendicular to each other as the y-axis direction, but the embodiment is not limited to this.

Each of the source contact 160 and the drain contact 180 may be formed of a metal. As described above, each of the source contact 160 and the drain contact 180 may comprise the same material as the gate metal layer 172 or the gate electrode 170 and may include other materials. The source and drain contacts 160 and 180 may be formed of a reflective electrode material having ohmic characteristics. For example, each of the source and drain contacts 160 and 180 includes at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu) Layer structure or a multi-layer structure. For example, each of source contact 160 and drain contact 180 may take the form of TiN stacked over Ti (172-3) illustrated in FIG.

1, the sides (e.g., 160-2B) of the contact wings (e.g., 160-2, 160-3) of the contact electrodes 160,180 are at a second angle (e.g., 2). Here, the second angle [theta] 2 may be a positive number of 0 degrees or more.

On the other hand, the power semiconductor device illustrated in FIG. 1 may further include the gate insulating layer 190, but the embodiment is not limited thereto. According to another embodiment, unlike that shown in FIG. 1, the power semiconductor device may not include the gate insulating layer 190.

1, the gate insulating layer 190 is formed between the gate electrode 170 and the epi layer 120, between the gate electrode 170 and the passivation layer 130, between the gate metal layer 172 and the passivation layer 130, Layer 130 as shown in FIG. Specifically, the gate insulating layer 190 is disposed between the bottom surface 170-1A of the gate penetration portion 170-1 and the top surface 120A of the epi layer 120, and the gate wing portions 170-2 and 170 3 and the upper surfaces 130A and 130B of the passivation layer 130 and the side surfaces 170-1B and 170-1B of the gate penetration portion 170-1 and the passivation layer 130. [ Layer 130 as shown in FIG.

The gate insulating layer 190 is made of Al ₂ O ₃ A silicon oxide layer such as SiO ₂ , or a silicon nitride layer, and may have a thickness of, for example, 100 Å to 300 Å, but the embodiments are not limited thereto.

Each of the source contact 160 and the drain contact 180 may also be in electrical contact with the epi layer 120 through the gate insulating layer 190 as well as the passivation layer 130.

The gate insulating layer 190 is disposed between the bottom surfaces 160-2A and 160-3A of the contact wing portions 160-2 and 160-3 and the top surfaces 130A and 130C of the passivation layer 130. [ At this time, the bottom faces 160-2A and 160-3A of the contact wing portions 160-2 and 160-3 may be disposed in direct contact with the upper surface of the gate insulating layer 190 in direct contact therewith. If the gate insulating layer 190 is omitted, the bottom faces 160-2A and 160-3A of the contact wing portions 160-2 and 160-3 are electrically connected to the upper faces 130A and 130C of the passivation layer 130, As shown in FIG.

The intermediate insulating layer 140 may be disposed while covering the upper portion 172B and the side portion 172A of the gate metal layer 172. [ The intermediate insulating layer 140 may include, but is not limited to, the same material as the passivation layer 130. For example, the intermediate insulating layer 140 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD.

The contact pads 152 and 154 are electrically connected to the source contact 160 and the drain contact 180 through the intermediate insulating layer 140, respectively. The contact pad includes source and drain pads 152 and 154 and may be formed by at least one of gold (Au), aluminum (Al), or copper (Cu) , 154).

Hereinafter, a method of manufacturing the power semiconductor device illustrated in FIG. 1 will be described with reference to FIGS. 4A to 4M attached hereto, but the embodiments are not limited thereto, and the power Needless to say, semiconductor devices can be manufactured.

4A to 4M are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, an epi layer 120 is formed on a substrate 110. The substrate 110 may be formed using silicon, silicon carbide, GaN, sapphire, or the like. The epitaxial layer 120 may be formed by sequentially laminating a transition layer 122, a buffer layer 124, and a barrier layer 126 on a substrate 110, as illustrated in FIG.

The transition layer 122 may be formed using aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like. The buffer layer 124 may be an undoped semiconductor layer.

The buffer layer 124 may be formed of a semiconductor compound, and may be formed of a compound semiconductor such as a group III-V element or a group II-VI element. For example, the buffer layer 124 may be formed using a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + . The buffer layer 124 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

The barrier layer 126 may be formed using a compound semiconductor such as a group III-V element or a group II-VI element. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) The barrier layer 126 may be formed of any one or more of AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

4B, etching is performed to remove the epi layer 120 of the element isolation region IA of the substrate 110 using a conventional photolithography process, but the embodiment is not limited thereto . For example, etching of the epi layer 120 may utilize dry etching. According to another embodiment, impurity ions may be implanted into the epi-layer 120 of the element isolation region without etching the epi layer 120 of the element isolation region of the substrate 110. [

Referring to FIG. 4C, the passivation layer 130 is formed on the side and the top of the epi layer 120 shown in FIG. 4B, but the embodiment is not limited thereto. For example, according to another embodiment, the passivation layer 130 may be formed only on the top of the epi layer 120. The passivation layer 130 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition (CVD) method, a PECVD method, an LPCVD method, a molecular beam epitaxy (MBE), an inductively coupled plasma chemical vapor deposition (Inductively Coupled Plasma Chemical Vapor Deposition (ICPCVD), Hydride Vapor Phase Epitaxy (HVPE), and the like. However, the present invention is not limited thereto.

4D, the passivation layer 130 is etched using a conventional photolithography process so that the gate insulating layer 190 is disposed and the gate penetration portion 170-1 of the gate electrode 170 is formed Thereby exposing the region 210 to be formed.

4E, the epi layer 120 includes the exposed region 210 to form the gate insulating layer 190 on the passivation layer 130B. According to another embodiment, the gate insulating layer 190 may be omitted. The gate insulating layer 190 may be formed to a thickness of, for example, 15 nm by an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, or the like, but the embodiment is not limited thereto. For example, the gate insulating layer 190 may be formed of aluminum oxide (Al ₂ O ₃ ) by atomic layer deposition.

Referring to FIG. 4F, a metal layer 170 is formed on the gate insulating layer 190, and then a photoresist pattern 220 is formed to cover the region where the gate electrode 170 is to be formed. The metal layer 170 may be formed using e-beam evaporation or a metal sputter. When the metal layer 170 is formed on the gate insulating layer 190 by the metal sputtering, the metal layer 170 can be formed more easily than by the electron beam evaporation method. After the metal layer 170 is formed, a subsequent heat treatment may be performed. For example, rapid thermal annealing may be performed at 400 ° C for 10 minutes. Here, the metal layer 170 may be a refractory metal or a mixture of such refractory metals. Alternatively, the metal layer 170 may include at least one of Ta, Tantalum, TiN, Pd, W, or WSi ₂ .

4G, the gate electrode 170 is formed by etching the metal layer 170 using an inductively coupled plasma (ICP) etching method using the photoresist pattern 220 as an etching mask. Then, the photoresist pattern 220 is removed by ashing and / or stripping.

Since the passivation layer 130 is etched instead of the epi layer 120 after the gate insulating layer 190 is etched while the metal layer 170 is etched using the photoresist pattern 220 as an etch mask, (120) may be protected from etching of the metal layer (170). Thus, the passivation layer 130 serves as an etch stop layer for protecting the epi layer 120, particularly, the barrier layer 126 from the etching of the metal layer 170.

4H, a photoresist pattern 230 exposing the source contact 160 and the regions 211 and 212 where the drain contact 180 is to be formed is electrically connected to the gate electrode 170 and the gate insulating layer 190, .

4I, the gate insulating layer 190 and the passivation layer 130 of the exposed regions 211 and 212 are etched using the photoresist pattern 230 as an etching mask. At this point, some of the epi layer 120, for example, the barrier layer 126 may be more etched, but embodiments are not limited to such etch depth. For example, the barrier layer 126 of the epi layer 120 can be etched to 150 ANGSTROM. Thereafter, the photoresist pattern 230 is removed.

Referring to FIG. 4J, a metal layer 240 is formed on the exposed epi layer 120, the gate electrode 170, and the gate insulating layer 170. Here, the metal layer 240 may be formed as a single layer or a multilayer structure including at least one of aluminum (Al), titanium (Ti), chrome (Cr), nickel (Ni), copper have. Thereafter, photoresist patterns 250-1 and 250-2 covering the regions where the contact electrodes 160 and 180 are to be formed are formed on the metal layer 240. Then, Particularly, according to the embodiment, the photoresist pattern 250-3 covering the region where the gate metal layer 172 is to be formed is formed on the metal layer 240. [

Referring to FIG. 4K, the metal layer 240 is etched by, for example, inductively coupled plasma (ICP) etching using the photoresist patterns 250-1, 250-2, and 250-3 as etching masks. So that the contact electrodes 160 and 180 and the gate metal layer 172 are simultaneously formed. After the contact electrodes 160 and 180 are formed, a heat treatment is performed at a temperature of 700 ° C for the ohmic characteristics of the contact electrodes 160 and 180. Thereafter, the photoresist patterns 250-1, 250-2, and 250-3 are removed.

5A to 5D show a process sectional view of a power semiconductor device in another embodiment.

After forming the gate electrode 170 as shown in Fig. 4G, instead of forming the contact electrodes 160 and 180 using the process shown in Figs. 4H to 4K, The source contact 360 and the drain contact 380, which are contact electrodes, can be formed.

That is, referring to FIG. 5A, a first intermediate insulating layer 310 is formed on the gate electrode 170 and the gate insulating layer 190 shown in FIG. 4G. The first intermediate insulating layer 310 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, and SOD. A photoresist pattern 320 is then formed on the first intermediate insulating layer 310 to expose regions 332 and 334 where the source contact 360 and the drain contact 380 are to be formed.

5B, the barrier layer of the first intermediate insulating layer 310, the gate insulating layer 190, the passivation layer 130, and the epi layer 120 is patterned using the photoresist pattern 320 as an etching mask. The layer 126 is etched to expose the epi layer 120. Thereafter, the photoresist pattern 320 is removed.

Referring to FIG. 5C, a metal layer 340 is formed on the exposed epi layer 120 and the first intermediate insulating layer 310. Thereafter, a photoresist pattern 350 is formed on the metal layer 340 so as to cover the regions where the source contact 360 and the drain contact 380 are to be formed.

5D, the source and drain contacts 360 and 380 are formed by etching the metal layer 340 using the photoresist pattern 350 as an etching mask. Thereafter, the photoresist pattern 350 is removed.

5D, the first intermediate insulating layer 310 protects the gate electrode 170 from etching the metal layer 340 to form the contact electrodes 360 and 380 . However, after forming the source contact 360 and the drain contact 380, as shown in Figure 5d, during the heat treatment at a temperature of about 700 ° C to improve the ohmic characteristics of these (360, 380) The material of the power semiconductor element may be deteriorated due to a material change in the first intermediate insulating layer 310 and a leakage current may be generated. If a leakage current occurs, it may be difficult to implement a power semiconductor device having a desired breakdown voltage.

However, as shown in FIGS. 4H to 4K, when forming the contact electrodes 160 and 180, the first intermediate insulating layer 310 is unnecessary. Accordingly, since the first intermediate insulating layer 310 to be deformed in the heat treatment process is not present after the contact electrodes 160 and 180 are formed as shown in FIG. 4K, the leakage current is prevented from being generated, May be realized.

In addition, when the contact electrodes 160 and 180 are formed as illustrated in FIGS. 4H to 4K, since it is not necessary to form the first intermediate insulating layer 310 as illustrated in FIGS. 5A to 5D, The process can be simplified, and the manufacturing cost can be reduced.

4L, a second intermediate insulating layer 140 is formed on the contact electrodes 160 and 180, the gate electrode 170, and the gate insulating layer 190. Next, as shown in FIG. The second intermediate insulating layer 140 may be formed of the same material as the passivation layer 130, but the present invention is not limited thereto. The second intermediate insulating layer 140 may include at least one of SiN _x , MgO, Sc ₂ O ₃ , SiO ₂ , SOG, or SOD. The photoresist pattern 260 exposing the second intermediate insulating layer 140 regions 215 and 216 of the upper portions 160A and 180A of the contact electrodes 160 and 180 to be contacted with the contact pads 152 and 154 is then removed, .

Referring to FIG. 4M, the upper surfaces 160A and 180A of the contact electrodes 160 and 180 are exposed by etching the second intermediate insulating layer 140 using the photoresist pattern 260 as an etching mask , The photoresist pattern 260 is removed. A metal layer 150 is then formed on the upper surfaces 160A and 180A of the exposed contact electrodes 160 and 180 and the second intermediate insulating layer 140. Thereafter, a photoresist pattern 270 is formed on the metal layer 150 to cover the areas where the contact pads 152 and 154 are to be disposed. Thereafter, the metal layer 150 is etched using the photoresist pattern 270 as an etching mask to form the contact pads 152 and 154. Thereafter, the photoresist pattern 270 is removed to complete the power semiconductor device illustrated in FIG.

Although the photolithography process has been described as an example of the etching process in the above-described embodiments, the present invention is not limited thereto. It is needless to say that the etching process can also be performed by the e-bem lithography method or the nano-imprinted lithography method.

Hereinafter, the magnitude of the leakage current when the power semiconductor device includes the first intermediate insulating layer 310 and the case where the power semiconductor device includes the first intermediate insulating layer 310 will be described as follows.

FIG. 6 is a graph showing leakage currents when the power semiconductor device includes the first intermediate insulating layer 310 (410) and not (420). Here, the horizontal axis represents the drain voltage (V), and the vertical axis represents the leakage current (Leakage current).

Referring to FIG. 6, when a power semiconductor device includes a first intermediate insulating layer 310, a material change is caused in the first intermediate insulating layer 310 to cause a leakage current generated in the power semiconductor device to be large .

However, it can be seen that when the power semiconductor device does not include the first intermediate insulating layer 310 (420), the leakage current generated in the power semiconductor device decreases (430). As a result, a power semiconductor device having a desired breakdown voltage can be realized.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

110: substrate 120: epi layer
122: transition layer 124: buffer layer
126: barrier layer 130: passivation layer
140: intermediate insulating layer (or second intermediate insulating layer)
152, 154: contact pad 160, 180: contact electrode
170: gate electrode 172: gate metal layer
310: first intermediate insulating layer 340: metal layer
360: source contact 380: drain contact

Claims (12)

Board;
An epi layer disposed on the substrate;
A passivation layer disposed over the epilayer;
A gate electrode disposed on the epi layer through the passivation layer;
A gate metal layer on top and sides of the gate electrode; And
And a contact electrode spaced from the gate metal layer and disposed over the epi layer. The semiconductor device according to claim 1, further comprising a gate insulating layer disposed between the gate electrode and the epi layer, between the gate electrode and the passivation layer, and between the gate metal layer and the passivation layer . The semiconductor device according to claim 1 or 2, wherein the gate electrode
A gate penetrating portion penetrating the passivation layer in a first direction; And
And a gate wing portion extending from the gate penetration portion in a second direction different from the first direction and disposed on the passivation layer. The semiconductor device according to claim 3, wherein the gate insulating layer
And between the bottom surface of the gate penetrating portion and the top surface of the epi layer, between the bottom surface of the gate vane portion and the top surface of the passivation layer, and between the side surface of the gate penetrating portion and the passivation layer. 3. The device of claim 2, wherein the contact electrode
A contact penetration portion penetrating the passivation layer and contacting the epi layer; And
And a contact wing portion extending from the contact penetration portion and disposed on the passivation layer. The power semiconductor element according to claim 5, wherein a bottom surface of the contact wing portion is in direct contact with an upper surface of the passivation layer or an upper surface of the gate insulating layer. The power semiconductor device according to claim 1,
An intermediate insulating layer disposed above and below the gate metal layer; And
And a contact pad electrically connected to the contact electrode through the intermediate insulating layer. 2. The power semiconductor device of claim 1, wherein the gate metal layer and the contact electrode comprise the same material. The power semiconductor device of claim 1, wherein the gate metal layer comprises a material having a resistance lower than the resistance of TiN. The method according to claim 1, wherein the gate metal layer comprises at least one of aluminum (Al), titanium (Ti), chrome (Cr), nickel (Ni), copper (Cu), and gold Power semiconductor device. The power semiconductor device according to claim 1, wherein the thickness of the gate metal layer is equal to the thickness of the contact electrode. The power semiconductor device according to claim 1, wherein the thickness of the gate metal layer is 2000 Å to 4000 Å.

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