JP2009302388A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize a current leaking from an element region in a semiconductor device having a hetero-junction. <P>SOLUTION: A semiconductor device 100 has a semiconductor multilayer portion 11 where nitride semiconductor layers 6 and 10 having different band gaps are laminated, and the semiconductor multilayer portion 11 has an element region 100a and an element isolation region 100b formed around the element region 100a. The element region 100a is isolated from other regions by the element isolation region 100b. A step of manufacturing the semiconductor device 100 includes a step of forming a pair of electrode groups 24 and 16 which are connected with a main electrode on the surface of the semiconductor multilayer portion 11 in the element region 100a, and a step of forming a sputter layer 12 on the surface of the semiconductor multilayer portion 11 in the element isolation region 100b by using a sputtering method. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a semiconductor stacked portion in which at least two types of nitride semiconductor layers having different band gaps are stacked. The present invention also relates to a method for manufacturing the semiconductor device.

  2. Description of the Related Art A semiconductor device has been developed that uses two types of nitride semiconductor layers that have different band gaps and that uses a two-dimensional electron gas layer induced on the heterojunction surface. An example of the semiconductor device is disclosed in Non-Patent Document 1. On the surface of the semiconductor stacked portion, an electrode group (source electrode, drain electrode, gate electrode, etc.) of the switching element is formed. Electrons injected from the source electrode pass through the two-dimensional electron gas layer on the heterojunction surface and reach the drain electrode. A gate electrode is formed between the source electrode and the drain electrode, and is turned on / off by a voltage applied to the gate electrode.

“Current Status and Prospects of High-Power AlGaN / GaN Heterojunction FETs” IEICE Transactions C Vol. J86-C No. 4 pp. 396-403 April 2003

In this type of semiconductor device, it is necessary to form an element isolation region around the element region and insulate the element region from the surrounding region. If insulation in the element isolation region is not ensured, the current flowing between the drain electrode and the source electrode leaks to the surrounding region beyond the element isolation region. In order to realize a structure in which the semiconductor stacked portion is formed in the insulating element isolation region, conventionally, the semiconductor stacked portion is formed only in a region inside the insulating element isolation region. This method requires a number of steps, and a simpler manufacturing method is required.
It is only necessary to form a semiconductor stacked portion extending between the element region and the element isolation region and then insulate the semiconductor stacked portion in the element isolation region, but an effective method for insulating has not been developed. If impurities are ion-implanted into a part of the semiconductor stacked portion, the crystal structure of the semiconductor stacked portion in the ion-implanted range is broken and insulated. However, the broken crystal structure may be recovered by a process such as a heat treatment, which is not sufficient. The semiconductor stack in the element isolation region cannot be reliably insulated.

  According to the present invention, in a semiconductor device having a semiconductor stacked portion in which at least two types of nitride semiconductor layers having different band gaps are stacked, the semiconductor stacked portion in the element isolation region is insulated and current leaks from the element region. A semiconductor device manufacturing method capable of suppressing this and a semiconductor device that can be manufactured by the manufacturing method are realized.

  The technique disclosed in this specification is characterized by using a sputtering method. In the technique disclosed in this specification, a sputter layer is formed on the surface of the semiconductor stacked portion in the element isolation region using a sputtering method. When a sputter layer is formed on the surface of a semiconductor laminated portion where at least two types of nitride semiconductor layers having different band gaps are laminated using a sputtering method, the crystal structure of the semiconductor laminated portion is broken, and the heterogeneity of the semiconductor laminated portion is reduced. The conductivity of the joint surface can be deteriorated. In the technology disclosed in this specification. By selectively forming a sputter layer on the surface of the semiconductor stack in the element isolation region, current leakage from the element region is suppressed.

  The manufacturing method disclosed in this specification is used for a semiconductor device having a semiconductor stacked portion in which at least two types of nitride semiconductor layers having different band gaps are stacked. The semiconductor stacked portion includes an element region and an element isolation region that is formed around the element region and insulates the element region from other regions. The manufacturing method disclosed in this specification includes an electrode group forming step and a sputtering step. In the electrode group forming step, an electrode group of the switching element is formed on the surface of the semiconductor stacked portion in the element region. In the sputtering step, a sputter layer is formed on the surface of the semiconductor stacked portion in the element isolation region by using a sputtering method. The order in which the “electrode group forming step” and the “sputtering step” are performed is arbitrary. That is, the “sputtering process” may be performed prior to the “electrode group forming process”, or the “sputtering process” may be performed after the “electrode group forming process”.

When the “sputtering process” is performed after the “electrode group forming process”, the semiconductor laminated part is formed on the surface of the semiconductor laminated part in the element region not covered with the electrode group prior to the sputtering process rather than by the sputtering method. A step of forming a base insulating layer by a method with a low degree of damage is added, and in the sputtering step, the surface of the semiconductor stack in the element isolation region, the surface of the electrode group, and the surface of the base insulating layer, It is preferable that a step of forming a wiring group that reaches the electrode group through the insulating layer formed by the sputtering process by sputtering the insulating material is added.
Examples of the “method in which the degree of damage to the semiconductor stacked portion is lower than that of the sputtering method” include a CVD method and an EB vapor deposition method.

  The sputtered layer formed by the sputtering process is also used to electrically insulate the electrode group of the switching element on the surface of the semiconductor stacked portion. That is, according to the manufacturing method, it is possible to simultaneously suppress leakage current from the element region and insulate and separate the electrode group of the switching element. Since the sputtered layer does not contact the surface of the semiconductor stacked portion in the element region, the crystal structure of the semiconductor stacked portion in the element region is not broken.

  The semiconductor device disclosed in this specification has a semiconductor stacked portion in which at least two types of nitride semiconductor layers having different band gaps are stacked, and the semiconductor stacked portion is disposed around the element region and the element region. An element isolation region that is formed and insulates the element region from other regions is provided. An electrode group of the switching element is formed on the surface of the semiconductor stacked portion in the element region. The semiconductor stacked portion in the element isolation region is modified into an insulating layer by damage caused by sputtering.

  By forming a sputter layer on the surface of the semiconductor stacked portion in the element isolation region using a sputtering method, current leakage from the element region can be suppressed. In addition, it is possible to easily manufacture a structure in which a conductive semiconductor stacked portion is formed only in an insulating element isolation region.

(First embodiment)
FIG. 1 is a cross-sectional view of a main part of the semiconductor device 100. FIG. 2 shows a plan view of the semiconductor device 100. 1 is a longitudinal sectional view corresponding to the line II in FIG. As shown in FIG. 1, the semiconductor device 100 is a horizontal semiconductor device, and electrode groups 16, 20, and 24 are provided on the surface of the semiconductor stacked portion 11. The semiconductor stacked unit 11 includes nitride semiconductor layers 6 and 10 having different band gaps. The electrodes 16, 20, and 24 extend in a stripe shape in the depth direction of FIG. 1 (see also FIG. 2). The element region 100a is surrounded by the element isolation region 100b. In the element isolation region 100 b, the sputter layer 12 is in contact with the surface of the semiconductor stacked portion 11. In the element region 100 a, the sputter layer 12 is not in contact with the surface of the semiconductor stacked portion 11. In the element region 100 a, electrodes 16, 20, 24 or an insulating film (underlying insulating layer) 18 are interposed between the sputtered layer 12 and the semiconductor stacked portion 11. Hereinafter, the form of the semiconductor device 100 will be described in detail from the back side.

A buffer layer 4 made of aluminum nitride (AlN) is provided on the surface of a sapphire substrate 2 made of sapphire. As will be described later, the sapphire substrate 2 is an underlayer for crystal growth of the semiconductor stacked portion 11. Therefore, the material used for the sapphire substrate 2 can use, for example, silicon carbide (SiC), gallium nitride (GaN), silicon (Si), or the like instead of sapphire. A first nitride semiconductor layer 6 made of gallium nitride is provided on the surface of the buffer layer 4. The first nitride semiconductor layer 6 does not contain impurities. A second nitride semiconductor layer 10 made of gallium nitride / aluminum (Al _0.25 Ga _0.75 N) is provided on the surface of the first nitride semiconductor layer 6. The second nitride semiconductor layer 10 also contains no impurities. The thickness of the second nitride semiconductor layer 10 is 15 nm or less. The second nitride semiconductor layer 10 is stacked on the surface of the first nitride semiconductor layer 6 to form the semiconductor stacked portion 11. In addition, the range of the code | symbol 8 of the semiconductor laminated part 11 has shown the range where the crystallinity of the semiconductor laminated part 11 is lower than another range. As will be described later, the range of the reference numeral 8 of the semiconductor stacked portion 11 is a range in which a part of the semiconductor stacked portion 11 is modified into an insulating layer due to damage caused by sputtering. In the following description, the range of 8 is referred to as an insulating region 8. The insulating region 8 is formed from the surface of the semiconductor stacked portion 11 to the deep portion beyond the heterojunction surface. The insulating region 8 makes a round around the element region 100a and corresponds to the element isolation region 100b.

A source electrode 24 and a drain electrode 16 made of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) are provided on the surface of the semiconductor stacked portion 11. The source electrode 24 is connected to the low potential of the power supply via the source wiring 22. The drain electrode 16 is connected to the high potential of the power supply via the drain wiring 14. The material of the source wiring 22 and the drain wiring 14 is titanium and aluminum. The semiconductor device 100 is a horizontal switching element because both of the pair of electrodes 24 and 16 connected to the main power source are formed on the surface of the semiconductor stacked portion 11. A gate electrode 20 made of nickel and gold is provided on the surface of the semiconductor stacked portion 11 between the source electrode 24 and the drain electrode 16. The gate electrode 20 is in Schottky contact with the second nitride semiconductor layer 10. The gate electrode 20 is connected to a control power supply via a gate wiring (not shown). The gate electrode 20 may be made of platinum and gold.
The source electrode 24, the drain electrode 16 and the gate electrode 20 are separated from each other, and the respective electrodes 24, 16 and 20 are electrically separated by the sputter layer 12. The source wiring 22, the drain wiring 14, and the gate wiring described above penetrate the sputter layer 12 and reach the source electrode 24, the drain electrode 16, and the gate electrode 20, respectively. The sputter layer 12 is a silicon oxide (SiO) film formed by a sputtering method. The sputter layer 12 is formed on the surface of the semiconductor stacked portion 11 in the element isolation region 100b, but is formed on the surface of the electrodes 24, 16, 20 or the insulating film (underlying insulating layer) 18 in the element region 100a. Yes. The insulating film 18 is a silicon nitride (SiN) film formed by a CVD (Metal Organic Chemical Vapor Deposition) method.

  As described above, the semiconductor stacked portion 11 includes the first nitride semiconductor layer 6 made of gallium nitride and the second nitride semiconductor layer 10 made of gallium nitride / aluminum. Since gallium nitride and gallium nitride / aluminum have different band gap widths, a two-dimensional electron gas layer is formed on the heterojunction surface between them. However, since the crystal structure of the first nitride semiconductor layer 6 and the second nitride semiconductor layer 10 is broken in the insulating region 8, a two-dimensional electron gas layer is hardly formed between them.

  In the semiconductor device 100, electrons injected from the source electrode 24 into the semiconductor stacked portion 11 pass through the two-dimensional electron gas layer and reach the drain electrode 16. That is, electrons can move through the semiconductor stacked portion 11 in the element region 100a. However, since the semiconductor stacked portion 11 in the element region 100a is surrounded by the insulating region 8, electrons cannot move out of the element region 100a. In the semiconductor device 100, it is difficult for current to leak from the element region 100a.

A method for manufacturing the semiconductor device 100 will be described with reference to FIGS.
First, as shown in FIG. 3, the buffer layer 4 is crystal-grown on the sapphire substrate 2. Thereafter, the first nitride semiconductor layer 6 is crystal-grown on the buffer layer 4, and the second nitride semiconductor layer 10 is crystal-grown on the first nitride semiconductor layer 6. The buffer layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 10 are crystal-grown using the MOCVD method. The buffer layer 4 is crystal-grown at a lower temperature than when the first nitride semiconductor layer 6 and the second nitride semiconductor layer 10 are crystal-grown. The lattice mismatch between the sapphire substrate 2 and the first nitride semiconductor layer 6 can be relaxed, and the first nitride semiconductor layer 6 can be favorably crystal-grown.

Next, as shown in FIG. 4, a photoresist mask 26 having an opening 26a and a mask layer (insulating film) 18 having an opening 18a are formed on the surface of the second nitride semiconductor layer 10 using a photolithography process. . The material of the mask layer 18 is silicon nitride (SiN), and is formed using a CVD method. The opening 18a is formed by etching the mask layer 18 with buffered hydrofluoric acid (B-HF). Next, as shown in FIG. 5, the source electrode 24 and the drain electrode 16 are formed on the surface of the second nitride semiconductor layer 10 exposed in FIG. 4 using a lift-off method (electrode group forming step).
Next, as shown in FIG. 6, a photoresist mask 28 having an opening 28 a is formed by using a photolithography process, and an opening 18 b is formed in the mask layer 18. The opening 18 b is formed between the source electrode 24 and the drain electrode 16. Next, as shown in FIG. 7, the gate electrode 20 is formed on the surface of the second nitride semiconductor layer 10 exposed in FIG. 6 by using a lift-off method. The gate electrode 20 is formed between the source electrode 24 and the drain electrode 16.

Next, as shown in FIG. 8, an opening 18 c is formed in the surface of the second nitride semiconductor layer 10. The opening 18c is formed by forming a resist mask using a photolithography process and removing a part of the insulating film 18 with buffered hydrofluoric acid. The insulating film 18 is formed on the surface of the semiconductor stacked portion 11 in the element region 100a not covered with the electrode groups 24, 16 and 20. The opening 18c is formed at a position corresponding to the element isolation region 100b.
Next, as shown in FIG. 9, a sputter layer 12 is formed on the surface of the semiconductor stacked portion 11 using a sputtering method (sputtering process). In the sputtering process, the sputtered layer 12 is formed on the surface of the semiconductor stacked portion 11 in the element isolation region 100b, the surfaces of the electrodes 24, 16 and 20, and the surface of the insulating film 18. As described above, since the material of the sputter layer 12 is silicon oxide, each of the electrodes 24, 16 and 20 is electrically insulated by the sputter layer 12.
Thereafter, a contact hole is formed in the sputter layer 12 on the source electrode 24 to connect the source electrode 24 and the source wiring 22. A contact hole is formed in the sputter layer 12 on the drain electrode 16 to connect the drain electrode 16 and the drain wiring 14. A contact hole is formed in the sputtered layer 12 on the gate electrode 20 to connect the gate electrode 20 and the gate wiring. Through the above steps, the semiconductor device 100 of FIG. 1 is obtained.

  When a sputter layer is formed on the nitride semiconductor layer using a sputtering method, the crystal structure of the nitride semiconductor layer is destroyed due to damage caused by the sputtering method. Therefore, the crystal structure of the semiconductor stacked portion 11 in the element isolation region 100b is broken, and the conductivity of the insulating region 8 is deteriorated. However, the crystal structure of the semiconductor stacked portion 11 in the element region 100a is not broken. As described above, in this manufacturing method, the sputtering method is used only when the sputter layer 12 is formed. When the sputter layer 12 is formed, the source electrode 24, the drain electrode 16, the gate electrode 20, or the insulating film 18 is formed on the surface of the semiconductor stacked portion 11 in the element region 100a. Therefore, the sputter layer 12 does not directly contact the surface of the semiconductor stacked portion 11 in the element region 100a. The mask layers 26 and 28 and the insulating film 18 are formed using a CVD method. Even if a mask layer or an insulating film is formed on the nitride semiconductor layer by CVD, the crystal structure of the nitride semiconductor layer is not destroyed. Therefore, the conductivity of the semiconductor stacked portion 11 in the element region 100a does not deteriorate.

(Second Embodiment)
FIG. 10 is a cross-sectional view of the main part of the semiconductor device 200. In the semiconductor device 200, the gate electrode 220 faces the second nitride semiconductor layer 10 with the insulating film 18 interposed therebetween. By adjusting the thickness of the insulating film 18, the threshold voltage of the semiconductor device 200 can be adjusted. Note that the material of the gate electrode 220 is preferably aluminum, platinum (Pt), or polycrystalline silicon.

(Example 1)
A semiconductor laminated portion 11 in which a gallium nitride / aluminum (Al _0.25 Ga _0.75 N) layer 10 is crystal-grown on the surface of the gallium nitride layer 6 is prepared, and silicon oxide (sputtering method) is formed on the semiconductor laminated portion 11. A sample (Example 1) on which a (SiO) film was formed was prepared. The sample was subjected to cathodoluminescence measurement (hereinafter CL measurement). The thickness of the gallium nitride / aluminum layer 10 is 15 nm. Further, as Comparative Example 1, CL measurement was also performed on a sample having only the semiconductor stacked portion 11.
FIG. 11 shows the measurement result of the CL intensity of the gallium nitride / aluminum layer 10, the curve 34 shows the measurement result of Example 1, and the curve 32 shows the measurement result of Comparative Example 1. FIG. 12 shows the measurement result of the CL intensity of the gallium nitride layer 6, the curve 38 shows the measurement result of Example 1, and the curve 36 shows the measurement result of Comparative Example 1. The horizontal axis of the graph indicates the measurement wavelength (nm), and the vertical axis indicates the CL intensity.

  As shown in FIG. 11, the sample of Comparative Example 1 shows a peak of CL intensity near the wavelength of 325 nm (curve 32). This indicates that the crystallinity of the gallium nitride / aluminum layer 10 is high. On the other hand, the sample of Example 1 does not have a CL intensity peak near the wavelength of 325 nm (curve 34). This indicates that the crystallinity of the gallium nitride / aluminum layer 10 is low. That is, the crystal structure of the gallium nitride / ammonium layer 10 is broken.

As shown in FIG. 12, in the gallium nitride layer 6, both the sample of Example 1 (curve 38) and the sample of Comparative Example 1 (curve 36) show a peak in CL intensity near a wavelength of 360 nm. However, the CL intensity of the curve 38 is smaller than the CL intensity of the curve 36. This indicates that the sample of Example 1 has lower crystallinity of gallium nitride than the sample of Comparative Example 1.
From the results of this example, it was confirmed that when a silicon oxide film was formed on the semiconductor multilayer portion 11 by sputtering, the crystallinity of the semiconductor multilayer portion 11 was lowered. In other words, it was confirmed that when a sputtered film is formed on the semiconductor multilayer portion 11 using the sputtering method, the semiconductor multilayer portion 11 is modified into an insulating layer due to damage caused by the sputtering method. In the semiconductor devices 100 and 200, since the insulating region 8 is formed in the element isolation region 100b, current leakage from the element region 100a is suppressed.

(Example 2)
A semiconductor laminated portion 11 in which a gallium nitride / aluminum (Al _0.25 Ga _0.75 N) layer 10 is crystal-grown on the surface of the gallium nitride layer 6 is prepared, and silicon oxide (sputtering method) is formed on the semiconductor laminated portion 11. A sample (Example 2) on which a (SiO) film was formed was prepared. The sample was subjected to Hall measurement.
As Comparative Example 2, Hall measurement was also performed on a sample having only the semiconductor stacked portion 11. In this example, the experiment was performed by changing the thickness of the gallium nitride / aluminum layer 10 to two conditions (15 nm and 25 nm). Table 1 shows the results.

As shown in Table 1, when a silicon oxide film is formed on the semiconductor stacked portion 11, the sheet carrier density decreases, the carrier (electron) mobility decreases, and the sheet resistance increases. That is, it becomes difficult for a current to flow through the semiconductor stacked portion 11. The same result was obtained even when the thickness of the gallium nitride / aluminum layer 10 was changed. It was confirmed that the crystallinity of the insulating region 8 can be reduced even when the thickness of the gallium nitride / aluminum layer 10 is 25 nm.
In the semiconductor devices 100 and 200, the silicon oxide film 12 is formed on the surface of the semiconductor stacked portion 11 in the element isolation region 100b by sputtering. In the semiconductor devices 100 and 200, the element isolation region 100b surrounds the element region 100a. From the results of this example, it was confirmed that the semiconductor devices 100 and 200 were suppressed from leaking current from the element region 100a.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1 is a longitudinal sectional view of a semiconductor device according to a first embodiment. 1 is a plan view of a semiconductor device according to a first embodiment. 1 shows a manufacturing process of a semiconductor device of a first embodiment. 1 shows a manufacturing process of a semiconductor device of a first embodiment. 1 shows a manufacturing process of a semiconductor device of a first embodiment. 1 shows a manufacturing process of a semiconductor device of a first embodiment. 1 shows a manufacturing process of a semiconductor device of a first embodiment. 1 shows a manufacturing process of a semiconductor device of a first embodiment. 1 shows a manufacturing process of a semiconductor device of a first embodiment. The longitudinal cross-sectional view of the semiconductor device of 2nd Embodiment is shown. The CL measurement result of a gallium nitride aluminum layer is shown. The CL measurement result of a gallium nitride layer is shown.

Explanation of symbols

8: Insulation region (insulation layer)
11: Semiconductor laminated portion 12: Sputtered layer 14: Drain wiring 16: Drain electrode 18: Insulating film (underlying insulating layer)
20: gate electrode 22: source wiring 24: source electrode 100, 200: semiconductor device 100a: element region 100b: element isolation region

Claims (3)

It has a semiconductor laminated portion in which at least two types of nitride semiconductor layers having different band gaps are laminated, and the semiconductor laminated portion is formed around the element region and the element region. A method of manufacturing a semiconductor device having an element isolation region that is insulated from the region of
An electrode group forming step of forming an electrode group of a switching element on the surface of the semiconductor laminate in the element region;
A sputtering step of forming a sputter layer on the surface of the semiconductor laminated portion in the element isolation region using a sputtering method;
A method for manufacturing a semiconductor device, comprising: A step of forming a base insulating layer on the surface of the semiconductor multilayer portion in the element region not covered with the electrode group by a method having a lower degree of damage to the semiconductor multilayer portion than in the case of sputtering is added,
In the sputtering step, an insulating material is sputtered on the surface of the semiconductor stack in the element isolation region, the surface of the electrode group, and the surface of the base insulating layer,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a wiring group that penetrates through the insulating layer formed in the sputtering step and reaches the electrode group. It has a semiconductor laminated portion in which at least two types of nitride semiconductor layers having different band gaps are laminated, and the semiconductor laminated portion is formed around the element region and the element region. A semiconductor device including an element isolation region that is insulated from the region of
The electrode group of the switching element is formed on the surface of the semiconductor stacked portion in the element region,
A semiconductor device, wherein a semiconductor laminated portion in the element isolation region is modified into an insulating layer by damage caused by sputtering.

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