JP2007180330A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a small leakage current. <P>SOLUTION: A HEMT according to this invention has a substrate 1 comprising a silicon, a semiconductor region 2 comprising a nitride semiconductor, a source electrode 3, a drain electrode 4, and a gate electrode 5. The sunbstrate 1 has a groove 9, and an insulating region 8 comprising a silicon oxide is provided in the groove 9. The insulating region 8 is arranged between first and second parts 10, 11 of the substrate 1 facing to the electrode 3 and the electrode 4 to suppress the leakage current in the substrate 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a field effect transistor and a Schottky barrier diode with small leakage current, and a method for manufacturing the same.

  A nitride semiconductor device such as a high electron mobility transistor (HEMT) using a silicon substrate is known from, for example, International Publication WO2005 / 015642 A1 (hereinafter referred to as Patent Document 1). The silicon substrate not only has a lower material cost than a sapphire substrate, but also has excellent workability, so that the cost of the nitride semiconductor device can be reduced.

  However, since the difference in thermal expansion coefficient between the silicon substrate and the nitride semiconductor is large, it is difficult to form a thick nitride semiconductor region on the silicon substrate with no or few cracks. The thickness of the region is at most about 2 to 3 μm. When, for example, a HEMT is configured as the nitride semiconductor device, the distance between the source electrode and the drain electrode is usually determined to be about 10 to 20 μm. For this reason, since the thickness of the nitride semiconductor region is significantly smaller than the distance between the drain electrode and the source electrode, the resistance in the thickness direction of the nitride semiconductor region is so small that it can be ignored. As a result, the drain electrode and the source electrode are electrically connected to both ends of the electron transit layer in the nitride semiconductor region and are also electrically connected to both ends of the silicon substrate. Since the resistance value of the electron transit layer is extremely small and the voltage between the drain electrode and the source electrode is low when the HEMT is turned on, the voltage applied across the silicon substrate is also low, and the current flowing through the silicon substrate ( The reactive current or leakage current is also negligibly small. On the other hand, when the HEMT is turned off, a depletion layer is generated in the electron transit layer based on the gate voltage applied to the gate electrode formed between the drain electrode and the source electrode. Current flowing in the lateral direction is blocked or suppressed. As a result, the current flowing in the lateral direction in the electron transit layer when the HEMT is turned off has a smaller value than the current component flowing in the silicon substrate through the longitudinal direction of the electron transit layer. The current component that flows through the silicon substrate during the off operation of the HEMT is a leakage current of the HEMT, which degrades the electrical characteristics of the HEMT. In a semiconductor device such as a HEMT, the breakdown voltage is generally determined on the basis of the magnitude of the leakage current. Therefore, if the leakage current is large, the breakdown voltage of the semiconductor device is inevitably lowered.

  Increasing the resistivity of the silicon substrate reduces the leakage current flowing through the silicon substrate. However, since silicon is a semiconductor, it is difficult to form a silicon substrate so as to have an insulating property equivalent to that of an insulating substrate.

  As a method for reducing leakage current flowing in a silicon substrate, Patent Document 1 discloses disposing a buffer region including a pn junction between a nitride semiconductor layer for forming a semiconductor element and the silicon substrate. However, if an impurity is added to the buffer region to form a pn junction in the buffer region, the impurity in the buffer region causes a decrease in the crystal quality of the nitride semiconductor formed thereon. Reduce the electron mobility in the layer. This makes it difficult to repeatedly form a semiconductor device (for example, HEMT) having the same characteristics with high reproducibility.

As another method for suppressing the leakage current, an inactive layer is formed by implanting oxygen ions on the surface of the semiconductor substrate, and a semiconductor layer such as GaAs or AlGaAs for a semiconductor element is formed on the inactive layer. The formation is disclosed in Japanese Patent Laid-Open No. 01-302742 (hereinafter referred to as Patent Document 2). The inactive layer of Patent Document 2 has an effect of suppressing leakage current, but it becomes difficult to satisfactorily epitaxially grow a semiconductor layer for a semiconductor element on the inactive layer. Further, when the semiconductor substrate is a silicon substrate, even if oxygen ions are implanted here, only an inactive layer having a resistivity of about 10 ⁶ Ωcm can be obtained, and a sufficient effect of suppressing leakage current can be obtained. I can't.

Although the HEMT has been described above, other semiconductor devices such as MESFETs, insulated gate FETs, and Schottky barrier diodes other than the HEMT have the same leakage current problem as the HEMT.
International Publication WO 2005/015642 A1 Japanese Patent Laid-Open No. 01-302742

  The problem to be solved by the present invention is that it is difficult to reduce the leakage current of a semiconductor device using a conductive substrate. Accordingly, an object of the present invention is to provide a semiconductor device capable of relatively easily achieving suppression of a current flowing through a substrate.

The present invention for solving the above problems includes a substrate having conductivity,
A semiconductor region disposed on one main surface of the substrate to form a semiconductor element;
At least first and second electrodes disposed on a surface of the semiconductor region;
And an insulating region formed between the first and second portions of the substrate facing the first and second electrodes. The present invention relates to a semiconductor device.

In addition, as shown in claim 2, the semiconductor region has an electron transit layer disposed on the substrate and an electron supply layer disposed on the electron transit layer, and the first electrode is The source electrode is disposed on the electron supply layer, the second electrode is a drain electrode disposed on the electron supply layer, and the semiconductor device is further disposed on the electron supply layer. It is desirable to have a gate electrode.
According to a third aspect of the present invention, in order to form a Schottky barrier diode, the first electrode is an electrode in Schottky contact with the semiconductor region, and the second electrode is in ohmic contact with the semiconductor region. Desirably, the electrodes are in contact.
According to a fourth aspect of the present invention, in order to form a field effect transistor such as a MESFET, the semiconductor region has a semiconductor layer for forming a field effect transistor, and the first electrode is formed on the semiconductor layer. A connected source region; the second electrode is a drain electrode connected to the semiconductor layer; and the semiconductor device further includes a gate electrode formed on the semiconductor layer. Is desirable.
According to a fifth aspect of the present invention, the insulating region is formed in an elongated shape when seen in a plan view, is disposed in parallel to the first and second electrodes, and has a width of 0.1 to 3 μm. Is desirable.
Further, as shown in claim 6, in order to manufacture the semiconductor device of claim 1, forming a groove extending from one main surface of the conductive substrate toward the other main surface;
Embedding an insulator in the groove of the substrate to obtain an insulating region;
Obtaining a semiconductor region for a semiconductor element by vapor-depositing a semiconductor on the substrate having the insulating region;
Forming a first electrode on one side of the surface of the semiconductor region facing the insulating region and forming a second electrode on the other side. It is desirable that

  The insulating region in the substrate provided according to the present invention is disposed between the first and second portions of the substrate facing the first and second electrodes. Therefore, even when a voltage is applied to the first and second portions of the substrate by applying a voltage to the first and second electrodes, the resistance value between the first and second portions is reduced in the insulating region. Since it is higher on the basis of this, the leakage current through the substrate is suppressed. Thereby, the leakage current component of the current flowing between the first and second electrodes of the semiconductor device can be suppressed.

  Next, an embodiment of the present invention will be described with reference to FIGS.

  A HEMT as a semiconductor device using a nitride semiconductor according to Example 1 of the present invention shown in FIG. 1 is a semiconductor for forming a main part of a HEMT element as a semiconductor element 1 and a conductive substrate 1 made of silicon. The region 2 includes a source electrode 3 as a first electrode, a drain electrode 4 as a second electrode, and a gate electrode 5 as a control electrode.

The substrate 1 is made of a p-type silicon single crystal containing a group III element such as B (boron) as a conductivity determining impurity, and has one main surface 6 and the other main surface 7 facing each other. One main surface 6 of the substrate 1 of this embodiment is a (111) just surface in the crystal plane orientation indicated by the Miller index. A preferable impurity concentration of the substrate 1 is a relatively low value, for example, about 1 × 10 ¹² cm ⁻³ to 1 × 10 ¹⁴ cm ⁻³ in order to reduce a leakage current passing through the substrate 1. The rate is a relatively high value, for example, about 100 Ω · cm to 10000 Ω · cm. The substrate 1 has a thickness of about 200 μm, which is larger than the thickness of the semiconductor region 2, and functions as a support for the semiconductor region 2. Note that an n-type impurity may be introduced into the substrate 1 instead of the p-type impurity, or the substrate 1 may be undoped.

  An insulating region 8 according to the invention is provided in the substrate 1. The insulating region 8 is made of silicon oxide embedded in a groove 9 having an opening width W1 of 1 μm formed in the substrate 1 and has a resistivity higher than that of the substrate. The insulating region 8 is disposed between the first and second portions 10 and 11 indicated by a broken line in the substrate 1 facing the source electrode 3 and the drain electrode 4, and the one main surface 6 of the substrate 1 to the other. The main surface 7 is penetrated. In more detail, it arrange | positions between the 3rd part 10a shown by the broken line in the board | substrate 1 which opposes the gate electrode 5, and the 2nd part 11 shown by the broken line in the board | substrate 1 which opposes the drain electrode 4. FIG. Has been. The insulating region 8 is elongated in the planar shape of FIG. 2 and extends parallel to the source electrode 3 and the drain electrode 4. In order to epitaxially grow the semiconductor region 2 on the substrate 1, the width W1 of the insulating region 8 is preferably set to 0.1 to 3 μm, more preferably 0.5 to 1 μm.

  The semiconductor region 2 formed on the substrate 1 includes a buffer region 12, an electron transit layer 13, and an electron supply layer 14, and is a known MOCVD (Metal Organic Chemical Vapor Deposition), that is, a kind of epitaxial growth method. It is formed by the phase growth method.

The buffer region 12 schematically shown in FIG. 1 as one layer was actually formed on and over the first layer of aluminum nitride AlN formed on the substrate 1. And a second layer made of gallium nitride GaN. For example, the first layer of the buffer layer 12 other than AlN
_{Al x M y Ga 1-xy} N
Here, the M is at least one element selected from In (indium) and B (boron), and the x and y satisfy 0 <x ≦ 1, 0 ≦ y <1, and x + y ≦ 1. It can also be formed by another nitride semiconductor that can be represented by a numerical value. Further, the second layer of the buffer region 12 is made of other than GaN, for example,
Al _a M _b Ga _1-ab N
Here, M is at least one element selected from In (indium) and B (boron), and a and b are 0 ≦ a <1, 0 ≦ b <1, a + b ≦ 1, a < It can also be formed by another nitride semiconductor which can be expressed by a numerical value satisfying x. The buffer region 12 can also be formed by repeatedly arranging the first and second layers a plurality of times. In addition, the buffer area 12 can be formed of only the first layer. It is also possible to omit the buffer region 12 and form the electron transit layer 13 directly on the substrate 2.

  The electron transit layer 13 disposed on the buffer region 12 can also be called a channel layer, and is made of a nitride semiconductor, preferably a gallium nitride-based semiconductor, which is undoped, that is, not doped with impurities. A preferred material for the electron transit layer 13 is GaN, and a preferred thickness is 500 nm. The electron transit layer 13 can also be formed of a Group 3-5 compound semiconductor other than GaN.

The electron supply layer 14 disposed on the electron transit layer 13 supplies electrons generated from donor impurities (n-type impurities) to the electron transit layer 10 and is different from the material of the electron transit layer 13. It is made of a n-type nitride semiconductor, and preferably made of n-type Al _0.2 Ga _0.8 N doped with Si as an n-type impurity. The electron supply layer 14 has a thickness of 30 nm, for example. The electron supply layer 13 can also be formed of a Group 3-5 compound semiconductor other than AlGaN.

The source electrode 3 and the drain electrode 4 are formed on one main surface 15 of the semiconductor region 2 and are in ohmic contact with the electron supply layer 14. The gate electrode 5 is formed between the source electrode 3 and the drain electrode 4 on one main surface 15 of the semiconductor region 2 and is in Schottky contact with the electron supply layer 14. Note that a contact layer having a high n-type impurity concentration can be provided between the source electrode 3 and the drain electrode 4 and the electron supply layer 14.

  Next, a method for manufacturing the HEMT according to the first embodiment will be described with reference to FIGS. First, in order to obtain the substrate 1 of FIG. 1, a silicon substrate 1 ′ made of the same material is prepared, and a groove 9 ′ is formed in the substrate 1 ′ by, for example, anisotropic etching. 3 is for obtaining the groove 9 of FIG. 1 and extends from one main surface 6 ′ of the substrate 1 ′ toward the other main surface 7 ′ and has a depth of 200 μm. . The planar pattern and width W1 of the groove 9 'in FIG. 3 are the same as the planar pattern and width of the groove 9 in FIG.

  Next, a silicon oxide film is formed in the groove 9 ′ and on one main surface 6 ′ of the substrate 1 ′. Thereafter, the silicon oxide film other than in the groove 9 ′ is removed, and the groove 9 ′ is removed. An insulating region 8 made of silicon oxide is obtained. In FIG. 4, silicon oxide is buried in the entire groove 9 '. Instead, a silicon oxide film is formed on the wall and bottom of the groove 9', and silicon oxide is formed in the groove 9 '. It is also possible to produce a portion that is not filled with, that is, a void.

  Next, as shown in FIG. 5, the semiconductor region 2 including the buffer region 12, the electron transit layer 13, and the electron supply layer 14 is formed on one main surface 6 ′ of the substrate 1 ′ by a known MOCVD method. An insulating region 8 is exposed on one main surface 6 'of the substrate 1'. The width W1 of the insulating region 8 is relatively narrow 1 μm, and a nitride semiconductor is vapor-phase grown on the substrate 1 '. In this case, the semiconductor grows not only in a direction perpendicular to one main surface 6 'of the semiconductor substrate 1' but also in a direction parallel to the main surface 6 'of one main surface, that is, in a lateral direction. Therefore, the semiconductor region 2 is also obtained on the insulating region 8. The method for forming the semiconductor region 2 is substantially the same as the method described in Patent Document 1 and the like, and thus detailed description thereof is omitted.

  Next, as shown in FIG. 6, the source electrode 3, the drain electrode 4, and the gate electrode 6 are formed on the surface of the semiconductor region 2 by a known method. The source electrode 3 and the drain electrode 4 are formed of a laminated body of, for example, a Ti (titanium) layer and an Al (aluminum) layer, and the gate electrode 5 functioning as a Schottky electrode is, for example, a Pb (palladium) layer and a Ti (titanium) layer. And an Au (gold) layer.

In FIG. 6, the insulating region 8 is located between the first and second portions 10 ′ and 11 ′ of the substrate 1 ′ facing the source electrode 3 and the drain electrode 4, more specifically facing the gate electrode 5. The insulating region 8 is disposed between the third portion 10a of the substrate 1 and the second portion 11 of the substrate 1 facing the drain electrode 4, so that the insulating region 8 is one main surface 6 'of the substrate 1'. 6 that does not penetrate from the first main surface 7 ′ to the other main surface 7 ′, the leakage current between the source electrode 3 and the drain electrode 4 in the HEMT off period, and the gate electrode 5 and the drain electrode 4 An effect of suppressing the leakage current is obtained based on the insulating region 8. However, in order to further enhance the effect of suppressing the leakage current, in this embodiment, the portion 16 where the groove 9 'shown by the broken line of the substrate 1' is not formed is removed. Thereby, the HEMT of FIG. 1 is obtained.
As shown in FIG. 6, the leakage current in the state where the insulating region 8 does not penetrate from the one main surface 6 ′ of the substrate 1 ′ to the other main surface 7 ′ is less than the required leakage current limit value. 6 is also possible to complete the HEMT of FIG. 6 without removing the lower portion 16 of the substrate 1 ′.

  When the HEMT of FIG. 1 is used, an insulator is preferably disposed under the other main surface 7 of the substrate 1. When the HEMT of FIG. 1 is turned on, the control voltage (normally on) for turning on the HEMT between the gate electrode 5 and the source electrode 3 while setting the potential of the drain electrode 4 higher than the potential of the source electrode 3. Apply zero volt in the case of structure. Since the electron transit layer 13 and the electron supply layer 14 are heterojunction, a well-known two-dimensional electron gas (2DEG) layer is formed in the vicinity of the heterojunction of the electron supply layer 14. Functions as a current path between the two. Further, since the electron supply layer 14 is a very thin film, it functions as an insulator in the horizontal direction and functions as a conductor in the vertical direction. Therefore, when the HEMT is turned on, electrons flow through the path of the source electrode 3, the electron supply layer 14, the electron transit layer 13, the electron supply layer 14, and the drain electrode 4. The flow of electrons is controlled by a control voltage applied to the gate electrode 5. During the off period in which the control voltage for turning off the HEMT is applied to the gate electrode 5, the current path of the electron transit layer 13 is blocked by the depletion layer generated based on the off control voltage of the gate electrode 5. As a result, the voltage between the source electrode 3 and the drain electrode 4 becomes higher than when it is turned on, and the voltage between the first and second portions 10 and 11 of the substrate 1 in FIG. However, since the insulating region 8 is provided in the substrate 1, the current passing between the first and second portions 10 and 11 of the substrate 1 and the current passing between the second and third portions 11 and 10a are As compared with the conventional case where the insulating region 8 is not provided, the size is significantly reduced. Thereby, both the leakage current component between the source electrode 3 and the drain electrode 4 of the HEMT and the leakage current component between the gate electrode 10a and the drain electrode 4 can be suppressed.

This embodiment has the following effect in addition to the above-described effect of suppressing the leakage current.
(1) Since the width W1 of the insulating region 8 is a value of a thin film within the range of 0.1 to 3 μm, the semiconductor region 2 can be satisfactorily formed on the insulating region 8 with relatively few crystal defects. Even when the semiconductor region 2 is relatively thin, this flatness can be maintained.
(2) As shown in FIG. 3, a groove 9 ′ that does not penetrate from one main surface 6 ′ of the substrate 1 ′ to the other main surface 7 ′ is formed, and then the insulating region 8, the semiconductor region 2, the source electrode 3, Since the drain electrode 4 and the gate electrode 5 are formed, and then the lower portion 16 of the substrate 1 ′ is removed, it is possible to obtain an insulating region 8 penetrating the substrate 1 while suppressing a decrease in the mechanical support function of the substrate 1. it can.
(3) Since the substrate 1 is made of silicon and the insulating region 8 is made of a silicon oxide film, the insulating region 8 can be easily obtained.
(4) The current passing through the substrate 1 is also suppressed by the insulating region 8 when the HEMT is on. Therefore, the substrate 1 having the insulating region 8 enables high-speed operation of the HEMT as well as a well-known SOI (silicon on insulator) substrate.

  Next, a Schottky barrier diode according to the second embodiment will be described with reference to FIG. However, in FIG. 7 and FIGS. 8 to 10 described later, substantially the same parts as those in FIGS.

  The semiconductor region 2a in FIG. 7 includes a buffer region 12, a GaN layer 13a, and an n-type AlGaN layer 14a that are sequentially arranged on the substrate 1. The GaN layer 13a and the n-type AlGaN layer 14a are formed in the same manner as the electron transit layer 13 and the electron supply layer 14 of FIG. The ohmic electrode 3a as the first electrode is in ohmic contact with the semiconductor region 2a in the same manner as the source electrode 3 in FIG. The Schottky electrode 4a as the second electrode is in Schottky contact similar to the gate electrode 5 of FIG. 1 with respect to the semiconductor region 2a. The insulating region 8 is disposed between the first and second portions 10 and 11 of the substrate 1 facing the ohmic electrode 3a and the Schottky electrode 4a.

  In the Schottky barrier diode of FIG. 7, when the potential of the Schottky electrode 4a is higher than the potential of the ohmic electrode 3a, a forward current flows through the path of the Schottky electrode 4a, the semiconductor region 2a, and the ohmic electrode 3a. On the contrary, when the potential of the Schottky electrode 4a is lower than the potential of the ohmic electrode 3a, the Schottky barrier diode is in a reverse bias state, and only the leakage current flows. Since the insulating region 8 is provided in the substrate 1, the leakage current does not flow through the substrate 1, but only through the semiconductor region 2a, and the leakage current of the Schottky barrier diode is greatly reduced. Therefore, the same effect as that of the first embodiment shown in FIG. 1 can be obtained by the second embodiment shown in FIG. 7A and 7B, a nitride semiconductor layer such as an n-type or p-type GaN layer is provided on the buffer region 12 instead of the GaN layer 13a and the n-type AlGaN layer 14a, and an ohmic electrode is provided on the nitride semiconductor layer. 3a and a Schottky electrode 4a can also be provided.

  8 includes a semiconductor region 2b, a source electrode 3, a drain electrode 4, and a gate electrode 5 formed on a substrate 1 by a vapor deposition method. Yes. The semiconductor region 2b includes a buffer region 12 and a nitride semiconductor layer 13b made of, for example, n-type GaN. The nitride semiconductor layer 13b of FIG. 8 is provided instead of the electron transit layer 13 and the electron supply layer 14 of FIG. The source electrode 3 and the drain electrode 4 are in ohmic contact with the n-type nitride semiconductor layer 13b, and the gate electrode 5 is in Schottky contact with the n-type nitride semiconductor layer 13b. The insulating region 8 in the substrate 1 is disposed between the first and second portions 10 and 11 of the substrate 1 facing the source electrode 3 and the drain electrode 4. More specifically, an insulating region 8 is disposed between the third portion 10 a of the substrate 1 facing the gate electrode 5 and the second portion 11 of the substrate 1 facing the drain electrode 4.

  When the field effect transistor is on, a drain current flows through the path of the drain electrode 4, the semiconductor region 2b, and the source electrode 3, and the voltage between the drain electrode 4 and the source electrode 3 is kept at a relatively low value. On the contrary, when the potential for turning off the gate electrode 5 is applied, no current flows through the n-type nitride semiconductor layer 3b, so that the voltage between the drain electrode 4 and the source electrode 3 is higher than that when the gate electrode 5 is turned on. As a result, the voltage between the first and second portions 10 and 11 of the substrate 1 becomes higher than when the circuit is turned on. However, since the insulating region 8 is provided between the first and second portions 10 and 11 of the substrate 1 and the resistance value of the current path through the substrate 1 is high, the leakage current through the substrate 1 is greatly suppressed. Is done. Therefore, the same effect as that of the first embodiment shown in FIG. 1 can be obtained by the third embodiment shown in FIG.

  The deformed substrate 1a according to the fourth embodiment shown in FIG. 9 has first and second grooves 9a and 9b. The first groove 9a is disposed between the source electrode 3 and the gate electrode 5 indicated by a broken line when viewed in plan, and the second groove 9b is disposed between the drain electrode 4 and the gate electrode 5 when viewed in plan. Has been placed. Accordingly, two grooves 9a and 9b are arranged between the first and second portions of the substrate 1a facing the source electrode 3 and the drain electrode 4. Since the insulating regions 8a and 8b are provided in the first and second grooves 9a and 9b, the leakage current passing through the substrate 1a can be further suppressed. Further, an unnecessary current between the source electrode 3 and the gate electrode 4 and an unnecessary current between the gate electrode and the drain electrode 4 can be suppressed. The deformed substrate 1a shown in FIG. 9 can be used for both the HEMT of FIG. 1 and the MESFET of FIG.

  The HEMT according to the fifth embodiment shown in FIG. 10 has a modified source electrode 3c, drain electrode 4c, gate electrode 5c, and insulating region 9c, and the others are formed substantially the same as FIG. The source electrode 3c and the drain electrode 4c in FIG. 10 are each formed in a comb shape when seen in a plan view, and the gate electrode 5c meanders. Also, the insulating region 9c indicated by the dotted line meanders between the source electrode 3c and the drain electrode 4c in the same manner as the gate electrode 5c.

  Even if the source electrode 3c and the drain electrode 4c are formed in a comb shape, if the insulating region 8c is disposed between the source electrode 3c and the drain electrode 4c in plan view, the same effect as in the first embodiment is obtained. Can be obtained. Note that the insulating region 8c in FIG. 10 can be disposed between the gate electrode 5c and the drain electrode 4c when viewed in plan.

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) Also in the Schottky barrier diode of FIG. 7, the ohmic electrode 3a and the Schottky electrode 4a can be formed in a non-linear pattern such as a comb, and the insulating region 8 can also be formed in a non-linear pattern. Further, the source electrode 3, the drain electrode 4, and the gate electrode 5 of the MESFET of FIG. 8 can be formed in a non-linear pattern such as a comb shape, and the insulating region 8 can also be a non-linear pattern.
(2) In each embodiment, the insulating region 8 is not formed so as to reach the other main surface 7 from the one main surface 6 of the substrate 1, and reaches the other main surface 7 from the one main surface 6 of the substrate 1. It can be formed to a depth that does not. Further, the insulating region 8 can be formed only in an arbitrary part between the one main surface 6 and the other main surface 7 of the substrate 1. Further, as viewed in a plan view, the insulating region 8 is not formed so as to connect all of the opposing sides of the one main surface 6 of the substrate 1 but only in a part between the sides of the pair. You can also In these cases, the first and second portions of the substrate 1 facing the first and second electrodes are not completely separated by the insulating region, but the first and second portions of the substrate 1 are interposed by the insulating region 8. The resistance value between the second portions increases and the leakage current through the substrate 1 decreases.
(3) Various modifications can be made to the configuration of the semiconductor regions 2, 2a, and 2b. For example, in the semiconductor region 2 of FIG. 1, a well-known spacer layer is disposed between the electron transit layer 13 and the electron supply layer 14, or a well-known contact layer is provided on the electron supply layer 14, or a buffer. Layer 12 can be omitted.
(4) The insulating region 8 can be formed of an insulating material other than silicon oxide. The insulating region 8 can also be a gap.
(5) The substrates 1 and 1a can be formed of a material other than single crystal silicon, for example, silicon oxide such as SiC, nitride semiconductor, or the like.
(6) An insulated gate field effect transistor can be obtained by disposing a gate insulating film between the gate electrode 5 of FIGS. 1 and 8 and the semiconductor regions 2 and 2b. The present invention can also be applied to other semiconductor devices in which current flows in the lateral direction other than HEMT, MESFET, and Schottky diode.

It is a center longitudinal cross-sectional view which shows schematically HEMT according to Example 1 of this invention. It is a top view of HEMT of FIG. It is sectional drawing of the board | substrate for demonstrating the manufacturing method of HEMT of FIG. It is sectional drawing which shows what provided the insulation area | region in the board | substrate of FIG. It is sectional drawing which shows what provided the semiconductor region on the board | substrate of FIG. It is sectional drawing which shows what provided the electrode on the semiconductor region of FIG. 6 is a cross-sectional view showing a Schottky barrier diode according to Example 2. FIG. 6 is a cross-sectional view showing a MESFET according to Embodiment 3. FIG. FIG. 6 is a plan view showing a HEMT substrate according to a fourth embodiment. FIG. 10 is a plan view showing a HEMT according to a fifth embodiment.

Explanation of symbols

1, 1a Substrate 2, 2a, 2b Semiconductor region 3 Source electrode 4 Drain electrode 5 Gate electrode 8 Insulating region 9 Groove 10, 11 First and second parts

Claims (6)

A conductive substrate;
A semiconductor region disposed on one main surface of the substrate to form a semiconductor element;
At least first and second electrodes disposed on a surface of the semiconductor region;
A semiconductor device comprising: an insulating region formed between first and second portions of the substrate facing the first and second electrodes. The semiconductor region has an electron transit layer disposed on the substrate and an electron supply layer disposed on the electron transit layer;
The first electrode is a source electrode disposed on the electron supply layer;
The second electrode is a drain electrode disposed on the electron supply layer;
The semiconductor device according to claim 1, further comprising a gate electrode disposed on the electron supply layer.   The first electrode is an electrode in Schottky contact with the semiconductor region to form a Schottky barrier diode, and the second electrode is an electrode in ohmic contact with the semiconductor region. The semiconductor device according to claim 1. The semiconductor region comprises a semiconductor layer for forming a field effect transistor;
The first electrode is a source region connected to the semiconductor layer;
The second electrode is a drain electrode connected to the semiconductor layer;
The semiconductor device according to claim 1, further comprising a gate electrode formed on the semiconductor layer.   5. The insulating region according to claim 1, wherein the insulating region is elongated in plan view, is disposed in parallel to the first and second electrodes, and has a width of 0.1 to 3 [mu] m. The semiconductor device according to any one of the above. Forming a groove extending from one main surface of the conductive substrate toward the other main surface;
Embedding an insulator in the groove of the substrate to obtain an insulating region;
Obtaining a semiconductor region for a semiconductor element by vapor-depositing a semiconductor on the substrate having the insulating region;
Forming a first electrode on one side of the surface of the semiconductor region facing the insulating region, and forming a second electrode on the other side;
A method for manufacturing a semiconductor device, comprising:

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