JP2011124514A - Group-iii nitride-based semiconductor element, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group-III nitride-based semiconductor element inexpensively manufacturable and having a high dielectric breakdown voltage, and to provide a method of manufacturing the same. <P>SOLUTION: The group-III nitride-based semiconductor element includes: a substrate formed, on a surface thereof, with a silicon layer, an insulating layer, and a composite layer including, on a surface, a plurality of nucleus regions formed of silicon and an insulation region embedding areas among the plurality of nucleus regions in this order; a buffer layer formed on the substrate and formed of a group-III nitride-based semiconductor; an operation layer formed on the buffer layer and formed of a group-III nitride-based semiconductor; and a first electrode and a second electrode formed on the operation layer, wherein the maximum width L<SB>1</SB>of each of the nucleus regions is smaller than a distance L<SB>2</SB>between the first electrode and the second electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a group III nitride semiconductor device formed on a silicon substrate, in particular, a GaN semiconductor device and a method for manufacturing the same.

Wide band gap semiconductors typified by Group III nitride compounds have high dielectric breakdown voltage, good electron transport properties, and good thermal conductivity, making them extremely useful as semiconductor devices for high temperature, high power, or high frequency applications. Attractive. For example, AlGaN / GaN
A field effect transistor (FET) having a heterostructure has a 2
Dimensional electron gas is generated. This two-dimensional electron gas has high electron mobility and carrier density, and has attracted much attention. In addition, a heterojunction FET (HFET) using an AlGaN / GaN heterostructure has a low on-resistance and a high switching speed, and can operate at a high temperature. These features are very suitable for power switching applications.

Group III nitride semiconductors are generally silicon (Si), silicon carbide (SiC).
Metal organic chemical vapor deposition (MOCVD: Metal Oxi) on a dissimilar material substrate such as sapphire
Crystal growth is performed by de Chemical Vapor Deposition (MBE) method, Molecular Beam Epitaxy (MBE) method, etc., but using Si as a substrate for growth is being studied for cost reduction in mass production. .

However, since a substrate made of Si and a group III nitride semiconductor have different physical constants such as a lattice constant and a thermal expansion coefficient, by forming a buffer layer made of a material such as AlN, InGaN, AlGaN, or GaN, the substrate Reducing lattice mismatch between the semiconductor layer and the semiconductor layer has been studied.

In Patent Document 1, a Si nanowire is formed on a silicon substrate, and G is attached to the tip of the nanowire.
It is described that the lattice mismatch and the thermal mismatch between the substrate and the compound semiconductor are alleviated by depositing a compound semiconductor made of aN.

However, the dielectric breakdown voltage of Si is 0.3 MV / cm, which is greatly inferior to 3.0 MV / cm of Group III nitride semiconductors. Therefore, a substrate made of Si and Ga
When the compound semiconductor layer made of N is in direct contact, dielectric breakdown occurs due to a leak path passing through the Si substrate, making it difficult to achieve high breakdown voltage of the device.

In order to solve such a problem, it is necessary to form a group III nitride semiconductor thin film to a thickness of about 10 μm. However, it takes time for crystal growth, and the manufacturing cost is greatly increased. there were.

Patent Document 2 discloses a substrate in which a SiO ₂ layer 2b and a Si layer 2c are sequentially formed on a conductive Si substrate 2a in order to increase the vertical breakdown voltage in a nitride semiconductor device formed on a Si substrate. The use is described (see FIG. 11).

JP 2007-326771 A JP 2008-034411 A

However, even in the invention described in Patent Document 2, since the Si layer 2c is provided on the side on which the group III nitride semiconductor is formed, there is conductivity in a direction parallel to the surface thereof.
There is a problem in that dielectric breakdown occurs due to a leak path passing through the i layer 2c.

The present invention has been made to solve the above-described problems, and can be manufactured at a low cost, and has a high breakdown voltage. A group III nitride semiconductor device and a group III nitride semiconductor An object is to provide a method for manufacturing an element.

In order to solve the above problems, the group III nitride semiconductor device of the present invention includes a silicon layer, an insulating layer, and a composite layer having a plurality of core regions made of silicon and an insulating region filling between the plurality of core regions. A substrate formed in this order, a buffer layer made of a group III nitride semiconductor formed on the substrate, an operation layer made of a group III nitride semiconductor formed on the buffer layer, and the operation layer and a first electrode and a second electrode formed on, that each of the maximum width L ₁ of the core region is less than the distance L ₂ between the first electrode and the second electrode It is characterized by.

A group III nitride semiconductor device according to another aspect of the present invention is characterized in that the insulating region is made of SiO ₂ .

In the method for manufacturing a group III nitride semiconductor device of the present invention, a silicon layer, an insulating layer, and a composite layer having a plurality of core regions made of silicon on the surface and an insulating region filling between the plurality of core regions are formed in this order. Preparing the prepared substrate, and using the nucleus region as a nucleus on the substrate, II
A step of forming a buffer layer made of a group I nitride semiconductor, a step of forming an operation layer made of a group III nitride semiconductor on the buffer layer, and a first electrode and a second electrode on the operation layer. , in which and forming spaced apart by the maximum width L ₁ or more predetermined distance L ₂ of the plurality of core regions.

According to the present invention, a group III nitride semiconductor device having sufficient breakdown voltage characteristics (breakdown voltage) can be formed without forming a buffer layer and an operating layer made of a group III nitride semiconductor thick. Since the thickness of the layer made of a group III nitride semiconductor for obtaining a desired breakdown voltage can be reduced, the manufacturing cost can be reduced.

1 is a side sectional view showing a schematic configuration of a group III nitride semiconductor device according to an embodiment of the present invention. 1A is a top sectional view and FIG. 2B is a top view showing a schematic configuration of a group III nitride semiconductor device according to an embodiment of the present invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the group III nitride semiconductor device which concerns on one Embodiment of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the group III nitride semiconductor device which concerns on one Embodiment of this invention. It is side sectional drawing which shows schematic structure of the group III nitride semiconductor device which concerns on 2nd embodiment of this invention. It is a sectional side view showing a schematic structure of a group III nitride semiconductor device according to another embodiment of the present invention. It is a top view which shows schematic structure of the group III nitride semiconductor device which concerns on Example 1 of this invention. It is a graph which shows the relationship between the distance between electrodes of a group III nitride semiconductor device which concerns on Example 1 of this invention, and a proof pressure. It is a top view which shows schematic structure of the group III nitride semiconductor device which concerns on Example 2 of this invention. It is a graph which shows the relationship between the distance between electrodes of a group III nitride semiconductor device which concerns on Example 2 of this invention, and a proof pressure. It is sectional drawing which shows schematic structure of the nitride semiconductor element which concerns on a prior art.

  The group III nitride semiconductor device according to the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of a group III nitride semiconductor device 100 according to the first embodiment of the present invention. As shown in FIG. 1, the group III nitride semiconductor device 100 of the present invention includes a silicon layer 11, an insulating layer 13, and a plurality of core regions 15 made of silicon on the surface and insulation filling between the plurality of core regions. A substrate 10 in which an L / S (line / stripe) layer 19 having a region 17 is formed in this order, and an AlN layer 21 (described later) formed on the substrate 10.
, And a buffer layer 20 comprising a multi-layer 23 in which a plurality of GaN layers and Al _x Ga _1-x N layers (0 <x ≦ 1) are alternately stacked, and a group III nitride formed on the buffer layer 20 An operation layer 30 made of a physical semiconductor, and a plurality of electrodes (first electrode 41,
A second electrode 43).

That is, the group III nitride semiconductor device 100 according to the first embodiment of the present invention is a Schottky barrier diode (SBD).

Here, the group III nitride compound semiconductor is a compound semiconductor typified by GaN, for example, Al _a In _b Ga ₁ -abN (0 ≦ a <1, 0 ≦ b <1, a + b It is a compound semiconductor represented by <1). The group III nitride compound semiconductor used in the present invention may be one in which a part of nitrogen (N) is substituted with arsenic (As) or phosphorus (P) as a group V element.

FIG. 2 is a top view of the group III nitride semiconductor device 100 of FIG. 1 according to the first embodiment of the present invention. 2A is a top view of the portion of the L / S layer 19, and FIG. 2B is a top view of the operation layer 30 and the electrodes.
Here, as shown in FIG. 2A, the L / S layer 19 has a plurality of core regions 15 of a predetermined shape made of silicon on the surface and an insulating region formed so as to fill the space between the core regions 15. 17 and the insulating region 17 is formed of an insulator such as SiO ₂ , for example. Substrate 1
The zero core region 15 has a maximum width L ₁ of a plurality of electrodes 41, 43 formed on the operation layer 30.
Are formed to be smaller than the adjacent distance L ₂ (FIG. 2B).

In FIG. 2A, the layer (the L / S layer 1) for forming the group III nitride semiconductor of the substrate 10 is shown.
9) illustrates a line / stripe pattern as the planar shape of the nucleus region 15 to be exposed, but is not limited to this, and includes a polygonal nucleus region 15 such as a circle, a rectangle, or a hexagon. It may be a composite layer.

Next, a method for manufacturing a group III nitride semiconductor device of the present invention will be described with reference to the drawings.
3 and 4 are schematic cross-sectional views illustrating a process for manufacturing a group III nitride semiconductor device 100 according to an embodiment of the present invention.
First, as shown in FIG. 3A, a substrate (substrate precursor) 10 ′ provided with a silicon layer 11, an insulating layer 13, and another silicon layer 15 ′ is prepared. At this time, another silicon layer 15 '
The surface orientation of the main surface (exposed surface) is preferably the (111) plane. Further, as a method for producing the substrate 10 ′, a conventionally known ion implantation method, bonding method, or the like can be employed.

Next, a mask M having a predetermined pattern is formed on the silicon layer 15 ′, and the silicon layer 15 ′ where the mask M is not formed is oxidized to oxidize the core region 15 made of Si and the Si layer 15.
An L / S layer 19 having an insulating region 17 made of O ₂ is formed (FIG. 3B). As a method for oxidizing the silicon layer 15 ′, various conventionally known methods such as thermal oxidation can be used. The substrate 10 is formed by the above process.

Next, the mask M is removed, and the nucleus region 15 exposed on the surface of the L / S layer 19 is used as a growth nucleus.
Selective lateral growth (ELOG: Epitaxial Lateral Overgrowt)
h), an island-shaped AlN layer 21 is formed (FIG. 3C). At this time, on the surface of the L / S layer, a portion that does not become a nucleus of epitaxial growth, that is, an insulating region 17 made of SiO ₂
However, by appropriately setting the growth conditions, epitaxial growth can be performed with the nucleus region 15 made of Si as the nucleus. Furthermore, the ELOG can make the AlN layer 21 a layer with reduced dislocations.

Next, the island-like _GaN / Al on the grown AlN layer 21 in _{x Ga 1-x} N (where 0 <
The buffer layer 20 is formed by forming the multi-layer 23 having a multilayer structure of x ≦ 1) (FIG. 4A). In forming the multi-layer 23, for example, the growth in the lateral direction is promoted by changing the growth pressure so that the surface becomes flat.

Further, an operation layer 30 made of a group III nitride semiconductor for forming an element is formed on the buffer layer 20. The operation layer 30 is made of Al _y In _z Ga _1-yz N (where 0 ≦ y ≦
1, 0 ≦ z ≦ 1, 0 ≦ x + y ≦ 1) may be formed of one layer of a single composition made of a group III nitride-based semiconductor, a plurality of layers having different compositions, or a single layer You may form in the layer from which a composition changes among layers.

The operation layer 30 is, for example, p-type GaN (p-GaN), undoped GaN (un-G).
aN), p-GaN or un-GaN and AlGaN stack (AlGaN /
p-GaN (un-GaN)) or a layer made of Al _y Ga _1-y N (0 ≦ y ≦ 1) in which the buffer layer 20 side is GaN and the Al composition gradually increases in the stacking direction. be able to.

It is desirable that the maximum width of the insulating region 17 be smaller than the thickness of the buffer layer 20. By setting the maximum width of the insulating region 17 in this way, even when the AlN layer 21 is formed in an island shape by selective lateral growth, the outermost surface of the buffer layer 20, that is, the surface on which the operation layer 30 is formed is flat. Sexuality can be increased.

Thereafter, by forming a plurality of electrodes 41 and 43 on the operation layer 30, the group III nitride semiconductor device 100 according to the first embodiment of the present invention is completed.

The group III nitride semiconductor device 100 according to the first embodiment can be used as a Schottky barrier diode (SBD) by forming the electrodes 41 and 43 as ohmic electrodes and Schottky electrodes, respectively. At this time, the ohmic electrode can be formed by depositing Ti / Al to a thickness of 25 nm and 200 nm using sputtering and lift-off methods, and performing a heat treatment at 600 ° C. for 10 minutes. Similarly, the Schottky electrode can be formed by depositing Ni / Au to a thickness of 50 nm and 100 nm, respectively, using sputtering and lift-off methods.

The group III nitride semiconductor device 100 formed in this way is formed on a substrate 10 having a composite layer having a plurality of core regions made of silicon on the surface and an insulating region filling between the core regions. Therefore, a leakage path passing through the Si substrate is not formed between the electrodes, and a high breakdown voltage can be realized.

Further, since the selective lateral growth is performed with the nucleus region 15 made of Si exposed on a part of the surface of the L / S layer 19 as a nucleus, the dislocation density is reduced, and the group III nitride formed thereon The crystal quality of each layer made of a compound semiconductor can be improved.

Further, conventionally, it has been necessary to grow a layer made of a group III nitride compound semiconductor in order to increase the breakdown voltage. However, when obtaining the same breakdown voltage, the thickness of the group III nitride compound semiconductor layer is also reduced. Since the thickness can be reduced, the cost can be significantly reduced.

(Second embodiment)
Next, a group III nitride semiconductor device according to the second embodiment of the present invention will be described.
FIG. 5 is a cross-sectional view showing a schematic configuration of a group III nitride semiconductor device 200 according to the second embodiment of the present invention.

The group III nitride semiconductor device 200 includes the substrate 10, the buffer layer 20, and the operation layer 30 as in the group III nitride semiconductor device 100, but the structure of the electrodes formed on the operation layer 30 is different. ing. That is, in the group III nitride semiconductor device 200, the operation layer 3
Two ohmic electrodes (a source electrode 51 and a drain electrode 53) are formed apart from each other on 0, and an insulating film 60 made of, for example, SiO ₂ is formed on the surface of the operation layer 30 between the two ohmic electrodes.
Is formed. Then, a gate electrode 55 is formed on the insulating film 60 to form a so-called MO.
S-type field effect transistor MOSFET (FET: Field Effect Tra)
nistor).

The group III nitride semiconductor device 200 is also formed such that the maximum width L ₁ of the nucleus region 15 of the substrate 10 is smaller than the distance L ₃ between the source electrode 51 and the drain electrode 53. With such a configuration, even when a high voltage is applied between the source electrode 51 and the drain electrode 53, a leak path through the substrate 10 is not formed, so that a high breakdown voltage can be realized. it can.

In the present embodiment, the group III nitride semiconductor device 200 has the insulating film 60 formed directly on the surface of the operation layer 30, but the present invention is not limited to such a structure.
That is, as in the group III nitride semiconductor device 300 shown in FIG. 6, a part of the surface of the operation layer 30 between the source electrode 51 and the drain electrode 53 is removed, and the recess 31 having an inverted trapezoidal cross section is removed. The gate electrode 55 may be formed on the inner surface of the recess 31 with the insulating film 60 interposed therebetween. At this time, the operation layer 30 includes a channel layer 33 made of p-GaN or un-GaN and an electron supply layer 35 made of AlGaN, and is formed to a depth at which the bottom surface 31 a of the recess 31 reaches the channel layer 33. Is desirable.

With such a structure, a two-dimensional electron gas (2DEG: 2dimension) is generated between the channel layer 33 and the electron supply layer 35 due to spontaneous polarization and polarization caused by the piezoelectric effect.
nal electron gas) occurs. Since 2DEG has a high carrier density and electron mobility, the group III nitride semiconductor device 300 can be a MOSFET having low on-resistance and excellent switching characteristics.

The group III nitride semiconductor device of the present invention can be variously modified without departing from the spirit of the invention.
For example, although the operation layer 30 in FIG. 6 is formed by the channel layer 33 and the electron supply layer 35, a layer made of AlN of several nm may be inserted between the channel layer 33 and the electron supply layer 35. With such a configuration, 2 formed between the channel layer 33 and the electron supply layer 35.
The carrier density of the dimensional electron gas can be increased and the electron mobility can be further improved.

  Hereinafter, embodiments of the present invention will be described in detail.

The group III nitride semiconductor device of Example 1 has the same configuration as the SBD shown in FIG. Hereinafter, a method for manufacturing a group III nitride semiconductor device according to Example 1 will be described.

First, a substrate (substrate precursor) 10 ′ having thicknesses of 5 μm and 0.5 μm of SiO ₂ layer (insulating layer) 13 and Si layer (another silicon layer) 15 ′ is prepared. PCVD (Plasma-
enhanced Chemical Vapor Deposition), or L
A thickness of 500 n is formed on the substrate 10 'by PCVD (Low Pressure CVD).
m SiN is deposited. Thereafter, an L / S pattern (not shown) having a line width and a space width of 1 μm is formed by photolithography.

Next, a part of SiN is removed by reactive ion etching (RIE), and then the resist is removed. This SiN is used as a mask M in the following oxidation process.
Next, the Si layer 15 ′ of the substrate is oxidized by wet oxidation, and then the mask is removed by RIE.

After the substrate 10 on which the L / S pattern is formed is RCA cleaned, metal organic chemical vapor deposition (MO
CVD) was set in the apparatus, trimethyl gallium as source gases (TMGa), trimethyl aluminum (TMAl), AlN layer 21 by using NH _3, and a multi-layer 23, GaN layer, A
The lGaN layer is grown sequentially.

The AlN layer 21 uses TMAl and NH ₃ as source gases at a growth pressure of 50 Torr.
It grows in an island shape so that the average thickness is 100 nm.
The multi-layer 23 has a structure in which eight pairs of layers made of GaN having a thickness of 200 nm and layers made of AlN having a thickness of 20 nm are alternately stacked. At this time, the first four pairs are grown at a growth pressure of 500 Torr using TMGa, TMAl and NH ₃ as source gases. The remaining four pairs grow at a growth pressure of 50 Torr for the purpose of flattening the growth surface.

Further, the GaN layer and the AlGaN layer are grown so as to have thicknesses of 800 nm and 25 nm, respectively, using TMGa, TMAl and NH ₃ as source gases at a growth pressure of 200 Torr. The Al composition of the AlGaN layer 35 is 20%.

In the AlGaN / GaN heterojunction structure, 2DEG is generated as described above, and thus this 2DEG functions as a channel. For this reason, in this embodiment, the AlGaN / GaN laminated structure functions as the operation layer 30.

Thereafter, an ohmic electrode made of Ti / Al is formed on the AlGaN layer by sputtering and a lift-off method, and heat treatment is performed at 600 ° C. for 10 minutes. The thickness of Ti / Al is 25 nm and 200 nm, respectively. A Schottky electrode made of Ni / Au is formed by the same method. The thicknesses of Ni / Au are 50 nm and 100 nm, respectively. Through the above steps, the semiconductor element (SBD) according to Example 1 is completed.

FIG. 7 is a top view of the group III nitride semiconductor device 400 of the first embodiment. As shown in FIG. 7, the group III nitride semiconductor device 400 of this example includes two electrodes (Schottky electrode and ohmic electrode) on the operation layer 30. The Schottky electrode 71 has a diameter of 300
The ohmic electrode 73 has a circular shape of μm and a shape having a concentric opening with the Schottky electrode 71. In this embodiment, the distance between the Schottky electrode 71 and the ohmic electrode 73 (
The breakdown voltage when the electrode distance) _{L a} varied 3μm~70μm was measured.

As Comparative Example 1, a semiconductor element having the same configuration as that of Example 1 except that an SOI substrate according to the prior art was used was prepared, and the distance between the Schottky electrode and the ohmic electrode was 3 μm.
The withstand voltage was measured when it was changed at ˜70 μm.

Figure 8 is a graph showing the relation between the electrode distance L _a and the breakdown voltage. As shown in FIG. 8, in the case of Comparative Example 1 using an SOI substrate Si conductive as the substrate is present on the entire surface breakdown voltage by increasing the electrode distance L _a was about 700 V. In contrast, in Example 1 of the present invention improves the breakdown voltage according to increase the inter-electrode distance L _a, the inter-electrode distance L _a could be obtained breakdown voltage of more than 2500V by the above 20 [mu] m. Here, the breakdown voltage is a voltage applied between the electrodes when the leak current between the electrodes exceeds 1 × 10 ⁻⁵ A / mm.

The group III nitride semiconductor device of Example 2 has the same configuration as MOSFET 300 shown in FIG. Hereinafter, although the manufacturing method of the group III nitride semiconductor device which concerns on Example 2 is demonstrated, since it is the same as that of Example 1 until the process of forming an AlGaN layer, description is abbreviate | omitted.

A SiO ₂ film is formed on the AlGaN layer 35 by PCVD, and photolithography and RI
An etching mask for forming a recess portion of the gate is formed by E. Thereafter, the recess portion 31 is formed by etching the AlGaN layer in the gate portion by dry etching.

After performing the RCA cleaning, a SiO ₂ film having a thickness of 60 nm is formed as the insulating film 60.
After removing the portion of the SiO ₂ film where the ohmic electrodes (source electrode 51 and drain electrode 53) are to be formed, an ohmic electrode is formed using sputtering and a lift-off method. The ohmic electrode is made of Ti / Al having a thickness of 25 nm and 200 nm, respectively. After forming the ohmic electrode, heat treatment is performed at 600 ° C. for 10 minutes.

Thereafter, the gate electrode 55 is formed on the SiO ₂ film 60 by sputtering and a lift-off method.
Form. The gate electrode 55 is made of Ti / Al having a thickness of 50 nm and 100 nm, respectively.

FIG. 9 is a top view of the group III nitride semiconductor device 500 of the second embodiment. As shown in FIG. 8, the group III nitride semiconductor device 500 of this example includes an insulating film between two ohmic electrodes (source electrode 51 and drain electrode 53) on the operating layer 30 and between the two ohmic electrodes. 6
A gate electrode 55 is provided through zero.

The gate electrode 55 has an annular shape with an inner diameter of 300 μm. The drain electrode 53 is
The gate electrode 55 is formed 5 μm apart from the gate electrode 55. Source electrode 5
1 is circular, is formed at a predetermined distance L _b on the inside of the gate electrode 55. In this embodiment, the measured breakdown voltage when changing the distance between electrodes L _b between the source electrode 51 and the gate electrode 55 in 3Myuemu～70myuemu.

As Comparative Example 2, a semiconductor device having the same configuration as that of Example 2 except that an SOI substrate according to the related art was used was prepared, and the interval between the drain electrode and the gate electrode was 3 μm to 70 μm.
The pressure resistance when changing with m was measured.

FIG. 10 is a graph showing the relationship between the interelectrode distance _Lb and the breakdown voltage. As shown in FIG. 10, in the case of Comparative Example 2 using a conductive Si substrate as a substrate, whereas breakdown voltage by increasing the electrode distance L _b was about 700 V, the present invention as a substrate in the case of using the substrate, an electrode distance L _b can be obtained breakdown voltage of more than 2600V by the above 30 [mu] m.

100, 200, 300, 400, 500 Group III nitride semiconductor device 10 Substrate 10 ′ Substrate (substrate precursor)
11 Silicon layer 13 Insulating layer 15 Core region 15 ′ Another silicon layer 17 Insulating region 19 L / S layer 20 Buffer layer 21 AlN layer 23 Multi layer 30 Operating layer 31 Recessed portion 31a Bottom surface 33 Channel layer 35 Electron supply layer 41 First Electrode 43 second electrode 51 source electrode 53 drain electrode 55 gate electrode 60 insulating film 71 Schottky electrode 73 ohmic electrode

Claims (6)

A substrate in which a composite layer having a silicon layer, an insulating layer, and a plurality of nucleus regions made of silicon and an insulating region filling between the plurality of nucleus regions is formed in this order;
A buffer layer made of a group III nitride semiconductor formed on the substrate;
An operation layer made of a group III nitride semiconductor formed on the buffer layer;
A first electrode and a second electrode formed on the operating layer;
Each of the maximum width L ₁ is, the first electrode and the group III nitride semiconductor device characterized by less than the distance L ₂ between the second electrode of the nucleus region. The group III nitride semiconductor device according to claim 1, wherein the insulating region is made of SiO ₂ . 3. The group III nitride semiconductor device according to claim 1, wherein the first electrode is an ohmic electrode, and the second electrode is a Schottky electrode. 4. The first electrode is a source electrode, the second electrode is a drain electrode, an insulating film formed between the source electrode and the drain electrode on the surface of the operation layer, and the insulation The group III nitride semiconductor device according to claim 1, further comprising a gate electrode formed on the film. Preparing a substrate comprising a silicon layer, an insulating layer, and a composite layer having a plurality of core regions made of silicon and an insulating region filling the plurality of core regions in this order;
Forming a buffer layer made of a group III nitride semiconductor using the nucleus region as a nucleus on the substrate;
Forming an operation layer made of a group III nitride semiconductor on the buffer layer;
Wherein the first electrode and the second electrode on the active layer, the group III nitride semiconductor device and forming spaced apart by the maximum width L ₁ or more predetermined distance L ₂ of the plurality of core regions Production method. Preparing the substrate comprises preparing a substrate precursor comprising one silicon layer, an insulating layer, and another silicon layer;
The method for manufacturing a group III nitride semiconductor device according to claim 5, further comprising a step of oxidizing a predetermined portion of the another silicon layer.

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