KR101668445B1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR101668445B1
KR101668445B1 KR1020150025310A KR20150025310A KR101668445B1 KR 101668445 B1 KR101668445 B1 KR 101668445B1 KR 1020150025310 A KR1020150025310 A KR 1020150025310A KR 20150025310 A KR20150025310 A KR 20150025310A KR 101668445 B1 KR101668445 B1 KR 101668445B1
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South Korea
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semiconductor layer
gate insulating
insulating film
channel structure
structure
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KR1020150025310A
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Korean (ko)
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KR20160102792A (en
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이정희
손동혁
김도균
조영우
원철호
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경북대학교 산학협력단
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L2029/785
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13064High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

Abstract

A semiconductor device manufacturing method is disclosed. The method includes the steps of forming a first semiconductor layer on a substrate, forming a second semiconductor layer that induces a two-dimensional electron gas (2DEG) on the first semiconductor layer, Forming a third semiconductor layer doped with a p-type dopant on the second semiconductor layer, forming a first semiconductor layer, a second semiconductor layer and a second semiconductor layer so as to have a predetermined source structure, a drain structure and a channel structure, Etching the structure in which the third semiconductor layers are stacked, forming the gate insulating film so as to cover the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure and the upper surface of the third semiconductor layer in the channel structure And forming a gate electrode on the gate insulating film.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a pin-and-pet structure having a normally-on characteristic and using a 2DEG channel and a method of manufacturing the same.

As the degree of integration of semiconductor devices increases, the design rule for the elements of the semiconductor device becomes more severe. In particular, for semiconductor devices requiring a large number of transistors, the gate length, which is the standard of the design rule, is reduced, and the channel length is also reduced. The reduction in the channel length of the transistor results in a so-called short channel effect .

The short channel effect means that the effective channel length of the transistor is reduced due to the effect of the drain potential and the threshold voltage is reduced. Due to the short channel effect, it is difficult to control the transistor, and the off current of the transistor tends to increase. As a result, the reliability of the transistor is lowered, for example, the refresh characteristic of the memory element can be adversely affected.

In recent years, a fin-FET having a fin-channel structure in which a short channel effect, which is a problem in a conventional planar transistor, is suppressed and at the same time an operating current is increased, Respectively. Particularly, a device using a group III nitride semiconductor has various advantages such as a high breakdown field (~ 3 x 10 6 V / cm), maximum current density, stable high temperature operation, high thermal conductivity, It was spotlighted.

On the other hand, high electron mobility transistors (HEMTs) made of nitride semiconductors have also been attracting attention. In the HEMT, semiconductors having different band gaps are bonded, and 2-dimensional electron gas (2DEG) is induced in a semiconductor having a small band gap by a semiconductor having a large band gap. Such a HEMT has a problem that a normally-on phenomenon occurs because a 2DEG channel is formed basically.

It is an object of the present invention to provide a semiconductor device having a pin-and-pet structure using a 2DEG channel and having a normally-on characteristic, and a method of manufacturing the same.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming a first semiconductor layer on a substrate, forming a 2-dimensional (2DEG) Forming a second semiconductor layer on the first semiconductor layer, the third semiconductor layer being doped with a p-type dopant on the second semiconductor layer, forming a predetermined source structure, Drain structure and a channel structure, etching the structure in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure, Forming a gate insulating film so as to cover a side surface of the first semiconductor layer and an upper surface of the third semiconductor layer in the channel structure; and forming a gate electrode on the gate insulating film.

In this case, the step of forming the gate insulating layer may include forming a gate insulating layer on the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure, The gate insulating film can be formed so as to be thicker than the thickness of the formed gate insulating film.

The forming of the gate insulating layer may include forming a first gate insulating layer on the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure and the upper surface of the third semiconductor layer in the channel structure Removing a first gate insulating film formed on a top surface of a third semiconductor layer in the channel structure while leaving a first gate insulating film formed on a side surface of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure; And forming a second gate insulating film on the upper surface of the third semiconductor layer and the first gate insulating film in the channel structure.

The forming the gate insulating layer may include forming a gate insulating layer on the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure and the top surface of the third semiconductor layer in the channel structure, The thickness of the gate insulating film formed on the upper surface of the third semiconductor layer in the channel structure is set to be smaller than the thickness of the gate insulating film formed on the side surfaces of the first semiconductor layer, And etching the gate insulating film formed on the upper surface of the third semiconductor layer in the channel structure.

The etching may include forming a mask layer having a pattern corresponding to the predetermined source structure, the drain structure, and the channel structure on the third semiconductor layer to form the first semiconductor layer, the second semiconductor layer, A third semiconductor layer, and a third semiconductor layer in the channel structure, wherein the width of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure is greater than the width of the mask layer formed on the third semiconductor layer in the channel structure Wet etching the side surfaces of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer in the channel structure with an etching solution so as to have a smaller width, and removing the mask layer.

In this case, the etching solution may be a tetra-methyl ammonium hydroxide (TMAH) solution.

On the other hand, the method of manufacturing a semiconductor device according to the present embodiment may further include forming a source electrode in contact with a second semiconductor layer in the source structure, and forming a drain electrode in contact with the second semiconductor layer in the drain structure have.

Meanwhile, the first semiconductor layer may be made of GaN, and the second semiconductor layer may be made of AlGaN or AlN.

Meanwhile, a semiconductor device according to an embodiment of the present invention includes a source structure in which a first semiconductor layer and a second semiconductor layer are stacked, a drain region spaced apart from the source structure, A channel structure in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer doped with the p-type dopant are stacked, a gate structure that connects the source structure and the drain structure, And an insulating film and a gate electrode disposed on the gate insulating film.

In this case, the gate insulating layer may be formed thicker on a side surface of the channel structure than an upper surface of the channel structure.

The gate electrode may be disposed so as to surround all of the predetermined regions of the exposed surfaces of the gate insulating film.

On the other hand, the first semiconductor layer may be made of GaN, and the second semiconductor layer may be made of AlGaN or AlN.

Meanwhile, the semiconductor device according to the present embodiment may further include a source electrode disposed on the source structure and a drain electrode disposed on the drain structure.

FIGS. 1 to 7B are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention;
8 to 9 are sectional views for explaining semiconductor devices according to various embodiments of the present invention,
10 to 11 are views for explaining the formation of a gate insulating film according to an embodiment of the present invention,
12 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention, and FIG.
13 is a view showing a semiconductor device according to an embodiment of the present invention.

Various embodiments of the present invention will be described in detail with reference to the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the following embodiments can be modified into various other forms, and the technical scope of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Also, to "include" an element means that it may include other elements, rather than excluding other elements, unless specifically stated otherwise. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the technical spirit of the present invention is not limited by the relative size or spacing depicted in the accompanying drawings.

Hereinafter, a semiconductor device according to various embodiments of the present invention, and a method for manufacturing a semiconductor device, will be described. In particular, the semiconductor device of the present invention can be realized as an element using a nitride semiconductor.

The nitride semiconductor is a semiconductor belonging to the III-V group semiconductor and containing nitrogen as the V group element. Gallium nitride (GaN), aluminum nitride (AIN), and indium nitride (InN). It is a wide-gap semiconductor having a larger band gap than that of the conventional semiconductor, and the bandgap can be largely changed by changing the concentration of gallium, indium and aluminum.

The semiconductor device in this specification uses such a nitride, and can be variously implemented as a transistor, a diode, and the like. Hereinafter, for ease of explanation, it is assumed that the semiconductor device is a transistor. Transistors control the current or voltage flow in an electronic circuit to amplify or act as a switch.

The term " deposition ", "growth ", and the like used hereinafter are used to mean the formation of a semiconductor material layer, and the layer or thin film formed through various embodiments of the present invention may be formed by an organometallic vapor deposition APCVD, LPCVD, UHCVD, PVD, electron beam (MOCVD), molecular beam epitaxy (MBE), and the like. Method, a resistance heating method, or the like. When the metal organic chemical vapor deposition (MOCVD) method is used, the flow rate of the gas injected into the MOCVD reaction chamber can be determined, and the thickness of the thin film grown according to the kind of the gas, the pressure inside the reaction chamber, The surface roughness, the doped concentration of the dopant, and the like. Particularly, the higher the temperature, the better the crystallinity of the thin film can be obtained, which should be limited in consideration of the physical properties of the reaction gas and the temperature at which the reaction occurs. In particular, ALD (Atomic layer deposition) can be used for precise growth. According to the ALD method, thin film growth can be controlled on an atomic basis.

As used herein, the term "semiconductor layer" refers to a layer composed of a semiconductor material and may be replaced by another term such as an epitaxial layer, a material layer, or the like.

1 to 7B are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, a substrate 100 is provided as shown in FIG. The substrate 100 is selected as a material capable of growing semiconductor material on its upper surface. In particular, if a nitride layer is intended to be grown, it is possible to have a hexagonal crystal system, for example a nitride layer sapphire (Al 2 O 3) used for the substrate, or a silicon carbide (SiC), silicon (Si), zinc oxide (ZnO), gallium arsenide (Ga), gallium nitride (GaN), spinel (MgAlO 4), such as a substrate material .

Then, the first semiconductor layer 110 is formed on the substrate 100 as shown in FIG. Meanwhile, a buffer layer (not shown) may be formed on the substrate 100 before the first semiconductor layer 110 is grown directly on the substrate 100.

The buffer layer serves as a buffer layer for reducing crystal defects caused by the inconsistency of the crystal lattice of the substrate 100 and a crystal grown thereon, and can serve as a resistive layer for preventing leakage of current when a high voltage is applied . For example, the buffer layer may comprise a layer of at least one of highly resistive GaN, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, It may be a layer made up of several kinds of nucleation layers. This buffer layer may be formed to a thickness of, for example, 2 mu m.

If a buffer layer is used, the first semiconductor layer 110 is formed on the buffer layer. The first semiconductor layer 110 may be composed of GaN. The first semiconductor layer 110 may be an undoped GaN layer, and in some cases, may be a doped GaN layer. Doping with a high concentration of n-type dopant reduces the series resistance of the device and allows the current to flow better. The first semiconductor layer 110 may be formed to a thickness of, for example, 60 nm.

The second semiconductor layer 120 is formed on the first semiconductor layer 110 as shown in FIG. The second semiconductor layer 120 includes a semiconductor material different from the first semiconductor layer 110. In particular, the material of the second semiconductor layer 120 may differ from the material of the first semiconductor layer 110 by at least one of polarization property, energy bandgap and lattice constant. For example, at least one of the polarization ratio and the energy band gap of the second semiconductor layer 120 may be larger than that of the first semiconductor layer 110. For example, the second semiconductor layer 120 may be an AlGaN layer or an AlN layer. The second semiconductor layer 120 may be an undoped layer, but in some cases it may be a doped layer with certain impurities. The thickness of the second semiconductor layer 120 may be 15 nm to 20 nm.

The second semiconductor layer 120 may be formed to form a two-dimensional electron gas (hereinafter, referred to as a 2DEG) on a part of one semiconductor layer 110. The 2DEG may be formed in a region of the first semiconductor layer 110 below the heterojunction interface between the first semiconductor layer 110 and the second semiconductor layer 120. The 2DEG formed in the first semiconductor layer 110 may be used as a current path or channel between the source electrode and the drain electrode to be formed in a subsequent process. 2DEG is 8.8 × 10 12 cm - can have an electron mobility of Figure 1 - 2 concentration, 1700 cm 2 · V -1 · s of.

The semiconductor device of the present invention is realized by a high electron mobility transistor (HEMT) using the 2DEG as a channel.

GaN / AlGaN or GaN / AlN heterojunction is used. However, the present invention is not limited thereto, and any combination of materials capable of forming a 2DEG layer at the heterojunction interface may fall within the scope of the present invention. It is obvious to those skilled in the art that a detailed description thereof will be omitted.

Next, a third semiconductor layer 130 doped with a p-type dopant is formed on the second semiconductor layer 120 as shown in FIG. The third semiconductor layer 130 may be a GaN or AlGaN layer doped with a p-type dopant such as Mg. The doping concentration may be 2 x 10 19 cm -3 . The thickness of the third semiconductor layer 130 may be 100 nm.

Then, a mask layer 140 having a predetermined pattern is formed on the third semiconductor layer 130 as shown in FIG. 2A. Specifically, the mask layer 140 having a predetermined pattern can be formed by using the exposure process. In this case, for example, an E-beam lithography technique can be used.

The pattern of the mask layer 140 includes a first region 20, a second region 22 spaced apart from the first region 20, and a third region 22 connecting the first region 20 and the second region 22. [ (21). The first region 20 and the second region 22 refer to the source structure and the drain structure upper region of the present semiconductor device and the third region 21 refers to the upper region of the channel structure of the present semiconductor device. Here, the channel structure is a structure that connects the source structure and the drain structure when viewed structurally, functions as a movement path of electrons when viewed functionally, and the source structure and the drain structure are connected by the channel structure. Refers to a portion that receives electrons or plays a role of discharging electrons to external elements. The third region 21 of the mask layer 140 may have a width of 500 nm and a length of 2 mu m (from the first region 20 to the second region 22). The thickness of the mask layer 140 may be 50 nm.

Mask layer 140 is SiO 2, SiN x (for example, Si 3 N 4) can be a dielectric or metal, Cr, Ni and the like, which cause a reaction in the etching solution used in the wet etching in a subsequent step It can be selected as a substance that does not exist.

On the other hand, FIG. 2A shows a part of the pattern of the mask layer 140, and is enlarged as shown in FIG. 2B. FIG. 2B illustrates a top view of the mask layer 140. FIG.

Referring to FIG. 2B, a flat zone or a notch is formed on the substrate 100, and the mask layer 140 is patterned in a direction perpendicular to the substrate as shown in FIG. 2B. That is, the third region 21 of the mask layer 140 is patterned to be perpendicular to the flat zone. The reason for this is to obtain a channel having a width of nano-size in the wet etching to be performed in the subsequent step, taking advantage of the fact that the etching rate is significantly faster than the plane in which the plane perpendicular to the flat zone is horizontal. 2C shows a cross section A-A 'corresponding to the third region 21 of the mask layer 140. FIG.

Next, the first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130 are dry-etched to have a predetermined channel structure, a drain structure, and a source structure. Dry etching can be performed with a plasma using a halogen gas such as chlorine (Cl 2 ), bromine (Br 2 ), or iodine (I 2 ). For example, TCP-RIE (transformer coupled plasma reactive ion etching) equipment can be used.

3, a structure in which the first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130 are stacked under the mask layer 140 is formed in a trapezoidal shape Structure. Dry etching is often the reason the side walls are not straight. Its slanted angle is ~ 65 °.

Therefore, although not essential, wet etching may be further performed to further narrow the width of the channel structure while vertically tilting the dry etched side walls according to an embodiment of the present invention.

Specifically, the third semiconductor layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 are formed to have a width smaller than the width of the mask layer formed thereon, ), The side surfaces of the second semiconductor layer 120 and the first semiconductor layer 110 are wet-etched with an etching solution. More specifically, the width of the third semiconductor layer 130, the second semiconductor layer 120, and the first semiconductor layer 110, which are disposed under the third region 21 of the mask layer 140 shown in FIG. 2A, Is wet etched so as to have a width smaller than the width of the third region 21 of the mask layer 140. The wet etching solution that can be used at this time is tetramethyl ammonium hydroxide (TMAH), and wet etching can be performed at a temperature of about 80 ° C.

Specifically, when the wet etching is performed, first, the lateral slopes of the dry etched third semiconductor layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 are perpendicular to each other as shown in FIG. 4 . This is because the etching rate of the upper region (region close to the mask layer 120) is slower than the lower region of the structure.

Then, as the wet etching time elapses, the width becomes narrow as shown in Fig. The reason for this selective etching in the lateral direction is that the anisotropic etching along the crystal planes of the Group III nitride semiconductor structures constituting the third semiconductor layer 130, the second semiconductor layer 120 and the first semiconductor layer 110 (anisotropic etch). Specifically, when wet etching is performed using a TMAH solution, the etching is performed only on the nitrogen face and not on the gallium face. The surface exposed by the dry etching in the previous step has a mostly nitrogen surface, so it can react strongly to the TMAH solution.

Since the direction of the side surfaces of the dry etched third semiconductor layer 130, the second semiconductor layer 120 and the first semiconductor layer 110 is perpendicular to the flat zone of the substrate 100, Etch rate. Accordingly, as the wet etching proceeds, the widths of the third semiconductor layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 in the channel structure become narrow as shown in FIG.

The width of the third semiconductor layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 in the channel structure can be effectively controlled by adjusting the wet time, . In the experiment, the channel structure was trapezoidal immediately after dry etching, the top width was 400 nm, and the bottom width was ~ 550 nm. Subsequently, wet etching was performed for 10, 25, 35 and 40 minutes respectively with TMAH solution (concentration 5%, 80 ° C). As a result, the width of the channel structure was reduced to 300, 200, 100 and 50 nm, respectively. The etch rate was measured at 8.5 to 9 nm / min.

In case of using dry etching only, it is very difficult to precisely fabricate the width of the channel structure to the nano level. However, according to the embodiment of the present invention in which dry etching and wet etching are performed together as described above, A fin-shaped channel structure can be obtained. In addition, wet etching may also achieve additional effects such that the dry etched surface is planarized and the plasma damage induced on the dry etched surface can be removed.

Then, the mask layer 140 is removed as shown in FIG. 6A. As a result, a channel structure composed of the third semiconductor layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 having a nano-sized width can be obtained. 6B shows the entire structure viewed from above after the mask layer 140 is removed. The channel structure is narrow in the middle, and the source structure and the drain structure are on both sides of the channel structure.

6B, the channel structure in which the third semiconductor layer 130, the second semiconductor layer 120, and the first semiconductor layer 110 are stacked has a vertical side slope and a very wide width due to wet etching. narrow. Preferably the width is nanosize.

Next, as shown in FIG. 7A, only the portion where the gate electrode is to be formed is contained, and the remaining portion of the third semiconductor layer 130 is removed. The remaining third semiconductor layer 131 may be disposed in an arbitrary region on the second semiconductor layer 120 in the channel structure. However, the length thereof should not exceed the length of the channel structure (the length in the direction from the drain structure to the source structure). Fig. 7B shows a cross-section (A-A ') of the structure shown in Fig. 7A.

8, the gate insulating layer 150 is formed to surround the first semiconductor layer 110, the second semiconductor layer 120, and the remaining third semiconductor layer 131 in the channel structure . The gate insulating layer 150 may be formed of a material selected from Al 2 O 3 , SiO 2 , Si 3 N 4 , HfO 2, and the like.

A source electrode (not shown) and a drain electrode (not shown) are formed on the second semiconductor layer 120 in the source structure and the drain structure, respectively. Or the source electrode and the drain electrode may be formed on the first semiconductor layer 110 through the second semiconductor layer 120. Alternatively, the source electrode and the drain electrode may be formed through the second semiconductor layer 120 and the first semiconductor layer 110. That is, the source electrode and the drain electrode are formed to contact at least the second semiconductor layer 120. According to one example, a source electrode and a drain electrode can be formed in the following manner. Specifically, except for a region (contact hole) in which a source electrode and a drain electrode are to be formed, a mask layer is deposited over the entire device. The electrode can be deposited using a tron-beam evaporator in the mask layer and the contact hole. The electrode may be composed of an Au / Ni / Al / Ti metal layer. The electrode is then subjected to rapid thermal annealing. At this time, the heat treatment is performed in an N 2 atmosphere at 500 ° C (20 sec) - 800 ° C (30 sec). When the mask layer is lifted through the lift-off process, the source electrode and the drain electrode can be formed in the contact hole region. A gate electrode 160 is formed between the source electrode and the drain electrode formed in this manner through a subsequent process.

Specifically, the gate electrode 160 is formed to surround the gate insulating layer 150 as shown in FIG. For example, the gate electrode 160 may be composed of an Au / Ni metal layer.

The completed semiconductor device 1000 has a 2DEG channel (i.e., Top channel) and side channels (i.e., Side-wall channels) as shown in FIG. Thus, on the I D -V G curve, two distinct transconductance peaks (g m ) can be observed, one due to the side channels and the other due to the 2DEG channel.

On the other hand, the energy bandgap of the portion of the first semiconductor layer 110 below the third semiconductor layer 131, which is doped with the p-type dopant, can be increased. As a result, The electron gas of the 2DEG of the layer 110 can be reduced. Therefore, when the device is driven, compared with the case where the remaining third semiconductor layer 131 is not provided, the residual third semiconductor layer 131 is provided, so that the threshold voltage V th is shifted in a positive direction . As the doping concentration of the remaining third semiconductor layer 131 increases, the degree to which V th is shifted increases. As a result, g m The peak can be shifted to the right by the residual third semiconductor layer 131 doped with the p type dopant, thereby realizing a normally off device using the 2DEG channel.

Since the semiconductor device 1000 can simultaneously use the 2DEG channel and the side channels, the number of electrons available in the device operation can be relatively increased, so that excellent device characteristics can be obtained. In addition, high-frequency and high- Also suitable for power devices.

On the other hand, another embodiment In order to ensure that the g m curve widely formed according to the invention (broad g m curve is to the device gatchwoya to be a good linearity satisfied, thereby minimizing the distortion between the input and the output.) Gate The thickness of the insulating film can be adjusted. This embodiment will be described with reference to FIG. 9 below.

9, the thickness T 1 of the gate insulating film 150 formed on the side surfaces of the first semiconductor layer 110, the second semiconductor layer 120, and the residual third semiconductor layer 131 in the channel structure is The gate insulating film 150 may be formed so as to be thicker than the thickness T 2 of the gate insulating film 150 formed on the upper surface of the third semiconductor layer 131 remaining in the channel structure.

In order for the g m curve to be formed wider, g m ( m) due to the 2DEG channel shifted to the right by the remaining third semiconductor layer 131 To avoid overlapping the peaks, g m The peak also needs to be moved to the right side. To this end, the side wall thickness T 1 of the gate insulating layer 150 is relatively thick. For example, the side thickness T 1 may be about 30 nm and the top thickness T 2 may be about 5 to 10 nm.

On the other hand, a gate insulating film may not be present on the upper surface of the remaining third semiconductor layer 131. Therefore, according to another embodiment of the present invention, the semiconductor device 1000 '' having no gate insulating film on the upper surface of the third semiconductor layer 131 as shown in FIG. 13 is possible. However, in order to prevent the gate leakage current and to further increase the gate voltage swing, it is preferable that the gate insulating film is present on the upper surface of the third semiconductor layer 131 remaining. In this case, g m The peak is shifted further to the right, causing g m Peak, it is preferable that the gate insulating film on the upper surface exists in a minimum thickness. In summary, the upper surface thickness T 2 of the gate insulating film 150 is formed to a minimum thickness, and the side thickness T 1 is formed to be relatively thick, whereby the above-described effects can be achieved.

In order to make the thicknesses of the gate insulating layer 150 on the upper surface and the side surface of the channel structure different from each other, specifically, the following process can be performed. First, on the side surfaces of the first semiconductor layer 110, the second semiconductor layer 120, and the remaining third semiconductor layer 131 in the channel structure and the upper surface of the remaining third semiconductor layer 131 in the channel structure, (150). The thickness of the gate insulating layer 150 formed on the upper surface of the third semiconductor layer 131 remaining in the channel structure is smaller than the thickness of the first semiconductor layer 110, the second semiconductor layer 120, The gate insulating layer 150 formed on the upper surface of the third semiconductor layer in the channel structure is etched so as to have a predetermined thickness smaller than the thickness of the gate insulating layer 150 formed on the side surface of the layer 131. Dry etching can be used at this time.

In another embodiment, the gate insulating film 150 having different thicknesses of the side surface and the upper surface may be formed in a different manner. According to the present embodiment, the side surfaces of the first semiconductor layer 110, the second semiconductor layer 120, and the remaining third semiconductor layer 131 in the channel structure and the remaining third semiconductor layer 131 in the channel structure, Thereby forming a gate insulating film. 10, the gate insulating film formed on the side surfaces of the first semiconductor layer 110, the second semiconductor layer 120, and the remaining third semiconductor layer 131 in the channel structure is left, and the remaining third The gate insulating film formed on the upper surface of the semiconductor layer 131 is removed. Dry etching can be used at this time. Instead of exposing the upper surface of the remaining third semiconductor layer 131 by removing the gate insulating film, the gate insulating film may remain on the upper surface of the remaining third semiconductor layer 131 to a predetermined thickness.

11, an additional gate insulating film 151 is formed on the remaining upper surface of the third semiconductor layer 131 and on the remaining gate insulating film 150. Next, as shown in FIG. As a result, the thickness T 1 of the side surface of the two-layered gate insulating film becomes larger than the thickness T 2 of the top portion of the one-layered gate insulating film.

The above-described steps may be repeated to form a thicker gate insulating film on the side surface.

The conventional gate insulating layer 150 and the additional gate insulating layer 151 may be formed of the same material.

It will be appreciated by those skilled in the art that, based on the teachings herein, it is possible to select details such as the optimum semiconductor material, thickness of the gate insulating film, doping concentration, etc. to obtain a wide g m curve through experiments, As well as the degree to which it is obvious to those skilled in the art. Therefore, although the material of the semiconductor device, the thickness of the gate insulating film, the doping concentration, and the like are specified in the above-described embodiments, this is only a few examples for facilitating the understanding of the present invention and the scope of the present invention is limited thereto It should not be understood.

13 shows a semiconductor device 2000 according to an embodiment of the present invention. 13 will not be described in detail with respect to portions overlapping with the above-described components.

13, the semiconductor device 2000 includes a substrate 100, a first semiconductor layer 110, a second semiconductor layer 120, a remaining third semiconductor layer 131, a gate insulating layer 150, A gate electrode 160, a source electrode 170, and a drain electrode 180. Although not shown in FIG. 13, a buffer layer may be disposed between the substrate 100 and the first semiconductor layer 110. The buffer layer serves as a buffer layer for reducing crystal defects caused by the inconsistency of the crystal lattice of the substrate 100 and a crystal grown thereon, and can serve as a resistive layer for preventing leakage of current when a high voltage is applied . For example, the buffer layer may be a layer made of at least one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN, or a layer made of various kinds of nucleation layers for stepwise reducing crystal defects arising from lattice mismatch with the substrate .

The semiconductor device 2000 can be divided into a source structure portion S, a channel structure portion C, and a drain structure portion D. The channel structure portion C operates as a path through which electrons can move when the semiconductor element 2000 is in an on state and conversely acts to prevent current leakage when the semiconductor element 2000 is off So as to prevent the movement of the charge.

The channel structure portion C is formed by stacking the first semiconductor layer 110, the second semiconductor layer 120 and the remaining third semiconductor layer 131, (Not shown). As described above with reference to FIGS. 8, 9 and 12, the thickness of the gate insulating film of the channel structure portion C may be variously selected according to the embodiment.

In particular, as described above, the channel structure portion C can operate using both the 2DEG channel and the sidewall channel, and when the device is driven according to the thickness of the gate insulating film, the 2DEG channel and the sidewall channel are combined to obtain a wide g m peak have.

The source electrode 170 is a structure for electrically connecting an external element and the present semiconductor element 2000 to supply a carrier (electron or hole) to the semiconductor element 2000. The drain electrode 180 serves as a path through which the carriers supplied from the source electrode 160 move to the external device. The source electrode 170 and the drain electrode 180 are formed of an Au / Ni / Al / Ti metal layer for forming an ohmic contact with the first semiconductor layer 110 and / or the second semiconductor layer 120 . Here, an ohmic contact is a non-rectifying or resistive contact, in which the I-V curve follows the general Ohm's law.

The gate electrode 160 is configured such that a voltage for controlling on / off operation of the semiconductor device 2000 can be applied. As the semiconductor device (2000) according to the present invention described above, and g m peaks of the 2DEG channel is moved to the right, because of the wide g m curve merged g m peaks of the side wall channel, to get a good linearity in a relatively wide voltage range, .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It goes without saying that the example can be variously changed. Accordingly, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. * * * * * Recently Added Patents

100: substrate 110: first semiconductor layer
120: second semiconductor layer 130: third semiconductor layer

Claims (13)

  1. A method of manufacturing a semiconductor device,
    Forming a first semiconductor layer on the substrate;
    Forming a second semiconductor layer on the first semiconductor layer to induce a two-dimensional electron gas (2DEG) on the first semiconductor layer;
    Forming a third semiconductor layer doped with a p-type dopant on the second semiconductor layer;
    Etching a structure in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked so as to have a predetermined source structure, a drain structure, and a channel structure;
    A gate insulating film is formed so as to cover the exposed side of the first semiconductor layer, the exposed side of the second semiconductor layer and the exposed side of the third semiconductor layer in the channel structure and the upper surface of the third semiconductor layer in the channel structure ; And
    And forming a gate electrode on the gate insulating film.
  2. The method according to claim 1,
    Wherein forming the gate insulating film comprises:
    The gate insulating film is formed so that the thickness of the gate insulating film formed on the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure is larger than the thickness of the gate insulating film formed on the upper surface of the third semiconductor layer in the channel structure Wherein the semiconductor device is a semiconductor device.
  3. The method according to claim 1,
    Wherein forming the gate insulating film comprises:
    Forming a first gate insulating film on side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure and on a top surface of the third semiconductor layer in the channel structure;
    Removing a first gate insulating film formed on a top surface of a third semiconductor layer in the channel structure while leaving a first gate insulating film formed on sides of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure; And
    And forming a second gate insulating film on the upper surface of the third semiconductor layer in the channel structure and on the first gate insulating film.
  4. The method according to claim 1,
    Wherein forming the gate insulating film comprises:
    Forming a gate insulating film on the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure and the upper surface of the third semiconductor layer in the channel structure; And
    The thickness of the gate insulating film formed on the upper surface of the third semiconductor layer in the channel structure has a predetermined thickness smaller than the thickness of the gate insulating film formed on the side surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure And etching the gate insulating film formed on the third semiconductor layer in the channel structure.
  5. The method according to claim 1,
    Wherein the step of etching comprises:
    A mask layer having a pattern corresponding to the predetermined source structure, drain structure, and channel structure is formed on the third semiconductor layer, and a structure in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked Dry etching;
    Wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer in the channel structure have a width smaller than a width of the mask layer formed on the third semiconductor layer in the channel structure, Wet etching the sides of the second semiconductor layer and the third semiconductor layer with an etching solution; And
    And removing the mask layer. ≪ Desc / Clms Page number 19 >
  6. 6. The method of claim 5,
    Wherein the etching solution is a tetra-methyl ammonium hydroxide (TMAH) solution.
  7. The method according to claim 1,
    Forming a source electrode in contact with the second semiconductor layer in the source structure, and forming a drain electrode in contact with the second semiconductor layer in the drain structure.
  8. The method according to claim 1,
    Wherein the first semiconductor layer is made of GaN, and the second semiconductor layer is made of AlGaN or AlN.
  9. In a semiconductor device,
    A source structure in which a first semiconductor layer and a second semiconductor layer are stacked;
    A drain structure spaced apart from the source structure and including a first semiconductor layer and a second semiconductor layer stacked;
    A channel structure that connects the source structure and the drain structure and includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer doped with a p-type dopant;
    A gate insulating film surrounding the exposed side of the first semiconductor layer, the exposed side of the second semiconductor layer and the exposed side of the third semiconductor layer in the channel structure, and the upper surface of the third semiconductor layer in the channel structure; And
    And a gate electrode disposed on the gate insulating film.
  10. 10. The method of claim 9,
    Wherein the gate insulating film
    Wherein the channel structure is formed thicker on a side surface of the channel structure than an upper surface of the channel structure.
  11. 10. The method of claim 9,
    The gate electrode
    And the gate insulating film is disposed so as to surround all of predetermined regions of the exposed surfaces of the gate insulating film.
  12. 10. The method of claim 9,
    Wherein the first semiconductor layer is made of GaN, and the second semiconductor layer is made of AlGaN or AlN.
  13. 10. The method of claim 9,
    A source electrode disposed on the source structure; And
    And a drain electrode disposed on the drain structure.

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101031798B1 (en) * 2009-12-30 2011-04-29 경북대학교 산학협력단 3d nitride resonant tunneling semiconductor device and manufacturing method thereof
KR101452122B1 (en) * 2013-03-08 2014-10-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Finfet with strained well regions

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Publication number Priority date Publication date Assignee Title
KR20050006836A (en) * 2003-07-10 2005-01-17 삼성전자주식회사 Method for forming a semiconductor device
KR100591770B1 (en) * 2004-09-01 2006-06-26 삼성전자주식회사 Flash memory device using a semiconductor fin and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101031798B1 (en) * 2009-12-30 2011-04-29 경북대학교 산학협력단 3d nitride resonant tunneling semiconductor device and manufacturing method thereof
KR101452122B1 (en) * 2013-03-08 2014-10-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Finfet with strained well regions

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