KR101670238B1 - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device Download PDF

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KR101670238B1
KR101670238B1 KR1020150041413A KR20150041413A KR101670238B1 KR 101670238 B1 KR101670238 B1 KR 101670238B1 KR 1020150041413 A KR1020150041413 A KR 1020150041413A KR 20150041413 A KR20150041413 A KR 20150041413A KR 101670238 B1 KR101670238 B1 KR 101670238B1
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semiconductor layer
layer
semiconductor
trench
forming
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KR1020150041413A
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Korean (ko)
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KR20160114922A (en
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이정희
강희성
김륜휘
조영우
손동혁
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경북대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
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Abstract

A semiconductor device manufacturing method is disclosed. The method includes the steps of: providing a first semiconductor layer; dry-etching the first semiconductor layer by forming a mask layer having a predetermined width on the first semiconductor layer; dry etching the first semiconductor layer; Wet etching the side surface of the first semiconductor layer that has been dry etched so as to have a smaller width, removing the mask layer, etching the first semiconductor layer by dry etching and wet etching, Etching the first semiconductor layer to form a trench, and forming a gate electrode having a contact region wider than the width of the trench.

Description

Technical Field [0001] The present invention relates to a method of manufacturing a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a T-shaped gate.

In a high-speed device such as a high electron mobility transistor (HEMT), which is mainly used in a satellite broadcast receiver, a high-speed logic circuit, and a power module, a gate length is required for a high modulation operation, A large area pattern is required for the passage.

Accordingly, a T-shaped gate having a cross-sectional shape of "T" is used. Such a T-shaped gate includes a gate head and a gate foot, and can maintain a small gate resistance while reducing the width of the gate foot. Are widely used in semiconductor devices based on III-V compounds.

In order to make the T-shaped gate have a nano-sized gate foot, electron beam lithography is used. In order to manufacture a T-shaped gate having a nano-sized gate foot using an electron beam exposure process An exposing process must be performed using an electron beam having an acceleration voltage of approximately 100 keV, which is costly and requires a high acceleration voltage to damage the semiconductor substrate.

Accordingly, there is a need for a method of manufacturing a T-shaped gate with a simpler process without damage to the substrate.

The present invention has been devised in view of the above-mentioned needs, and an object of the present invention is to provide a method of manufacturing a semiconductor device having a n-sized T-shaped gate.

According to another aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising: providing a first semiconductor layer; forming a mask layer having a predetermined width on the first semiconductor layer, Etching the first semiconductor layer by dry etching, wet etching the side surface of the dry-etched first semiconductor layer so that the width of the first semiconductor layer is smaller than the width of the mask layer, removing the mask layer Forming an insulating layer having a predetermined height at a portion where the first semiconductor layer is removed by the dry etching and the wet etching; etching the first semiconductor layer to form a trench; And forming a gate electrode having a contact region wider than the width of the trench.

In this case, the step of dry etching may be performed such that the height of the first semiconductor layer corresponding to the portion where the mask layer is not formed is lower than the height of the first semiconductor layer corresponding to the portion where the mask layer is formed, 1 < / RTI > semiconductor layer.

In this case, the semiconductor device manufacturing method according to the present embodiment may further include the step of forming the source electrode and the drain electrode on the first semiconductor layer having the low height.

Meanwhile, the step of providing the first semiconductor layer may include forming the first semiconductor layer on the second semiconductor layer.

In this case, the step of forming the trench may be to form the trench so that the second semiconductor layer having a certain height exists under the trench.

Meanwhile, the second semiconductor layer may have a structure in which a third semiconductor layer is stacked on the fourth semiconductor layer.

In this case, the third semiconductor layer may be made of GaN, and the fourth semiconductor layer may be made of AlGaN or AlN.

On the other hand, the step of forming the trench may be to form the trench to pass through the third semiconductor layer.

The step of forming the insulating layer may include depositing an insulating layer on a portion of the first semiconductor layer where the first semiconductor layer is removed by the dry etching and the wet etching, Depositing a photoresist in a coating manner, and performing a dry etch to remove the photoresist and the insulating layer deposited within a range exceeding the predetermined height.

Meanwhile, the first semiconductor layer may be doped with an n-type dopant.

Meanwhile, the wet etching may be performed by wet etching using a tetra-methyl ammonium hydroxide (TMAH) solution.

FIGS. 1A to 9 are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention,
10 to 12 are views for explaining a semiconductor device manufactured according to a method of manufacturing a semiconductor device according to various embodiments of the present invention.

Various embodiments of the present invention will be described in detail with reference to the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the following embodiments can be modified into various other forms, and the technical scope of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Also, to "include" an element means that it may include other elements, rather than excluding other elements, unless specifically stated otherwise. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the technical spirit of the present invention is not limited by the relative size or spacing depicted in the accompanying drawings.

Hereinafter, a semiconductor device according to various embodiments of the present invention, and a method for manufacturing a semiconductor device, will be described. In particular, the semiconductor device of the present invention can be realized as an element using a nitride semiconductor.

The nitride semiconductor is a semiconductor belonging to the III-V group semiconductor and containing nitrogen as the V group element. Gallium nitride (GaN), aluminum nitride (AIN), and indium nitride (InN). It is a wide-gap semiconductor having a larger band gap than that of the conventional semiconductor, and the bandgap can be largely changed by changing the concentration of gallium, indium and aluminum.

The semiconductor device in this specification uses such a nitride, and can be variously implemented as a transistor, a diode, and the like. Hereinafter, for ease of explanation, it is assumed that the semiconductor device is a transistor. Transistors control the current or voltage flow in an electronic circuit to amplify or act as a switch.

The term " deposition ", "growth ", and the like used hereinafter are used to mean the formation of a semiconductor material layer, and the layer or thin film formed through various embodiments of the present invention may be formed by an organometallic vapor deposition APCVD, LPCVD, UHCVD, PVD, electron beam (MOCVD), molecular beam epitaxy (MBE), and the like. Method, a resistance heating method, or the like. When the metal organic chemical vapor deposition (MOCVD) method is used, the flow rate of the gas injected into the MOCVD reaction chamber can be determined, and the thickness of the thin film grown according to the kind of the gas, the pressure inside the reaction chamber, The surface roughness, the doped concentration of the dopant, and the like. Particularly, the higher the temperature, the better the crystallinity of the thin film can be obtained, which should be limited in consideration of the physical properties of the reaction gas and the temperature at which the reaction occurs. In particular, ALD (Atomic layer deposition) can be used for precise growth. According to the ALD method, thin film growth can be controlled on an atomic basis.

As used herein, the term "semiconductor layer" refers to a layer composed of a semiconductor material and may be replaced by another term such as an epitaxial layer, a material layer, or the like.

1A to 9 are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, a first semiconductor layer 110 is formed as shown in FIG. The first semiconductor layer 110 may be formed on a substrate, a buffer layer, or a second semiconductor layer 120 of a material different from the first semiconductor layer 110.

The first semiconductor layer 110 and the second semiconductor layer 120 may be an undoped GaN layer or a GaN layer doped with a predetermined impurity in some cases.

Then, a mask layer 150 having a predetermined width is formed on the first semiconductor layer 110 as shown in FIG. 1A. Specifically, the mask layer 150 having a predetermined pattern can be formed by using the exposure process. In this case, for example, an E-beam lithography technique can be used. Mask layer 150 is SiO 2, SiN x (for example, Si 3 N 4) can be a dielectric or metal, Cr, Ni and the like, which cause a reaction in the etching solution used in the wet etching in a subsequent step It can be selected as a substance that does not exist.

1B is a top view of the first semiconductor layer 110 with a mask layer 150 formed thereon. The arrangement direction of the mask layer 150 can be determined based on a flat zone or a notch of the substrate 100 on which the crystal growth of the first semiconductor layer 110 is based as shown in FIG. have. That is, as shown in FIG. 1B, the shape of the mask layer 150 is long in a direction perpendicular to the flat zone or notch of the substrate 100, 1 < / RTI > The reason why the arrangement direction of the mask layer 150 is determined in this manner is that the first semiconductor layer 110 to be performed in the subsequent step is formed by using the fact that the etching rate is significantly faster than the plane in which the plane perpendicular to the flat zone is horizontal, In order to obtain a structure having a width of nano-size through wet etching.

1C shows a cross-section (A-A ') of the structure shown in FIG. 1A.

Then, the first semiconductor layer 110 under the mask layer 150 is dry-etched as shown in FIG. Dry etching can be performed with a plasma using a halogen gas such as chlorine (Cl 2 ), bromine (Br 2 ), or iodine (I 2 ). For example, TCP-RIE (transformer coupled plasma reactive ion etching) equipment can be used.

The first semiconductor layer 110 corresponding to the portion where the mask layer 150 is not formed is higher than the height of the first semiconductor layer 110 corresponding to the portion where the mask layer 150 is formed, The first semiconductor layer 110 is dry-etched so that the height of the first semiconductor layer 110 is low. The reason for leaving a part of the first semiconductor layer 110 corresponding to the portion where the mask layer 150 is not formed is that the first semiconductor layer 110 is a semiconductor layer doped heavily with an n- N ++ GaN), a low resistance ohmic contact is formed between the source electrode (not shown) and the drain electrode (not shown) to be formed in a subsequent step.

When the dry etching is performed, the first semiconductor layer 110 under the mask layer 150 may have a trapezoidal shape as shown in FIG. That is, most of the side walls of the first semiconductor layer 110 are not straight as shown in FIG. 2 only by dry etching. Its slanted angle is ~ 65 °. Thus, a wet etch is further performed to further narrow the width while making the slope of the dry etched sidewalls vertical.

Specifically, wet etching can be performed using a tetra-methyl ammonium hydroxide (TMAH) solution. When the wet etching is performed, first, the side inclination of the dry-etched first semiconductor layer 110 becomes perpendicular as shown in FIG. This is because the etching rate of the upper region (the region close to the mask layer 150) is slower than the lower region of the structure.

Then, as the wet etching time elapses, the width becomes narrow as shown in Fig. The reason why it can be selectively etched only in the lateral direction is attributed to the anisotropic etch characteristic along the crystal planes of the Group III nitride semiconductor structures constituting the first semiconductor layer 110. Specifically, when wet etching is performed using a TMAH solution, the etching is performed only on the nitrogen face and not on the gallium face. The surface exposed by the dry etching in the previous step has a mostly nitrogen surface, so it can react strongly to the TMAH solution.

In addition, since the direction of the side surface of the dry-etched first semiconductor layer 110 is perpendicular to the flat zone of the substrate 100, it has a higher etch rate than the horizontal surface. Accordingly, as the wet etching proceeds, the width of the first semiconductor layer 110 becomes narrow as shown in FIG.

On the other hand, as a result of experiments with different wet etching times, it was found that the width can be effectively controlled by controlling the wet time. In the experiment, immediately after dry etching, the structure was trapezoidal in shape, with an upper width of 400 nm and a lower width of ~ 550 nm. Then, wet etching was performed for 10, 25, 35 and 40 minutes respectively with TMAH solution (concentration 5%, 80 ° C), and the width of the structure was reduced to 300, 200, 100 and 50 nm, respectively. The etch rate was measured at 8.5 to 9 nm / min. As the etch rate increased, the width decreased further and the width was reduced to less than 10 nm.

It is very difficult to precisely fabricate the width of the semiconductor layer to a nano level. However, according to the embodiment of the present invention which performs both the dry etching and the wet etching as described above, the width of the nano- Can be obtained. In addition, wet etching may also achieve additional effects such that the dry etched surface is planarized and the plasma damage induced on the dry etched surface can be removed.

As a result, the first semiconductor layer 110 having a nano-sized width smaller than the width of the mask layer 150 can be obtained.

Then, the mask layer 150 is removed as shown in FIG.

Next, an insulating layer having a predetermined height is formed at a portion where the first semiconductor layer 110 is removed by dry etching and wet etching. Specifically, the insulating layer can be formed through the following steps.

First, as shown in FIG. 6, an insulating layer 160 is deposited on a portion where the first semiconductor layer 110 has been removed by dry etching and wet etching, and on the first semiconductor layer 110. Insulating layer 160 may be configured to be selected from an insulating material such as SiO 2, Al 2 O 3, Si 3 N 4, HfO 2.

Then, a photoresist 170 is deposited on the insulating layer 160 as shown in FIG. The photoresist 170 may be deposited by a spin coating method. Spin coating is a coating method based on the principle that the fluid is spread by centrifugal force as the substrate is rotated at a very high speed. Since the photoresist has a constant viscosity, it can be applied relatively thick to the protruding region and relatively thick to the non-protruding region, depending on the nature of such photoresist when applied by a spin coating method. 7, a photoresist 170 is thinly deposited on the protruding portion of the first semiconductor layer 110 having a width of nano-size, and a photoresist 170 is formed on the other non- Is relatively thick.

Then, dry etching is performed so that the insulating layer 160 is flattened. When the photoresist 170 and the insulating layer 160 are sequentially removed by performing the dry etching using the property that the photoresist 170 is deposited with the step difference, the photoresist 170 and the photoresist 170, as shown in FIG. 8, The insulating layer 160 deposited within a range exceeding a certain height may be removed and the insulating layer 160 may be planarized.

This dry etching can be performed until the protruding upper surface of the first semiconductor layer 110 is exposed. In the process, only the photoresist 170 is etched and the insulating layer 160 under the photoresist 170 is protected in the portion where the photoresist 170 is relatively thickly deposited. That is, after the dry etching is completed as shown in FIG. 8, the insulating layer 160 having a certain height may remain next to the protruded structure of the first semiconductor layer 110. In this case, according to one embodiment, the first semiconductor layer 110 and the insulating layer 160 are formed to have the same height.

The first semiconductor layer 110 having a width of nano-size is formed in the insulating layer 160 by dry etching without complicated processes, by using the property that the photoresist 170 is deposited with a step difference by spin coating, Can be disposed.

Next, as shown in FIG. 9, the first semiconductor layer 110 is etched to form a trench 90. More specifically, the trench 90 can be formed by dry etching using a gas having a larger etch selectivity with respect to the first semiconductor layer 110 than the insulating layer 160. For example, when the first semiconductor layer 110 is made of GaN and the insulating layer 160 is made of SiO 2 or SiN, the Cl system can be etched using gas.

As described above, the etching using the etching selectivity can precisely etch only the portion where the first semiconductor layer 110 is disposed, so that the nano-sized width (10 nm or less) corresponding to the width of the first semiconductor layer 110, The trench 90 can be formed. Even with the conventional E-beam lithography method, it is almost impossible to form the trench having such an extremely fine width.

Then, the gate electrode material is filled in the trench 90 to obtain a T-shaped gate electrode 180 as shown in FIGS. 10 to 12. FIG. This type of gate electrode is commonly referred to as a T-shaped gate (or T-gate). The T-shaped gate is composed of a gate head (contact region) and a gate bridge, and is characterized in that the width of the gate head is larger than the width of the gate leg.

According to one example, the following steps may be performed to form the gate electrode 180 of this type. 8, in a state where the insulating layer 160 is disposed beside the protruded portion of the first semiconductor layer 110, a predetermined period of time to cover the protruded upper surface of the first semiconductor layer 110 and the insulating layer 160 The resist of the height is deposited. Then, in the lithography process, the resist corresponding to the region including the projected upper surface of the first semiconductor layer 110, that is, the region where the gate head is to be formed, is removed. Then, the first semiconductor layer 110 is etched to form a trench 90 as shown in FIG. Then, a gate metal (for example, titanium, platinum, or gold formed sequentially from the bottom) is deposited so as to fill the resist-removed portion and the trench 90, and is coated on the resist and resist using a resist solution The gate electrode 180 of the T-type can be formed.

According to the semiconductor device manufacturing method of the above-described embodiments, it is possible to manufacture a semiconductor device having a T-shaped gate electrode having a width of nano size (for example, 10 nm or less) which is difficult to be realized by an E-beam lithography method .

10 to 12 illustrate various types of semiconductor devices including the gate electrode 180 manufactured according to the above-described method.

FIG. 10 illustrates a semiconductor device manufactured according to a method of manufacturing a semiconductor device according to an embodiment of the present invention.

10, a semiconductor device 1000 includes a buffer layer 101, a second semiconductor layer 120, a first semiconductor layer 110, an insulating layer 160, a gate electrode 180, a source electrode 191, And a drain electrode 193.

The buffer layer 101 serves as a buffer layer for reducing crystal defects caused by the incoincidence of crystal lattice of the substrate (not shown) and the crystal lattice of the material grown thereon, and serves as a resistance layer for preventing current leakage when a high voltage is applied can do. For example, the buffer layer 101 may be formed of a layer consisting of at least one of highly resistive GaN, GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN, The layer may consist of several kinds of nucleation layers to reduce the number of nucleation layers. Meanwhile, the buffer layer 101 may have an arbitrary structure, and the second semiconductor layer 120 may be formed directly on the substrate (not shown).

The second semiconductor layer 120 is formed on the buffer layer 101 (or the substrate). The second semiconductor layer 120 may be an undoped GaN layer and may be a doped GaN layer in some cases. The second semiconductor layer 120 may operate as a channel region when driving the device.

The first semiconductor layer 110 is formed on the second semiconductor layer 120. The first semiconductor layer 110 may be an undoped GaN layer, and in some cases, may be a doped GaN layer. The first semiconductor layer 110 is a layer remaining after the dry etching and the wet etching as described with reference to FIGS. That is, the first semiconductor layer 110 is used for forming the gate electrode 180, and the source electrode 191 and the drain (not shown) when the first semiconductor layer 110 is a high concentration n-type doped GaN layer (N ++ GaN) It is possible to form ohmic of a low resistance of the electrode 193, so that it can have a low on resistance.

The insulating layer 180 is disposed under the gate electrode 180. The insulating layer 180 may be made of an insulating material such as SiO 2 , Al 2 O 3 , Si 3 N 4 , HfO 2, or the like. The insulating layer 180 serves as a field plate for dispersing the field of the edge portion of the gate electrode 180 on the drain electrode 193 side. Therefore, the breakdown voltage of the semiconductor device 1000 can be increased, so that a high voltage can be applied to the semiconductor device 1000.

The gate electrode 180 is configured such that a voltage for controlling on / off operation of the semiconductor device 1000 can be applied. In particular, the gate foot portion of the gate electrode 180 may have a nano size, for example, a width of 10 nm or less. Therefore, the microwave characteristics such as the oscillation frequency and the current gain cut-off frequency of the semiconductor device 1000 can be improved. By having a gate head region wider than the gate gate portion of the gate electrode 180, an increase in the gate resistance can be prevented.

The source electrode 191 is disposed on the first semiconductor layer 110 in such a manner as to supply carriers (electrons or holes) to the semiconductor element 1000 by electrically connecting the external element and the present semiconductor element 1000 .

The drain electrode 193 is disposed on the first semiconductor layer 110 with the gate electrode 180 therebetween and spaced apart from the source electrode 191. The drain electrode 193 serves as a channel through which the carrier supplied from the source electrode 191 is moved to the external device.

The source electrode 191 and the drain electrode 193 may be formed of an Au / Ni / Al / Ti metal layer for forming an ohmic contact with the first semiconductor layer 110. Here, an ohmic contact is a non-rectifying or resistive contact, in which the I-V curve follows the general Ohm's law.

According to one example, the source electrode 191 and the drain electrode 193 can be formed in the following manner. Specifically, a mask layer is formed over the entire device except the region (contact hole) where the source electrode 191 and the drain electrode 193 are to be formed. The electrode can be deposited using a tron-beam evaporator in the mask layer and the contact hole. The electrode may be composed of an Au / Ni / Al / Ti metal layer. The electrode is then subjected to rapid thermal annealing. At this time, the heat treatment can be performed in an N 2 atmosphere at 500 ° C (20 sec) - 800 ° C (30 sec). When the mask layer is lifted through the lift-off process, the source electrode 191 and the drain electrode 193 can be formed in the contact hole region.

FIG. 11 illustrates a semiconductor device manufactured according to a method of manufacturing a semiconductor device according to another embodiment of the present invention.

11, a semiconductor device 1000 'includes a buffer layer 101, a fourth semiconductor layer 140, a third semiconductor layer 130, a first semiconductor layer 110, an insulating layer 160, A source electrode 191, and a drain electrode 193, as shown in FIG. The description of the configuration of the semiconductor device 1000 'that overlaps with the semiconductor device 1000 described above is replaced with the one described above.

The fourth semiconductor layer 140 is formed on the buffer layer 101 and may be composed of GaN. The fourth semiconductor layer 140 may be an undoped GaN layer, or may be a GaN layer doped with a predetermined impurity.

The third semiconductor layer 130 is formed on the fourth semiconductor layer 140 and includes a semiconductor material different from the fourth semiconductor layer 140. The material of the third semiconductor layer 130 may be different from that of the fourth semiconductor layer 140 in at least one of polarization, energy bandgap and lattice constant. For example, at least one of the polarization ratio and the energy band gap of the third semiconductor layer 130 may be larger than that of the fourth semiconductor layer 140. For example, the third semiconductor layer 130 may be an AlGaN layer or an AlN layer. The third semiconductor layer 130 may be an undoped layer, but in some cases it may be a doped layer with certain impurities.

A second dimension electron gas (hereinafter, referred to as 2DEG) may be formed on a part of the fourth semiconductor layer 140 by forming the third semiconductor layer 130. The 2DEG may be formed in a region of the fourth semiconductor layer 140 below the heterojunction interface between the third semiconductor layer 130 and the fourth semiconductor layer 140. The 2DEG formed in the fourth semiconductor layer 140 may be used as a current path between the source electrode 191 and the drain electrode 193, that is, as a channel. 2DEG is 8.8 × 10 12 cm - can have an electron mobility of Figure 1 - 2 concentration, 1700 cm 2 · V -1 · s of.

GaN / AlGaN or GaN / AlN heterojunction is used. However, the present invention is not limited thereto, and any combination of materials capable of forming a 2DEG layer at the heterojunction interface may fall within the scope of the present invention. It is obvious to those skilled in the art that a detailed description thereof will be omitted.

The semiconductor device 1000 'manufactured according to the present embodiment is a high electron mobility transistor (HEMT) using the 2DEG as a channel. In particular, it is a HEMT in a normally on state.

On the other hand, according to another embodiment, it is possible to manufacture a HEMT in a normally off state. This embodiment will be described with reference to FIG. 12 below.

The first semiconductor layer 110 is formed on the third semiconductor layer 130. The first semiconductor layer 110 may be an undoped GaN layer, and in some cases, may be a doped GaN layer. The first semiconductor layer 110 is a layer remaining after the dry etching and the wet etching as described with reference to FIGS. That is, the first semiconductor layer 110 is used for forming the gate electrode 180. When the first semiconductor layer 110 is a high concentration n-type doped GaN layer (N ++ GaN), the source electrode 191 and the drain electrode It is possible to form a low resistance ohmic layer 193 having a low ON resistance.

12 illustrates a semiconductor device manufactured according to a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 12, a semiconductor device 1000 '' includes a buffer layer 101, a fourth semiconductor layer 140, a third semiconductor layer 130, a first semiconductor layer 110, an insulating layer 160, An electrode 180, a source electrode 191, and a drain electrode 193.

In order to manufacture the semiconductor device 1000 '', a buffer layer 101 is first provided. The buffer layer 101 serves as a buffer layer for reducing crystal defects caused by the incoincidence of crystal lattice of the substrate (not shown) and the crystal lattice of the material grown thereon, and serves as a resistance layer for preventing current leakage when a high voltage is applied can do. For example, the buffer layer 101 may be formed of a layer consisting of at least one of highly resistive GaN, GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN, The layer may consist of several kinds of nucleation layers to reduce the number of nucleation layers. Meanwhile, the buffer layer 101 may have an optional structure, and the fourth semiconductor layer 140 may be formed directly on the substrate (not shown).

Next, a fourth semiconductor layer 140 is formed on the buffer layer 101 (or the substrate). The fourth semiconductor layer 140 may be composed of GaN. The fourth semiconductor layer 140 may be an undoped GaN layer, or may be a GaN layer doped with a predetermined impurity.

Next, a third semiconductor layer 130 is formed on the fourth semiconductor layer 140. The third semiconductor layer 130 includes a semiconductor material different from the fourth semiconductor layer 140. The material of the third semiconductor layer 130 may be different from that of the fourth semiconductor layer 140 in at least one of polarization, energy bandgap and lattice constant. For example, at least one of the polarization ratio and the energy band gap of the third semiconductor layer 130 may be larger than that of the fourth semiconductor layer 140. For example, the third semiconductor layer 130 may be an AlGaN layer or an AlN layer. The third semiconductor layer 130 may be an undoped layer, but in some cases it may be a doped layer with certain impurities.

A second dimension electron gas (hereinafter, referred to as 2DEG) may be formed on a part of the fourth semiconductor layer 140 by forming the third semiconductor layer 130. The semiconductor device 1000 'manufactured according to the present embodiment is a high electron mobility transistor (HEMT) using the 2DEG as a channel.

The first semiconductor layer 110 is formed on the third semiconductor layer 130. The first semiconductor layer 110 may be an undoped GaN layer, and in some cases, may be a doped GaN layer. In particular, the first semiconductor layer 110 may be a semiconductor layer doped with a high concentration of n-type dopant (e.g., N ++ GaN). In this case, ohmic contact with low resistance between the source electrode 191 and the drain electrode 193 can be formed.

Then, as described above with reference to FIGS. 1C to 5, the first semiconductor layer is dry-etched and wet-etched to form a protruding structure having a nano-sized width.

Next, as described above with reference to FIGS. 6 to 8, an insulating layer 160 is formed next to the protruding structure of the first semiconductor layer 110 having a nano-sized width.

A source electrode 191 and a drain electrode 193 are formed in the first semiconductor layer 110.

After the resist is applied to the entire device, the resist corresponding to the region where the gate head is to be formed is removed. This region is an area including the upper surface of the protruded structure of the first semiconductor layer 110. [

Then, the first semiconductor layer 110 is etched through the region where the resist is removed to form a trench. The method of forming the trench is similar to that described with reference to FIG. 9, but in this embodiment, the trench is formed to pass through the third semiconductor layer 130 together with the first semiconductor layer 110. In this case, the depth of the trench is preferably formed up to the upper surface of the fourth semiconductor layer 140 disposed under the third semiconductor layer 130.

The heterojunction between the third semiconductor layer 130 and the fourth semiconductor layer 140 is partially disconnected by the trenches. 2DEG does not occur in the thus disconnected part.

Then, a gate electrode material is deposited to fill the resist-removed region and the trench, and the resist is removed to form a T-type gate electrode 180. [

12, the semiconductor device 1000 '' physically eliminates the heterojunction between the third semiconductor layer 130 and the fourth semiconductor layer 140 at the time of forming the trench, A region where the 2DEG is disconnected at the bottom of the gate is generated. That is, the present semiconductor device 1000 '' may have a normally off state.

Meanwhile, the semiconductor devices of FIGS. 10 to 12 may further include a substrate (not shown) disposed under the buffer layer 101.

The substrate is selected as a material capable of growing a semiconductor material on its upper surface. Particularly, in order to grow the nitride layer, a sapphire (Al 2 O 3 ) substrate having a hexagonal crystal system such as a nitride layer, or a silicon carbide (SiC), a silicon (Si) Zinc oxide (ZnO), gallium arsenide (Ga), gallium nitride (GaN), spinel (MgAlO 4 ), or the like can be used as a substrate material.

The semiconductor device according to the above-described various embodiments uses T-type gates of nano size (for example, 10 nm or less), and is suitable for switching power devices as well as very high frequency and high output devices. It is also possible to measure the ballistic transport phenomenon due to the gate length below the mean free path of GaN.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It goes without saying that the example can be variously changed. Accordingly, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. * * * * * Recently Added Patents

110: first semiconductor layer 160: insulating layer
180: gate electrode 191: source electrode
193: drain electrode 1000: semiconductor element

Claims (11)

A method of manufacturing a semiconductor device,
Providing a first semiconductor layer;
Forming a mask layer having a predetermined width on the first semiconductor layer to dry-etch the first semiconductor layer;
Wet etching the side surface of the dry-etched first semiconductor layer so that a width of the first semiconductor layer is smaller than a width of the mask layer;
Removing the mask layer;
Forming an insulating layer having a predetermined height at a portion where the first semiconductor layer is removed by the dry etching and the wet etching;
Etching the first semiconductor layer to form a trench; And
Forming a gate electrode having a contact region wider than the width of the trench,
Wherein the wet etching comprises:
Wherein the wet etching is performed using a tetra-methyl ammonium hydroxide (TMAH) solution. The method according to claim 1,
Wherein the dry etching comprises:
The first semiconductor layer is dry-etched so that a height of the first semiconductor layer corresponding to a portion where the mask layer is not formed is lower than a height of the first semiconductor layer corresponding to a portion where the mask layer is formed Gt; 3. The method of claim 2,
And forming a source electrode and a drain electrode on the first semiconductor layer having the low height. The method according to claim 1,
The step of providing the first semiconductor layer may include:
Wherein the first semiconductor layer is formed on the second semiconductor layer. 5. The method of claim 4,
Wherein forming the trench comprises:
Wherein the trench is formed so that the second semiconductor layer having a constant height exists under the trench. 5. The method of claim 4,
Wherein the second semiconductor layer comprises:
And the third semiconductor layer is stacked on the fourth semiconductor layer. The method according to claim 6,
Wherein the third semiconductor layer is made of GaN, and the fourth semiconductor layer is made of AlGaN or AlN. The method according to claim 6,
Wherein forming the trench comprises:
And forming the trench to pass through the third semiconductor layer. A method of manufacturing a semiconductor device,
Providing a first semiconductor layer;
Forming a mask layer having a predetermined width on the first semiconductor layer to dry-etch the first semiconductor layer;
Wet etching the side surface of the dry-etched first semiconductor layer so that a width of the first semiconductor layer is smaller than a width of the mask layer;
Removing the mask layer;
Forming an insulating layer having a predetermined height at a portion where the first semiconductor layer is removed by the dry etching and the wet etching;
Etching the first semiconductor layer to form a trench; And
Forming a gate electrode having a contact region wider than the width of the trench,
Wherein forming the insulating layer comprises:
Depositing an insulating layer on the first semiconductor layer and the portion where the first semiconductor layer is removed by the dry etching and the wet etching;
Depositing a photoresist on the deposited insulating layer by a spin coating method; And
Performing a dry etch to remove the photoresist and the insulating layer deposited within a range exceeding the predetermined height. The method according to claim 1,
Wherein the first semiconductor layer comprises a first semiconductor layer,
type dopant is doped with an n-type dopant. delete
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KR20220095164A (en) * 2020-12-29 2022-07-06 경북대학교 산학협력단 Method of formation of self-aligned source/drain and ultra-short gate length with wet etching
KR102437939B1 (en) 2020-12-29 2022-08-30 경북대학교 산학협력단 Method of formation of self-aligned source/drain and ultra-short gate length with wet etching

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