JP5276849B2 - Manufacturing method of nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a nitride semiconductor device, which can suppress a current collapse, can increase a breakdown voltage, and can relax electric field concentration by forming a nitride semiconductor layer of a microcrystalline structure in a gradually inclining shape. <P>SOLUTION: A gate electrode is formed in a recessed part which is formed by obliquely inclining a sidewall formed on a highly insulating second nitride semiconductor layer with no aluminum contained therein. The recessed part whose sidewall is oblique is formed by being grown while a growth temperature of the second nitride semiconductor device is gradually lowered, and then is etched by using etchants with different etching rates depending on the growth temperatures. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method of manufacturing a nitride semiconductor device using a nitride semiconductor as an active layer, and in particular, a high electron mobility transistor (HEMT), a field effect transistor (FET), and a Schottky. The present invention relates to a method of manufacturing a nitride semiconductor device having an electrode that is in Schottky contact with a semiconductor device, such as a barrier diode.

  FIG. 5 shows a cross-sectional view of a conventional semiconductor device made of a group III-V nitride semiconductor. The semiconductor device shown in FIG. 5 has a so-called HEMT structure. On a substrate 11 made of a sapphire substrate, a buffer layer 12 made of gallium nitride (GaN), a channel layer 13 made of gallium nitride, and n-type aluminum gallium nitride. A carrier supply layer 15 made of (AlGaN) and a Schottky layer 14 made of non-doped aluminum gallium nitride are sequentially stacked. From the potential well in the vicinity of the heterojunction interface made up of the channel layer 13 and the carrier supply layer 15. A two-dimensional electron gas layer with extremely high electron mobility is formed. In the semiconductor device having such a structure, the carrier (two-dimensional electron gas) flowing between the source electrode 17a and the drain electrode 17b is controlled by controlling the voltage applied to the gate electrode 18 in Schottky contact with the Schottky layer 14. doing. Reference numeral 16 denotes a cap layer made of silicon nitride.

  The breakdown voltage of the conventional nitride semiconductor device having such a structure is greatly influenced by the Schottky characteristic formed by the contact between the gate metal and the nitride semiconductor layer. In general, Schottky characteristics of a gate metal formed on a nitride semiconductor layer, such as an aluminum gallium nitride (AlGaN) layer or a gallium nitride (GaN) layer, show a high gate leakage current, which triggers impact ionization, Reduce the breakdown voltage (drain breakdown voltage when the FET is off), which is an important parameter for nitride semiconductor devices with high output elements, to a lower level than expected, and fully exploit the high breakdown voltage characteristics of wide gap materials. There was a problem that could not. On the other hand, even in a semiconductor device in which a gate electrode is formed on a nitride semiconductor layer such as an aluminum gallium nitride (AlGaN) layer or a gallium nitride (GaN) layer, the surface trapped by electrons trapped in the surface level of the nitride semiconductor layer There is a problem that the potential fluctuates and frequency dispersion (current collapse) of the current-voltage characteristic occurs.

  On the other hand, in order to improve the breakdown voltage, it is known to use a field plate structure as shown in FIG. In the conventional field plate structure, a cap layer 16 made of silicon nitride, silicon oxide, or the like is used between the nitride semiconductor layer and the electrode portion connected to the gate electrode (for example, Patent Document 1). However, when silicon oxide is used as the cap layer, current collapse occurs, and when silicon nitride is used, there is a problem that the breakdown voltage is lower than when silicon oxide is used.

The applicant of the present application solves these problems, and on the nitride semiconductor layer having a highly insulating microcrystalline structure formed by setting the film formation temperature low for the purpose of suppressing current collapse and increasing the breakdown voltage. A nitride semiconductor device having a field plate structure has been proposed (Japanese Patent Application No. 2007-236115).
JP 2004-200248 A

  The nitride semiconductor device having a nitride semiconductor layer having a microcrystalline structure with high insulation characteristics previously proposed by the applicant of the present application reduces current collapse by controlling electrons trapped in the surface order or reducing the surface state density. Was suppressed and the high frequency characteristics were improved.

  Although higher breakdown voltage is desired, the conventional nitride semiconductor device uses a dry etching method using a chlorine-based gas when etching away a part of the nitride semiconductor layer having a microcrystalline structure. Therefore, there is a problem that the surface remains damaged and the leakage current increases.

  On the other hand, according to the wet etching method, although leakage current due to etching damage can be suppressed, in order to further increase the breakdown voltage, if the side wall of the nitride semiconductor layer having a microcrystalline structure is formed to have a gently inclined shape, etching is performed. Due to the slow rate etching of the crystal plane, it was possible to form only a nearly vertical shape.

  INDUSTRIAL APPLICABILITY The present invention can achieve current collapse suppression and high breakdown voltage, and a method for manufacturing a nitride semiconductor device that can form a nitride semiconductor layer having a microcrystalline structure in a gently slanted shape and reduce electric field concentration The purpose is to provide.

In order to achieve the above object, the invention according to claim 1 of the present application provides at least one group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and at least one of the group consisting of nitrogen, phosphorus and arsenic. In the method of manufacturing a nitride semiconductor device comprising a group III-V nitride semiconductor layer composed of a group V element containing nitrogen, a first nitride semiconductor comprising the group III-V nitride semiconductor layer on a substrate Forming a layer, and forming a second nitride semiconductor layer made of the III-V nitride semiconductor layer and not containing aluminum on the first nitride semiconductor layer, the first nitride The step of starting growth at a temperature lower than the film formation temperature of the semiconductor layer to become a microcrystalline structure, then gradually lowering the film formation temperature and growing to a temperature at which it becomes an amorphous structure ; 1st Nitro Forming a first electrode in ohmic contact with the physical semiconductor layer, and etching a part of the second nitride semiconductor layer using an etchant whose etching rate increases as the film forming temperature decreases; Forming a recess having an inclined side wall with an opening width on the surface side wide; and Schottky contact with the first nitride semiconductor layer exposed in the recess; at least the side wall on the first electrode side Forming a second electrode to be covered.

  According to a second aspect of the present invention, in the method for manufacturing a nitride semiconductor device according to the first aspect, the step of forming the second nitride semiconductor layer is based on a film formation temperature of the first nitride semiconductor layer. This is characterized in that the film is formed by maintaining the temperature at which the crystallite structure becomes low and growing, and then setting the film forming temperature at a lower temperature.

  The invention according to claim 3 of the present application is the method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein when the part of the second nitride semiconductor layer is etched to form the recess, The method includes a step of leaving the part of the second nitride semiconductor layer at the bottom of the recess and forming the gate electrode in Schottky contact with the second nitride semiconductor layer.

  According to the manufacturing method of the present invention, the structure having a highly insulating nitride semiconductor layer between the Schottky electrode and the ohmic electrode suppresses electrons trapped in the surface level between the Schottky electrode and the ohmic electrode or By reducing the surface state density, a current collapse phenomenon is suppressed, and a semiconductor device with improved high-frequency characteristics can be formed. At the same time, by adopting a structure in which the Schottky electrode covers the gently inclined side wall, the electric field concentration is alleviated, and a nitride semiconductor device having a higher breakdown voltage than the conventional structure in which the side wall portion is substantially vertical can be formed.

  In particular, the surface of the nitride semiconductor layer having high insulating properties is set to be lower at the surface, and the opening width on the surface side can be easily widened by etching using an etching solution having a different etching rate depending on the film forming temperature. An inclined side wall can be formed. Since the control of the inclined shape can be performed by controlling the film formation temperature, it is a very simple method. Further, since it is based on the wet etching method, there is an advantage that it is free of damage.

  Further, when the Schottky electrode is formed so as to be Schottky bonded through a thin nitride semiconductor layer having a microcrystalline structure, a nitride semiconductor device having a higher breakdown voltage can be formed. The thin nitride semiconductor layer having a microcrystalline structure is formed as a layer having a relatively low etching rate as compared with the upper layer portion (in other words, formed as a layer having a high growth temperature), thereby obtaining a uniform film thickness. Thus, a nitride semiconductor device with little variation in characteristics can be formed.

  Hereinafter, a method for manufacturing a nitride semiconductor device according to the present invention will be described in detail by taking as an example a method for manufacturing a HEMT that is a group III-V nitride semiconductor device.

  FIG. 1 is a sectional view of a nitride semiconductor device according to a first embodiment of the present invention, and FIG. 2 is an explanatory view of the manufacturing process. As shown in FIG. 2A, nitridation with a thickness of about 200 nm is performed on a substrate 11 made of silicon carbide (SiC) by MOCVD (metal organic chemical vapor deposition) method, MBE (electron beam epitaxial) method, or the like. A buffer layer 12 made of aluminum (AlN), a channel layer 13 made of non-doped gallium nitride (GaN) with a thickness of 2.5 μm having an energy gap smaller than that of a carrier supply layer described later, and carriers at the interface with the channel layer 13 A Schottky layer 14 made of n-type aluminum gallium nitride (AlGaN) with a thickness of 25 nm that forms a two-dimensional electron gas, and a high insulating property with a thickness of 200 nm formed at a temperature lower than the deposition temperature of the Schottky layer 14 A cap layer 19 made of non-doped gallium nitride (GaN) is laminated. The cap layer 19 has a microcrystalline structure (polycrystalline structure) by forming a film at a temperature range lower by about 500 ° C. to 600 ° C. than the film forming temperature of the Schottky layer 14 and by setting the film forming temperature lower toward the surface side. ) To form an amorphous structure, and a highly insulating semiconductor layer is formed. As an example, when the film formation temperature of the channel layer 13 and the Schottky layer 14 is 1080 ° C., it is preferable to start the growth at 500 ° C., gradually lower the growth temperature, and grow it in a temperature range up to about 425 ° C. A cap layer 19 can be formed.

The cap layer 19 thus formed has a high resistance of about 10 ¹¹ Ωcm. When the crystallinity of a GaN layer having a thickness of 1 μm grown at a deposition temperature of 500 ° C. was evaluated by X-ray diffraction, the half-value width of the rocking curve on the (004) plane was 1200 seconds. Similarly, at the growth temperature of 400 ° C., the half-value width cannot be measured. (Note that the GaN layer grown at 1080 ° C. has a single crystal structure, and its half-value width is 150 to 300 seconds.) Further, a cross-sectional TEM sample formed by changing the growth temperature was subjected to electron beam diffraction. When evaluated by the method, it has been confirmed that the polycrystalline structure changes to an amorphous structure as the temperature decreases.

  Next, as shown in FIG. 2B, the cap layer 19 in the source electrode 17a and drain electrode 17b formation regions on the Schottky layer 14 is removed by a dry etching method using chlorine gas or the like, and the Schottky layer 14 is removed. Expose. Thereafter, as shown in FIG. 2C, a source electrode 17a and a drain electrode 17b made of titanium (Ti) / aluminum (Al) are formed, and rapid heating is performed at 600 ° C. for 30 seconds to make ohmic contact with the Schottky layer 14. Form. The cap layer 19 can be left on the Schottky layer 14 as long as a low-resistance ohmic contact can be formed.

  Next, as shown in FIG. 2D, a part of the cap layer 19 in the gate electrode formation region between the source electrode 17a and the drain electrode 17b is removed in a concave shape, and the Schottky layer 14 is exposed at the bottom. Here, when forming the recess, a wet etching method using a 30 wt% gallium hydroxide solution having a liquid temperature of 90 ° C. is used. As shown in FIG. 3, this etching solution has etching characteristics with different etching rates depending on the growth temperature. When the cap layer 19 whose growth temperature is set lower as the surface side is etched using this etching solution as described above, the etching on the surface side proceeds faster, and the side walls become slanted as shown in FIG. Recesses can be formed.

  After that, as shown in FIG. 2E, a gate electrode 18 made of a nickel (Ni) / (Au) laminate or the like is formed to extend on the cap layer 19 on the recess and drain electrode 17b side. At the bottom of the recess, a Schottky contact is formed between the gate electrode 18 and the Schottky layer 14, and the gate electrode 18 extending toward the drain electrode 17b forms a field plate portion. In particular, since the gate electrode 18 is formed on the obliquely inclined side wall, the electric field concentration is reduced. Note that it is preferable not to form a gate electrode on the side wall on the source side. This is because an increase in the gate-source capacitance Cgs causes deterioration of the high frequency characteristics.

  In the present invention, since the cap layer 19 having a high insulating property is provided, the gate leakage current is reduced and collision ionization in the channel can be suppressed. Furthermore, by using a field plate structure, electric field concentration at the gate electrode end can be reduced. As a result, the off breakdown voltage was improved from the conventional 100V to 200V.

  Next, a second embodiment shown in FIG. 4 will be described. Similar to the first embodiment shown in FIG. 1, a thickness of about 200 nm is formed on a substrate 11 made of silicon carbide (SiC) by MOCVD (metal organic chemical vapor deposition) method, MBE (electron beam epitaxial) method or the like. A buffer layer 12 made of aluminum nitride (AlN), a channel layer 13 made of non-doped gallium nitride (GaN) with a thickness of 2.5 μm having an energy gap smaller than that of a carrier supply layer described later, and an interface with the channel layer 13 A Schottky layer 14 made of n-type aluminum gallium nitride (AlGaN) having a thickness of 25 nm that forms a two-dimensional electron gas serving as a carrier, and a high insulation property having a thickness of 200 nm formed at a temperature lower than the deposition temperature of the Schottky layer 14 A cap layer 19 made of non-doped gallium nitride (GaN) is laminated.The cap layer 19 has a microcrystalline structure (polycrystalline structure) by forming a film at a temperature range lower by about 500 ° C. to 600 ° C. than the film forming temperature of the Schottky layer 14 and by setting the film forming temperature lower toward the surface side. ) To form an amorphous structure, and a highly insulating semiconductor layer is formed. As an example, when the film formation temperature of the channel layer 13 and the Schottky layer 14 is 1080 ° C., the growth is started in the temperature range of 500 ° C. to 550 ° C., the thickness is grown from 20 nm to 30 nm, and the growth temperature is further lowered. If a growth is performed in a temperature range up to about 425 ° C., a suitable cap layer 19 can be formed.

  Further, according to the steps described in the first embodiment, the cap layer 19 in the source electrode 17a and drain electrode 17b formation region on the Schottky layer 14 is removed, and the Schottky layer 14 is exposed. Thereafter, a source electrode 17a and a drain electrode 17b made of titanium (Ti) / aluminum (Al) are formed on the exposed Schottky layer 14, and rapid heating is performed at 600 ° C. for 30 seconds to form ohmic contact with the Schottky layer 14. . The cap layer 19 can be left on the Schottky layer 14 as long as a low-resistance ohmic contact can be formed.

  Next, a part of the cap layer 19 in the gate electrode formation region between the source electrode 17a and the drain electrode 17b is removed in a concave shape. Here, in this example, the cap layer 19 having a microcrystalline structure is not completely removed, and the cap layer 19 having a microcrystalline structure is left about 20 nm at the bottom of the recess. As described above, when the cap layer 19 is formed, by setting the growth temperature at the initial stage of growth to a temperature range of 500 ° C. to 550 ° C., the etching rate of this portion becomes very slow, and the capability of about 20 nm is improved with good controllability. The layer can be left at the bottom of the recess. As the etching solution for forming the recess, the etching solution described in the first embodiment is used. As a result, the etching on the front surface side proceeds quickly, and a concave portion with an inclined side wall can be formed.

  Thereafter, in accordance with the steps described in the first embodiment, a gate electrode 18 made of a nickel (Ni) / (Au) laminate or the like is formed to extend on the concave portion and the cap layer 19 on the drain electrode 17b side. To do. At the bottom of the concave portion, a Schottky contact is formed between the gate electrode 18 and the Schottky layer 14 through the slightly remaining cap layer 19, and the gate electrode 18 extending to the drain electrode 17 b side has a field plate portion. Form. As described above, since the gate electrode 18 is formed on the obliquely inclined side wall, the electric field concentration is reduced. Further, since the increase in the gate-source capacitance Cgs causes deterioration of the high-frequency characteristics, it is preferable not to form a gate electrode on the source side wall.

  According to the present embodiment, since the cap layer 19 having high insulation characteristics exists at the Schottky interface, the Schottky barrier of the gate electrode 18 is high, gate leakage is reduced, and collision ionization in the channel is suppressed. Higher withstand voltage characteristics than the example can be obtained.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be modified. For example, the type of gate electrode and the type of ohmic electrode can be appropriately selected and set according to the type of nitride semiconductor layer to be used.

  Further, instead of the HEMT structure nitride semiconductor device, the nitride semiconductor layer doped with impurities is used as an active layer (channel layer), and the above Schottky layer 14 is formed on the FET structure or Schottky structure. A barrier diode structure may be used. The nitride semiconductor layer is not limited to the GaN / AlGaN system, and the second nitride semiconductor layer (corresponding to the cap layer 19 in the above embodiment) on which the gate electrode is formed is, for example, GaN, It can be composed of a layer containing BN, InN or a mixed crystal semiconductor thereof and not containing aluminum. Further, the first nitride semiconductor layer (corresponding to the Schottky layer 14 in the above embodiment) can be formed of, for example, a layer containing GaN, BN, InN, AlN, or a mixed crystal semiconductor thereof. Furthermore, a sapphire substrate may be used instead of the silicon carbide (SiC) substrate. In that case, it is preferable to use gallium nitride (GaN) as the buffer layer. A silicon (Si) substrate may be used instead of the silicon carbide (SiC) substrate.

  What is necessary is just to select suitably the composition of the etching liquid which etches a 2nd nitride semiconductor layer according to the kind of nitride semiconductor layer to be used. In general, as the growth temperature is lowered, the crystallinity is deteriorated and the surface having a high etching rate is easily exposed. As a result, when the growth temperature is lowered, the etching rate tends to increase, so that it can be appropriately selected from known etching solutions according to the type of the nitride semiconductor layer to be used.

  The shape of the recess can be controlled by the combination of the growth temperature, growth rate, and etchant of the second nitride semiconductor layer. Further, instead of the side wall being inclined, it is possible to make the opening width wide in a stepped manner. In this case, the growth temperature of the second nitride semiconductor layer is maintained at a constant temperature, and after the growth for a predetermined time, the growth temperature is lowered and the growth is repeated for a predetermined time. When the second nitride semiconductor layer grown in this way is etched using etching liquids having different etching rates depending on the growth temperature, a concave portion whose opening width expands stepwise can be formed.

  When the second nitride semiconductor layer is left in the recess, as described in the second embodiment, the first nitride semiconductor layer has been described in the first embodiment without keeping the growth temperature of the second nitride semiconductor layer constant. In this way, the growth temperature can be gradually lowered. Further, as described in the second embodiment, the second nitride semiconductor layer grown by keeping the growth temperature of the second nitride semiconductor layer constant is removed, and the first nitride exposed in the recess is removed. A configuration in which the Schottky electrode is in contact with the nitride semiconductor layer is also possible.

  Although the second nitride semiconductor layer has been described as having a microcrystalline structure, this is an aggregate of microcrystalline grains or a structure in which they are rearranged, the growth temperature, the gas composition of the atmosphere during growth, and the substrate to be grown. The size and arrangement of the crystal grains vary depending on the type of the material, and can be obtained by controlling the growth temperature within a range where desired Schottky characteristics, insulation characteristics, and the like can be obtained. When the growth temperature of the second nitride semiconductor layer is set to a temperature that is 400 degrees or more lower than the growth temperature of the first nitride semiconductor layer, it is suitable for forming a Schottky electrode.

1 is a sectional view of a nitride semiconductor device according to a first embodiment of the present invention. It is explanatory drawing of the manufacturing process of the nitride semiconductor device which is the 1st Example of this invention. It is explanatory drawing of the etching liquid used for the manufacturing process of the nitride semiconductor device which is the 1st Example of this invention. It is sectional drawing of the nitride semiconductor device which is the 2nd Example of this invention. It is sectional drawing of the semiconductor device which consists of a conventional III-V group nitride semiconductor. It is sectional drawing of the nitride semiconductor device provided with the conventional field plate structure.

Explanation of symbols

11; substrate, 12; buffer layer, 13; channel layer, 14; Schottky layer, 15; carrier supply layer, 16; cap layer made of silicon nitride, 17a; source electrode, 17b; drain electrode, 18; ; Cap layer

Claims (3)

Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a method for manufacturing a nitride semiconductor device comprising a semiconductor layer,
Forming a first nitride semiconductor layer comprising the group III-V nitride semiconductor layer on a substrate;
A second nitride semiconductor layer made of the III-V nitride semiconductor layer and not containing aluminum is formed on the first nitride semiconductor layer from the deposition temperature of the first nitride semiconductor layer. A step of starting growth at a temperature at which the crystallite structure is low, and then gradually lowering the film formation temperature to grow to a temperature at which the amorphous structure is formed;
Forming a first electrode in ohmic contact with the first nitride semiconductor layer;
A part of the second nitride semiconductor layer is etched using an etchant whose etching rate becomes faster as the film forming temperature is lower, so as to form a recess having an inclined side wall whose opening width on the surface side becomes wider. Process,
Forming a second electrode in Schottky contact with the first nitride semiconductor layer exposed in the recess and covering at least the side wall on the first electrode side. A method for manufacturing a semiconductor device.   2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the step of forming the second nitride semiconductor layer maintains a temperature at which a microcrystalline structure is formed lower than a film formation temperature of the first nitride semiconductor layer. A method of manufacturing a nitride semiconductor device, characterized by being a step of forming the film at a lower deposition temperature after the growth.   3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein when the recess is formed by etching a part of the second nitride semiconductor layer, the second nitride is formed at the bottom of the recess. A method of manufacturing a nitride semiconductor device, comprising: forming a second electrode that leaves a part of the oxide semiconductor layer and is in Schottky contact with the second nitride semiconductor layer.

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