KR101688965B1

KR101688965B1 - Manufacturing method for semiconductor device

Info

Publication number: KR101688965B1
Application number: KR1020150041418A
Authority: KR
Inventors: 이정희; 이동기; 김도균; 조영우; 손동혁
Original assignee: 경북대학교 산학협력단
Priority date: 2015-03-25
Filing date: 2015-03-25
Publication date: 2016-12-22
Also published as: KR20160114924A

Abstract

A semiconductor device manufacturing method is disclosed. The method includes the steps of: providing a first semiconductor layer on a substrate; forming a mask layer having a predetermined width on the first semiconductor layer to dry-etch the first semiconductor layer; Wet etching the side surface of the first semiconductor layer that is dry etched to have a width smaller than the width of the layer, removing the mask layer, forming an insulating layer on the portion where the first semiconductor layer is removed by dry etching and wet etching Forming a gate insulating film on the first semiconductor layer and the insulating layer, and forming a gate electrode on the gate insulating film.

Description

Technical Field [0001] The present invention relates to a method of manufacturing a semiconductor device,

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a very fine gate length capable of implementing a normally off characteristic.

BACKGROUND ART [0002] In recent years, due to rapid development of information communication technology worldwide, communication technology for high speed and large capacity signal transmission has been rapidly developed. Particularly in the wireless communication technology, demand for high-speed, high-power electronic devices has been increasing as demand for personal mobile phones, satellite communication, military radar, broadcasting communication, Therefore, a lot of research has been going on to reduce the energy loss of the power device used for the high power electronic device.

In particular, GaN-based nitride semiconductors have excellent physical properties such as high energy gap, high thermal chemical stability, and high electron saturation rate (~ 3 x 107 cm / sec), so that they can be applied not only to optical devices but also to electronic devices for high frequency and high output And has been actively studied worldwide.

Electronic devices using GaN-based nitride semiconductors have various advantages such as high breakdown field (~ 3 x 10 6 V / cm), maximum current density, stable high temperature operation and high thermal conductivity. High electron mobility transistors , HEMT), since the band-discontinuity at the bonding interface is large, a 2DEG (two-dimensional electron gas) layer is formed at the interface, and electrons at a high concentration can be induced, , It can be applied to high power devices.

Since a conventional high electron mobility transistor has a 2DEG layer at all times due to the nature of its structure, the device remains normally on when the voltage is not applied, and the voltage must always be applied to turn off the device do. Therefore, there is a problem that it is difficult to use as a switch because power consumption in a standby state is large. In addition, a high-speed device such as a high electron mobility transistor has a short gate length for a high modulation operation.

It is an object of the present invention to provide a method of manufacturing a semiconductor device having a very fine gate length capable of realizing a normally off characteristic.

According to another aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising: forming a first semiconductor layer on a substrate; forming a mask layer having a predetermined width on the first semiconductor layer; Wet etching the side surface of the dry-etched first semiconductor layer so that the width of the first semiconductor layer is smaller than the width of the mask layer; Forming a gate insulating film on the first semiconductor layer and the insulating layer, forming a gate insulating film on the first semiconductor layer and the insulating layer, And forming a gate electrode on the insulating film.

In this case, the step of providing the first semiconductor layer may include the steps of: providing a third semiconductor layer on the substrate; forming a second semiconductor layer on the third semiconductor layer; And forming the first semiconductor layer, wherein the third semiconductor layer is made of GaN, and the second semiconductor layer is made of AlGaN or AlN.

In this case, the first semiconductor layer may be composed of GaN doped with a p-type dopant.

Meanwhile, the method of manufacturing a semiconductor device according to the present embodiment may further include forming a source electrode and a drain electrode on the second semiconductor layer.

The step of forming the insulating layer may include depositing an insulating layer on a portion of the first semiconductor layer where the first semiconductor layer is removed by the dry etching and the wet etching, Depositing a photoresist in a coating manner, and performing a dry etch to remove the photoresist and planarize the deposited insulating layer.

In this case, the step of planarizing may planarize the first semiconductor layer and the insulating layer to the same height.

Meanwhile, the wet etching may be performed by wet etching using a tetra-methyl ammonium hydroxide (TMAH) solution.

FIGS. 1A to 9 are views for explaining a semiconductor device manufacturing method according to an embodiment of the present invention,
10 is a view for explaining a semiconductor device according to an embodiment of the present invention.

Various embodiments of the present invention will be described in detail with reference to the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the following embodiments can be modified into various other forms, and the technical scope of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Also, to "include" an element means that it may include other elements, rather than excluding other elements, unless specifically stated otherwise. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the technical spirit of the present invention is not limited by the relative size or spacing depicted in the accompanying drawings.

Hereinafter, a semiconductor device according to various embodiments of the present invention, and a method for manufacturing a semiconductor device, will be described. In particular, the semiconductor device of the present invention can be realized as an element using a nitride semiconductor.

The nitride semiconductor is a semiconductor belonging to the III-V group semiconductor and containing nitrogen as the V group element. Gallium nitride (GaN), aluminum nitride (AIN), and indium nitride (InN). It is a wide-gap semiconductor having a larger band gap than that of the conventional semiconductor, and the bandgap can be largely changed by changing the concentration of gallium, indium and aluminum.

The semiconductor device in this specification uses such a nitride, and can be variously implemented as a transistor, a diode, and the like. Hereinafter, for ease of explanation, it is assumed that the semiconductor device is a transistor. Transistors control the current or voltage flow in an electronic circuit to amplify or act as a switch.

The term " deposition ", "growth ", and the like used hereinafter are used to mean the formation of a semiconductor material layer, and the layer or thin film formed through various embodiments of the present invention may be formed by an organometallic vapor deposition APCVD, LPCVD, UHCVD, PVD, electron beam (MOCVD), molecular beam epitaxy (MBE), and the like. Method, a resistance heating method, or the like. When the metal organic chemical vapor deposition (MOCVD) method is used, the flow rate of the gas injected into the MOCVD reaction chamber can be determined, and the thickness of the thin film grown according to the kind of the gas, the pressure inside the reaction chamber, The surface roughness, the doped concentration of the dopant, and the like. Particularly, the higher the temperature, the better the crystallinity of the thin film can be obtained, which should be limited in consideration of the physical properties of the reaction gas and the temperature at which the reaction occurs. In particular, ALD (Atomic layer deposition) can be used for precise growth. According to the ALD method, thin film growth can be controlled on an atomic basis.

As used herein, the term "semiconductor layer" refers to a layer composed of a semiconductor material and may be replaced by another term such as an epitaxial layer, a material layer, or the like.

1A to 9 are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, a first semiconductor layer 110 is provided. The first semiconductor layer 110 may be formed on a substrate, a buffer layer, a semiconductor layer of a material different from that of the first semiconductor layer 110, or the like. 1A, the first semiconductor layer 110 is formed on the third semiconductor layer 130 on the structure in which the second semiconductor layer 120 is stacked, I will explain.

Specifically, referring to FIG. 1A, a third semiconductor layer 130 is formed on a buffer layer (or a substrate) 101.

The buffer layer 101 serves as a buffer layer for reducing crystal defects caused by the incoincidence of crystal lattice of the substrate (not shown) and the crystal lattice of the material grown thereon, and serves as a resistance layer for preventing current leakage when a high voltage is applied can do. For example, the buffer layer 101 may be formed of a layer consisting of at least one of highly resistive GaN, GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN, The layer may consist of several kinds of nucleation layers to reduce the number of nucleation layers.

Next, a third semiconductor layer 130 is formed on the buffer layer 101 as shown in FIG. 1A. The third semiconductor layer 130 may be made of GaN. For example, the third semiconductor layer 130 may be an undoped GaN layer, and in some cases, it may be a GaN layer doped with a predetermined impurity.

Next, a second semiconductor layer 120 is formed on the third semiconductor layer 130 as shown in FIG. 1A. The second semiconductor layer 120 may include a semiconductor material different from the third semiconductor layer 130. In particular, the material of the second semiconductor layer 120 may differ from the material of the third semiconductor layer 130 by at least one of a polarization property, an energy bandgap, and a lattice constant. For example, at least one of the polarization ratio and the energy band gap of the second semiconductor layer 120 may be larger than that of the third semiconductor layer 130. For example, the second semiconductor layer 120 may be an AlGaN layer or an AlN layer. The second semiconductor layer 120 may be an undoped layer, but in some cases it may be a doped layer with certain impurities.

The second semiconductor layer 120 may be formed to form a two dimensional electron gas (hereinafter, referred to as a 2DEG) on a part of the third semiconductor layer 130. The 2DEG may be formed in a region of the third semiconductor layer 130 below the heterojunction interface between the second semiconductor layer 120 and the third semiconductor layer 130. The 2DEG formed in the third semiconductor layer 130 may be used as a channel. 2DEG is 8.8 × 10 ¹² cm ^- can have an electron mobility of Figure ¹ ^- ² ^{concentration, 1700 cm 2 · V -1 ·} s of.

GaN / AlGaN or GaN / AlN heterojunction is used. However, the present invention is not limited thereto, and any combination of materials capable of forming a 2DEG layer at the heterojunction interface may fall within the scope of the present invention. It is obvious to those skilled in the art that a detailed description thereof will be omitted.

A semiconductor device manufactured according to an embodiment of the present invention may be realized by a high electron mobility transistor (HEMT) using the 2DEG as a channel.

Next, as shown in FIG. 1A, the first semiconductor layer 110 may be provided on the second semiconductor layer 120. FIG. The first semiconductor layer 110 may be a GaN or AlGaN layer doped with a p-type dopant such as Mg. The doping concentration may be 2 x 10 ¹⁹ cm ^-3 .

Next, a mask layer 140 having a predetermined width is formed on the first semiconductor layer 110 as shown in FIG. 1A. Specifically, the mask layer 140 having a predetermined pattern can be formed by using the exposure process. In this case, for example, an E-beam lithography technique can be used. Mask layer 140 is SiO _2, SiN _x (for example, Si ₃ N ₄₎ can be a dielectric or metal, Cr, Ni and the like, which cause a reaction in the etching solution used in the wet etching in a subsequent step It can be selected as a substance that does not exist.

FIG. 1B is a top view of the mask layer 140 formed on the first semiconductor layer 110. FIG. The arrangement direction of the mask layer 140 may be determined based on a flat zone or a notch of the substrate 100 on which the crystal growth of the first semiconductor layer 110 is based as shown in FIG. have. 1B, the shape of the mask layer 140 is a shape elongated in a direction perpendicular to a flat zone or a notch of the substrate 100, 1 < / RTI > The reason why the arrangement direction of the mask layer 140 is determined in this manner is that the first semiconductor layer 110 to be performed in the subsequent step is formed by using the fact that the etching rate is significantly faster than the plane in which the plane perpendicular to the flat zone is horizontal, In order to obtain a structure having a width of nano-size through wet etching.

1C shows a cross-section (A-A ') of the structure shown in FIG. 1A.

Then, the first semiconductor layer 110 under the mask layer 140 is dry-etched as shown in FIG. Dry etching can be performed with a plasma using a halogen gas such as chlorine (Cl ₂ ), bromine (Br ₂ ), or iodine (I ₂ ). For example, TCP-RIE (transformer coupled plasma reactive ion etching) equipment can be used.

When the dry etching is performed, the first semiconductor layer 110 under the mask layer 140 may have a trapezoidal shape as shown in FIG. That is, most of the side walls of the first semiconductor layer 110 are not straight as shown in FIG. 2 only by dry etching. Its slanted angle is ~ 65 °. Thus, a wet etch is further performed to further narrow the width while making the slope of the dry etched sidewalls vertical.

Specifically, wet etching can be performed using a tetra-methyl ammonium hydroxide (TMAH) solution. When the wet etching is performed, first, the side inclination of the dry-etched first semiconductor layer 110 becomes perpendicular as shown in FIG. This is because the etching rate of the upper region (the region close to the mask layer 140) is slower than the lower region of the structure.

Then, as the wet etching time elapses, the width becomes narrow as shown in Fig. The reason why it can be selectively etched only in the lateral direction is attributed to the anisotropic etch characteristic along the crystal planes of the Group III nitride semiconductor structures constituting the first semiconductor layer 110. Specifically, when wet etching is performed using a TMAH solution, the etching is performed only on the nitrogen face and not on the gallium face. The surface exposed by the dry etching in the previous step has a mostly nitrogen surface, so it can react strongly to the TMAH solution.

In addition, since the direction of the side surface of the dry-etched first semiconductor layer 110 is perpendicular to the flat zone of the substrate 100, it has a higher etch rate than the horizontal surface. Accordingly, as the wet etching proceeds, the width of the first semiconductor layer 110 becomes narrow as shown in FIG.

On the other hand, as a result of experiments with different wet etching times, it was found that the width can be effectively controlled by controlling the wet time. In the experiment, immediately after dry etching, the structure was trapezoidal in shape, with an upper width of 400 nm and a lower width of ~ 550 nm. Then, wet etching was performed for 10, 25, 35 and 40 minutes respectively with TMAH solution (concentration 5%, 80 ° C), and the width of the structure was reduced to 300, 200, 100 and 50 nm, respectively. The etch rate was measured at 8.5 to 9 nm / min. As the etch rate increased, the width decreased further and the width was reduced to less than 10 nm.

It is very difficult to precisely fabricate the width of the semiconductor layer to a nano level. However, according to the embodiment of the present invention which performs both the dry etching and the wet etching as described above, the width of the nano- Can be obtained. In addition, wet etching may also achieve additional effects such that the dry etched surface is planarized and the plasma damage induced on the dry etched surface can be removed.

As a result, the first semiconductor layer 110 having a nano-sized width smaller than that of the mask layer 140 can be obtained.

Then, the mask layer 140 is removed as shown in Fig.

Next, an insulating layer is formed at a portion where the first semiconductor layer 110 is removed by dry etching and wet etching. Specifically, the insulating layer can be formed through the following steps.

First, as shown in FIG. 6, an insulating layer 150 is deposited on a portion of the first semiconductor layer 110 where the first semiconductor layer 110 is removed by dry etching and wet etching, and on the first semiconductor layer 110. Insulation layer 150 may be configured to be selected from an insulating material such as _{SiO 2, Al 2 O 3,} Si 3 N 4, HfO 2.

Then, a photoresist 160 is deposited on the insulating layer 150 as shown in FIG. The photoresist 160 may be deposited by a spin coating method. Spin coating is a coating method based on the principle that the fluid is spread by centrifugal force as the substrate is rotated at a very high speed. Since the photoresist has a constant viscosity, it can be applied relatively thick to the protruding region and relatively thick to the non-protruding region, depending on the nature of such photoresist when applied by a spin coating method. 7, a photoresist 160 is thinly deposited on the protruded portion of the first semiconductor layer 110 having a width of nano-size, and the photoresist 160 is deposited on the other non- Is relatively thick.

Then, dry etching is performed so that the insulating layer 150 is flattened. When the photoresist 160 and the insulating layer 150 are sequentially removed by performing the dry etching using the property that the photoresist 160 is deposited with the step difference, the photoresist 160 and the photoresist 160, as shown in FIG. 8, The insulating layer 150 deposited within a range exceeding a certain height may be removed and the insulating layer 150 may be planarized. In this case, the first semiconductor layer 110 and the insulating layer 150 may be planarized to have the same height.

The first semiconductor layer 110 having a width of nano-size is formed in the insulating layer 150 by dry etching only without complicated processes, by using the property that the photoresist 160 is deposited with a step difference by spin coating, Can be disposed.

Next, as shown in FIG. 9, a gate insulating layer 170 is formed on the first semiconductor layer 110 and the insulating layer 150. The gate insulating layer 170 is formed to electrically isolate the gate electrode (not shown) and the first semiconductor layer 110 to be formed in a subsequent process. The gate insulating layer 170 may be formed of a material selected from Al ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , HfO _2, and the like.

10, a source electrode 181 and a drain electrode 183 are formed on the second semiconductor layer 120, and a gate electrode 190 is formed on the gate insulating film 170. Next, as shown in FIG.

According to one example, the source electrode 181 and the drain electrode 183 can be formed in the following manner. Specifically, a region (contact hole) for forming the source electrode 181 and the drain electrode 183 is formed. Then, except for the contact hole, a mask layer is formed over the entire device. The electrode can be deposited using a tron-beam evaporator in the mask layer and the contact hole. The electrode may be composed of an Au / Ni / Al / Ti metal layer. The electrode is then subjected to rapid thermal annealing. At this time, the heat treatment can be performed in an N ₂ atmosphere at 500 ° C (20 sec) - 800 ° C (30 sec). When the mask layer is lifted through the lift-off process, the source electrode 181 and the drain electrode 183 may be formed in the contact hole region.

Then, a gate electrode 190 is formed between the source electrode 181 and the drain electrode 183. The gate electrode 190 may be made of, for example, an Au / Ni metal layer.

According to the semiconductor device manufacturing method according to the above-described embodiments, it is possible to manufacture a semiconductor device having a gate length of nano size (for example, 10 nm or less) which is difficult to be realized by an E-beam lithography method.

Hereinafter, with reference to FIG. 11, description will be given of a semiconductor device that can be manufactured according to the above-described manufacturing method.

11 is a view showing a semiconductor device according to an embodiment of the present invention. 11, a semiconductor device 1000 includes a substrate 100, a buffer layer 101, a third semiconductor layer 130, a second semiconductor layer 120, a first semiconductor layer 110, an insulating layer 150 A source electrode 181, a drain electrode 183, and a gate electrode 190. The source electrode 181, the drain electrode 183,

The substrate 100 is selected as a material capable of growing a semiconductor material on its upper surface. Particularly, in order to grow the nitride layer, a sapphire (Al ₂ O ₃ ) substrate having a hexagonal crystal system such as a nitride layer, or a silicon carbide (SiC), a silicon (Si) Zinc oxide (ZnO), gallium arsenide (Ga), gallium nitride (GaN), spinel (MgAlO ₄ ), or the like can be used as a substrate material.

The buffer layer 101 serves as a buffer layer for reducing crystal defects caused by the inconsistency of the crystal lattice of the substrate 100 and the crystal lattice formed thereon and serves as a resistance layer for preventing current leakage when a high voltage is applied can do. For example, the buffer layer 101 may be formed of a layer consisting of at least one of highly resistive GaN, GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN, The layer may consist of several kinds of nucleation layers to reduce the number of nucleation layers. Meanwhile, the buffer layer 101 may have an arbitrary structure, and the third semiconductor layer 130 may be formed directly on the substrate 100.

The third semiconductor layer 130 is formed on the buffer layer 101 (or the substrate 100). The third semiconductor layer 130 may be an undoped GaN layer, or may be a GaN layer doped with a predetermined impurity.

The second semiconductor layer 120 is formed on the third semiconductor layer 130 and includes a semiconductor material different from the third semiconductor layer 130. In particular, the material of the second semiconductor layer 120 may differ from the material of the third semiconductor layer 1430 by at least one of a polarization property, an energy bandgap, and a lattice constant. For example, at least one of the polarization ratio and the energy band gap of the second semiconductor layer 120 may be larger than that of the third semiconductor layer 130. For example, the second semiconductor layer 120 may be an AlGaN layer or an AlN layer. The second semiconductor layer 120 may be an undoped layer, but in some cases it may be a doped layer with certain impurities.

The second semiconductor layer 120 may be formed to form a two dimensional electron gas (hereinafter, referred to as a 2DEG) on a part of the third semiconductor layer 130. The 2DEG may be formed in a region of the third semiconductor layer 130 below the heterojunction interface between the second semiconductor layer 120 and the third semiconductor layer 130. The 2DEG formed in the third semiconductor layer 130 may be used as a current path between the source electrode 181 and the drain electrode 183, that is, as a channel. 2DEG is 8.8 × 10 ¹² cm ^- can have an electron mobility of Figure ¹ ^- ² ^{concentration, 1700 cm 2 · V -1 ·} s of.

The first semiconductor layer 110 is disposed in one region on the second semiconductor layer 120. The first semiconductor layer may be a GaN or AlGaN layer doped with a p-type dopant such as Mg. The doping concentration may be 2 x 10 ¹⁹ cm ^-3 . the energy bandgap of the third semiconductor layer 130 under the first semiconductor layer 110 doped with the p-type dopant can be increased. As a result, the energy bandgap of the third semiconductor layer 130 Since the electron gas of the 2DEG can be reduced, a normally off characteristic can be realized.

The insulating layer 150 is disposed on the second semiconductor layer 120. Insulation layer 150 may be configured as, for example selected from insulation materials such as _{SiO 2, Al 2 O 3,} Si 3 N 4, HfO 2. The insulating layer 150 serves as a field plate for dispersing the field of the edge portion of the gate electrode 190 on the drain electrode 183 side. Therefore, the breakdown voltage of the semiconductor device 1000 can be increased, so that a high voltage can be applied to the semiconductor device 1000.

A gate insulating film 170 is disposed between the gate electrode 190 and the first semiconductor layer 110. The gate insulating layer 170 is formed to electrically isolate the gate electrode 190 from the first semiconductor layer 110. The gate insulating layer 170 may be formed of a material selected from Al ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , HfO _2, and the like.

The gate electrode 190 is a structure in which a voltage for controlling on / off operation of the semiconductor device 1000 can be applied. Since the first semiconductor layer 110 under the gate electrode 190 has a width of nano size, for example, 10 nm or less, that is, the gate length of the present semiconductor device 1000 may be 10 nm or less, 1000) can be applied to a high-frequency device and a high-output power device.

The source electrode 181 is a structure for electrically connecting an external element and the present semiconductor element 1000 to supply a carrier (electron or hole) to the semiconductor element 1000 and is disposed on the second semiconductor layer 120 . Or may be disposed to contact the third semiconductor layer 130 through the second semiconductor layer 120.

The drain electrode 183 may be disposed on the second semiconductor layer 120 with the gate electrode 190 therebetween and spaced apart from the source electrode 181. Or may be disposed to contact the third semiconductor layer 130 through the second semiconductor layer 120. The drain electrode 183 serves as a path through which the carrier supplied from the source electrode 181 is moved to the external device.

The source electrode 181 and the drain electrode 183 may be formed of an Au / Ni / Al / Ti metal layer for forming an ohmic contact with the first semiconductor layer 110. Here, an ohmic contact is a non-rectifying or resistive contact, in which the I-V curve follows the general Ohm's law.

Since the semiconductor device according to the embodiment can be realized by a high electron mobility transistor (HEMT) using a 2DEG as a channel, the semiconductor device can be applied as a high power device, and a semiconductor layer doped with a p- Layer 110) is disposed under the gate electrode 190, enabling the implementation of the normally off-off device characteristic. Further, since the semiconductor layer doped with the p-type dopant has a width of nano-sized (for example, 10 nm or less), it is suitable for switching power devices as well as very high-frequency and high-output devices. It is also possible to measure the ballistic transport phenomenon due to the gate length below the mean free path of GaN.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It goes without saying that the example can be variously changed. Accordingly, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. * * * * * Recently Added Patents

110: first semiconductor layer 120: second semiconductor layer
130: third semiconductor layer 150: insulating layer
170: gate insulating film 181: source electrode
183: drain electrode 190: gate electrode

Claims

A method of manufacturing a semiconductor device,
Providing a first semiconductor layer on a substrate;
Forming a mask layer having a predetermined width on the first semiconductor layer to dry-etch the first semiconductor layer;
Wet etching the side surface of the dry-etched first semiconductor layer so that a width of the first semiconductor layer is smaller than a width of the mask layer;
Removing the mask layer;
Forming an insulating layer on a portion where the first semiconductor layer is removed by the dry etching and the wet etching;
Forming a gate insulating film on the first semiconductor layer and the insulating layer; And
And forming a gate electrode on the gate insulating film,
Wherein forming the insulating layer comprises:
Depositing an insulating layer on the first semiconductor layer and the portion where the first semiconductor layer is removed by the dry etching and the wet etching;
Depositing a photoresist on the deposited insulating layer by a spin coating method; And
Performing a dry etch to remove the photoresist and planarize the deposited insulating layer.

The method according to claim 1,
The step of providing the first semiconductor layer may include:
Providing a third semiconductor layer on the substrate;
Forming a second semiconductor layer on the third semiconductor layer; And
And forming the first semiconductor layer on the second semiconductor layer,
Wherein the third semiconductor layer is made of GaN, and the second semiconductor layer is made of AlGaN or AlN.

3. The method of claim 2,
Wherein the first semiconductor layer comprises a first semiconductor layer,
and doped with p-type dopant.

3. The method of claim 2,
And forming a source electrode and a drain electrode on the second semiconductor layer.

delete

The method according to claim 1,
Wherein the planarizing step comprises:
Wherein the first semiconductor layer and the insulating layer are planarized to have the same height.

The method according to claim 1,
Wherein the wet etching comprises:
Wherein the wet etching is performed using a tetra-methyl ammonium hydroxide (TMAH) solution.