KR20220083619A - High electron mobility transistor and fabricating method thereof - Google Patents

Abstract

Disclosed are a high electron mobility transistor and a method for manufacturing the same. In the method of manufacturing a high electron mobility transistor according to an embodiment disclosed herein, a buffer layer, a first etch stop layer, a channel layer, a barrier layer, a second etch stop layer, a cap layer, a mask layer, and a patterned photoresist layer Forming a stacked structure sequentially stacked, etching areas other than the patterned photoresist layer in the stacked structure to the surface of the first etch stop layer, through a selective regrowth technique in the etched area of the stacked structure Forming a regrowth layer, and forming a source electrode and a drain electrode on an upper surface of the regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.

Description

HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATING METHOD THEREOF

An embodiment of the present invention relates to a high electron mobility transistor and a method for manufacturing the same.

High Electron Mobility Transistor (HEMT) is an electronic component that plays a key role in major national infrastructure projects such as national defense and communication fields due to excellent electron mobility characteristics and frequency characteristics. A HEMT device having high frequency performance requires optimization when forming a gate etch region, and optimization of parasitic resistance and capacitance components is essential to improve electrical and frequency characteristics.

However, in a high electron mobility transistor having a general structure, a barrier layer with a large energy bandgap exists between the doped cap layer and the channel. As a result, a resistance component is added to degrade the performance of the device. In addition, since the active region of the channel may be extended not only to the gate electrode but also to the source electrode and the drain electrode region, it is difficult to accurately control this, and it is difficult to optimize parasitic components that greatly affect the operating characteristics of the device.

Korean Patent Publication No. 10-1688965 (2016.12.22)

An object of the present invention is to provide a high-electron-mobility transistor capable of reducing overall resistance and improving performance, and a method for manufacturing the same.

On the other hand, the technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned are clearly to those of ordinary skill in the art to which the present invention belongs from the description below. can be understood

A method of manufacturing a high electron mobility transistor according to an embodiment of the present invention includes a buffer layer, a first etch stop layer, a channel layer, a barrier layer, a second etch stop layer, a cap layer, a mask layer, and a patterned photoresist layer forming the sequentially stacked multilayer structure; etching an area other than the patterned photoresist layer in the laminate structure to a surface of the first etch stop layer; forming a regrowth layer through a selective regrowth technique on the etched region of the laminate structure; and forming a source electrode and a drain electrode on an upper surface of the regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.

The patterned photoresist layer may be formed in a central portion of the stacked structure constituting the device unit of the high electron mobility transistor.

The etching to the surface of the first etch stop layer may include: performing etching to remove even the cap layer from areas other than the patterned photoresist layer; performing etching to remove the second etch stop layer in areas other than the patterned photoresist layer; and performing etching from the barrier layer to the surface of the first etch stop layer in a region other than the patterned photoresist layer.

The regrowth layer may be formed at a height of contacting a side surface of the channel layer from an upper portion of the first etch stop layer in the etched region of the stack structure and surrounding the side surface of the channel layer.

The regrowth layer may be formed on an upper portion of the first etch stop layer to have a height corresponding to that of the cap layer.

The regrowth layer may be made of the same material as the cap layer.

A method of manufacturing a high electron mobility transistor according to another embodiment of the present invention includes: forming a stacked structure including a channel layer, a barrier layer, and a cap layer on a buffer layer; forming a patterned photoresist layer in the upper center of the stacked structure, and etching areas other than the patterned photoresist layer in the stacked structure to the surface of the buffer layer; forming a regrowth layer in the etched region of the stack structure through a selective regrowth technique, wherein the regrowth layer is in contact with a side surface of the channel layer to surround the channel layer; and forming a source electrode and a drain electrode on an upper surface of the regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.

According to the disclosed embodiment, by etching a part using a patterned photoresist layer in the laminate structure and forming a regrowth layer in the etched region, the regrowth layer contacts the side surface of the channel layer to achieve low contact resistance, Since the barrier layer is removed between the source electrode and the drain electrode and the channel layer, it is possible to reduce a parasitic resistance component, thereby improving device performance.

On the other hand, the effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description. will be able

1 to 4 are views showing a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention,
5 is a scanning electron microscope photograph showing a regrowth layer (RG n+ InGaAs) and a gate electrode according to an embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. Embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited to the following embodiments. This embodiment is provided to more completely explain the present invention to those of ordinary skill in the art. Accordingly, the shapes of elements in the drawings are exaggerated to emphasize a clearer description.

The configuration of the invention for clarifying the solution to the problem to be solved by the present invention will be described in detail with reference to the accompanying drawings based on a preferred embodiment of the present invention, but the same in assigning reference numbers to the components of the drawings For the components, even if they are on different drawings, the same reference numbers are given, and it is noted in advance that the components of other drawings can be cited when necessary in the description of the drawings.

Meanwhile, directional terms such as upper side, lower side, one side, the other side, etc. are used in connection with the orientation of the disclosed drawings. Since components of embodiments of the present invention may be positioned in various orientations, the directional terminology is used for purposes of illustration and not limitation.

1 to 4 are views showing a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention.

Referring to FIG. 1 , a stacked structure 110 is formed on a substrate (not shown). The stacked structure 110 may constitute a device unit of a high electron mobility transistor. Here, the substrate (not shown) may support the stacked structure 110 . The substrate 102 may be made of a material such as silicon carbide (SiC), sapphire (Al ₂ O ₃ ), silicon (Si), or gallium nitride (GaN), but is not limited thereto. Also, the substrate (not shown) may be omitted in some cases.

The stacked structure 110 may be provided on the substrate (not shown). The stacked structure 110 includes a buffer layer 111 , a first etch stop layer 113 , a channel layer 115 , a barrier layer 117 , a second etch stop layer 119 , a cap layer 121 , and a mask layer 123 . ), and a photoresist layer 125 . However, the present invention is not limited thereto, and some layers may be omitted if necessary.

Each layer of the stacked structure 110 may be sequentially formed on an upper portion of a substrate (not shown) through deposition or growth. Terms such as "deposition" and "growth" used below are used in the same meaning as for forming a layer of a semiconductor material, and the layer or thin film formed through various embodiments of the present invention is formed by metal-organometallic vapor deposition. It can be grown in a growth chamber using organic chemical vapor deposition: MOCVD or molecular beam epitaxy (MBE), and in addition to PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method, It may be deposited and formed by various methods such as a resistance heating method.

When using the metal organometallic vapor deposition (MOCVD) method, the flow rate of the gas injected therein can be determined according to the volume of the MOCVD reaction chamber. properties such as thickness, surface roughness, and doped concentration of the dopant may vary. In particular, the higher the temperature, the better the crystallinity of the thin film can be obtained. In particular, for precise growth, an atomic layer deposition (ALD) method may be used. According to the ALD method, thin film growth can be controlled atomically.

A buffer layer 111 may be provided on a substrate (not shown). The buffer layer 111 serves as a buffer layer to reduce crystal defects caused by mismatch between the crystal lattice of the substrate (not shown) and the material grown on the substrate (not shown), and a current when a high voltage is applied. It can act as a resistive layer to prevent leakage. For example, the buffer layer 111 may be made of at least one of InAlAs, AlGaAs, GaN, InN, AlN, InGaN, AlGaN, and AlInN, but is not limited thereto, and various types of nucleation layers for reducing crystal defects in stages. may be done

A first etch stop layer 113 may be provided on the buffer layer 111 . The first etch stop layer 113 may serve to stop etching so that etching is not performed to the lower portion of the first etch stop layer 113 in an etching process to be described later. For example, the first etch stop layer 113 may be made of InP, but is not limited thereto.

A channel layer 115 may be provided on the buffer layer 111 . The channel layer 115 may be made of a material having high electron mobility. For example, the channel layer 115 may be made of a material selected from GaAs, InAs, and In _x Ga _1-x As, but is not limited thereto.

A barrier layer 117 may be provided on the buffer layer 111 to surround the channel layer 115 . For example, the barrier layer 117 may be respectively formed below and above the channel layer 115 to surround the channel layer 115 up and down to form a quantum-well structure, but is limited thereto. not. That is, the barrier layer 117 is formed on the channel layer 115 and the buffer layer 111 is formed under the channel layer 115 , so that the barrier layer 117 and the buffer layer 111 are formed on the channel layer 115 . ) to form a quantum well structure.

The barrier layer 117 has a larger energy bandgap than the channel layer 115 and may be made of a high resistivity material. For example, the barrier layer 117 may be made of InAlAs or AlGaAs, but is not limited thereto.

The second etch stop layer 119 may be provided on the barrier layer 117 . The second etch stop layer 119 may serve to stop etching so that etching is not performed to the lower portion of the second etch stop layer 119 in an etching process to be described later. For example, the second etch stop layer 119 may be made of InP or the like.

A capping layer 121 may be provided on the second etch stop layer 119 . The cap layer 121 may be made of a material doped with a high concentration to have a low sheet resistance while lowering a contact resistance with an electrode to be formed later. The cap layer 121 may be made of an n-type doped semiconductor material (eg, a material selected from GaAs, InAs, and In _x Ga _1-x As), but is not limited thereto.

A masking layer 123 may be provided on the cap layer 121 . The mask layer 123 is a hard mask and may protect a lower structure of the mask layer 123 in an etching process to be described later. For example, the mask layer 123 may be made of SiN, SiO ₂ , armorphous carbon, or the like, but is not limited thereto.

The photoresist layer 125 may be provided on the mask layer 123 . The photoresist layer 125 may be formed in a predetermined pattern on the mask layer 123 through a lithography process. The photoresist layer 125 may be patterned to be formed in the center of the device unit region of the high electron mobility transistor.

Referring to FIG. 2 , regions other than the patterned photoresist layer 125 in the stacked structure 110 may be etched. In this case, vertical etching may be performed up to the first etch stop layer 113 . That is, the etching is prevented by the first etch stop layer 113 and may be performed only up to the surface of the first etch stop layer 113 . Here, the etching may be performed by wet etching or dry etching.

Specifically, the etching may be performed in three steps. First, etching to remove even the cap layer 121 from areas other than the patterned photoresist layer 125 may be performed. Next, etching may be performed to remove the second etch stop layer 119 . Next, etching may be performed from the barrier layer 117 to the surface of the first etch stop layer 113 .

Referring to FIG. 3 , the regrowth layer 131 may be formed in the etched region of the etched stack structure 110 ′ through a selective regrowth technique. Here, the regrowth layer 131 may be grown from an upper portion of the first etch stop layer 113 to a height corresponding to the cap layer 121 . In this case, the regrowth layer 131 is provided while being in contact with the side surface of the channel layer 115 and surrounding the side surface of the channel layer 115 . At this time, the regrowth layer 131 forms an electrical contact with the side surface of the channel layer 115 .

The regrowth layer 131 may be made of a semiconductor material doped with a high concentration to have a low sheet resistance while lowering a contact resistance with an electrode. For example, the regrowth layer 131 may be formed of a semiconductor material doped with n-type (eg, a material selected from GaAs, InAs, In _x Ga _1-x As, etc.), but is not limited thereto. That is, the regrowth layer 131 may be made of the same material as the cap layer 121 . In this case, it is possible to secure a low contact resistance between the regrowth layer 131 and the channel layer 115 .

In an exemplary embodiment, the regrowth layer 131 may be grown through a metal-organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method.

Referring to FIG. 4 , each electrode of the high electron mobility transistor 100 may be formed. That is, the source electrode 133 and the drain electrode 135 may be respectively formed on the regrowth layer 131 , and the gate electrode 137 may be formed on the barrier layer 117 . 5 is a scanning electron microscope photograph showing the regrowth layer 131 (RG n+ InGaAs) and the gate electrode 137 according to an embodiment of the present invention.

Meanwhile, each electrode of the high electron mobility transistor 100 may be formed by a known method. For example, the source electrode 133 and the drain electrode 135 may be respectively formed by removing the mask layer 123 and depositing a conductive material on the regrowth layer 131 . Next, an insulating layer 139 may be formed on the cap layer 121 between the source electrode 133 and the drain electrode 135 .

Next, after etching the insulating layer 139 and the cap layer 121 to secure a space for forming the gate electrode 137 , the gate electrode 137 may be formed. In the etching process, the barrier layer 117 may be protected by the second etch stop layer 119 . In an exemplary embodiment, the gate electrode 137 may be formed in a T shape. In this case, the side surface of the cap layer 121 may be spaced apart from the gate electrode 137 .

In the disclosed embodiment, the regrowth layer 131 is formed as a channel layer ( 115) to achieve a low contact resistance, and since the barrier layer 117 is removed between the source electrode 133 and the drain electrode 135 and the channel layer 115, the parasitic resistance component can be reduced. It is possible to improve the performance of the device.

The above detailed description is illustrative of the present invention. In addition, the above description shows and describes preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, changes or modifications are possible within the scope of the concept of the invention disclosed herein, the scope equivalent to the written disclosure, and/or within the scope of skill or knowledge in the art. The written embodiment describes the best state for implementing the technical idea of the present invention, and various changes required in specific application fields and uses of the present invention are possible. Accordingly, the detailed description of the present invention is not intended to limit the present invention to the disclosed embodiments. Also, the appended claims should be construed to include other embodiments.

100: high electron mobility transistor
110: laminated structure
111: buffer layer
113: first etch stop layer
115: channel layer
117: barrier layer
119: second etch stop layer
121: cap layer
123: mask layer
125: photoresist layer
131: regrowth layer
133: source electrode
135: drain electrode
137: gate electrode
139: insulating layer

Claims (8)

forming a stacked structure in which a buffer layer, a first etch stop layer, a channel layer, a barrier layer, a second etch stop layer, a cap layer, a mask layer, and a patterned photoresist layer are sequentially stacked;
etching an area other than the patterned photoresist layer in the laminate structure to a surface of the first etch stop layer;
forming a regrowth layer through a selective regrowth technique on the etched region of the laminate structure; and
Forming a source electrode and a drain electrode on an upper surface of the regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.
The method according to claim 1,
The patterned photoresist layer,
A method of manufacturing a high electron mobility transistor, which is formed in the center of the stacked structure constituting the element unit of the high electron mobility transistor.
3. The method according to claim 2,
The step of etching to the surface of the first etch stop layer,
performing etching to remove even the cap layer from areas other than the patterned photoresist layer;
performing etching to remove the second etch stop layer in areas other than the patterned photoresist layer; and
and performing etching from the barrier layer to the surface of the first etch stop layer in a region other than the patterned photoresist layer.
3. The method according to claim 2,
The regrowth layer is
A method of manufacturing a high electron mobility transistor, which is formed in contact with a side surface of the channel layer on top of the first etch stop layer in the etched region of the stack structure and at a height surrounding the side surface of the channel layer.
5. The method according to claim 4,
The regrowth layer is
A method of manufacturing a high electron mobility transistor, which is formed on an upper portion of the first etch stop layer to have a height corresponding to that of the cap layer.
5. The method according to claim 4,
The regrowth layer is
A method of manufacturing a high electron mobility transistor, which is made of the same material as the cap layer.
forming a stacked structure including a channel layer, a barrier layer, and a cap layer on the buffer layer;
forming a patterned photoresist layer in the upper center of the stacked structure, and etching areas other than the patterned photoresist layer in the stacked structure to the surface of the buffer layer;
forming a regrowth layer through a selective regrowth technique on the etched region of the stack structure, the regrowth layer being in contact with a side surface of the channel layer to surround the channel layer; and
Forming a source electrode and a drain electrode on an upper surface of the regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.
A high electron mobility transistor manufactured by the method for manufacturing the high electron mobility transistor according to any one of claims 1 to 7.

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