WO2022124868A1

WO2022124868A1 - High electron mobility transistor and method for manufacturing same

Info

Publication number: WO2022124868A1
Application number: PCT/KR2021/018823
Authority: WO
Inventors: 김대현; 조현빈; 윤승원; 이인근
Original assignee: 경북대학교 산학협력단
Priority date: 2020-12-11
Filing date: 2021-12-13
Publication date: 2022-06-16

Abstract

Disclosed are a high electron mobility transistor and a method for manufacturing same. A method for manufacturing a high electron mobility transistor according to one embodiment disclosed herein comprises the steps of: forming a stacked structure in which a buffer layer, a channel layer, a barrier layer, an etch stop layer, a capping layer, a mask layer, and a patterned photoresist layer are sequentially stacked; etching regions other than the patterned photoresist layer in the stacked structure; forming each of a first regrowth layer and a second regrowth layer in the etched regions of the stacked structure through a selective regrowth technique; and forming each of a source electrode and a drain electrode on the upper surface of the second regrowth layer, and forming a gate electrode spaced apart from both the source electrode and the drain electrode.

Description

High electron mobility transistor and its manufacturing method

An embodiment of the present invention relates to a high electron mobility transistor and a method for manufacturing the same.

The present invention relates to the Civil-Military Technical Cooperation (R&D) (Ministry of Industry) of the Ministry of Trade, Industry and Energy (Project No.: 1415170814, Project No.: 19-CM-BD-05-MKE, Project Name: 3D TIV integration process for ultra-high frequency band and stacked InP/ GaN device technology development, task management institution: Defense Science Research Institute, research period: 2019.06.28. ~ 2022.06.27.)

On the other hand, in all aspects of the present invention, there is no property interest of the Korean government, which is the subject of providing the task.

High Electron Mobility Transistor (HEMT) is an electronic component that plays a key role in major national infrastructure projects such as national defense and communication fields due to excellent electron mobility characteristics and frequency characteristics. A HEMT device having high frequency performance requires optimization when forming a gate etch region, and optimization of parasitic resistance and capacitance components is essential to improve electrical and frequency characteristics.

However, in the conventional gate region etching method, it is difficult to selectively etch the capping layer, and it is difficult to accurately control the etch rate, so it is difficult to optimize parasitic components that greatly affect the operating characteristics of the device. have.

An object of the present invention is to provide a high electron mobility transistor capable of accurately controlling the size of a gate recess region and a method for manufacturing the same.

On the other hand, the technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned are clearly to those of ordinary skill in the art to which the present invention belongs from the description below. can be understood

The method of manufacturing a high electron mobility transistor according to an embodiment of the present invention comprises a stacked structure in which a buffer layer, a channel layer, a barrier layer, an etch stop layer, a cap layer, a mask layer, and a patterned photoresist layer are sequentially stacked. forming; etching a region other than the patterned photoresist layer in the laminate structure; forming a first regrowth layer and a second regrowth layer, respectively, on the etched region of the stack structure through a selective regrowth technique; and forming a source electrode and a drain electrode on an upper surface of the second regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.

The laminate structure may include a horizontal surface and a vertical surface exposed by the etching, and the first regrowth layer may be formed along the horizontal surface and the vertical surface of the laminate structure, respectively.

The etching may include etching from the mask layer to a portion of the channel layer or from the mask layer until the surface of the buffer layer is exposed.

The first regrowth layer may be formed to a height corresponding to the cap layer when formed along the vertical surface.

The forming of the gate electrode may include a gate recess process, and the first regrowth layer may be made of a material having a higher etch selectivity than the cap layer etched in the gate recess process.

In the gate recess process, etching is stopped by the first regrowth layer and the etch stop layer, so that the size of the gate recess region may be limited.

The second regrowth layer may be formed in a region defined by the first regrowth layer on the first regrowth layer.

The second regrowth layer may be formed to a height corresponding to the cap layer.

A method of manufacturing a high electron mobility transistor according to another embodiment of the present invention includes: forming a stacked structure including a channel layer, a barrier layer, and a cap layer on a buffer layer; forming a patterned photoresist layer in the upper center of the stacked structure; etching regions other than the patterned photoresist layer in the laminate structure such that the laminate structure includes a horizontal surface and a vertical surface exposed by the etching; forming a first regrowth layer along the horizontal surface and the vertical surface through a selective regrowth technique in the etched region of the laminate structure; forming a second regrowth layer on the first regrowth layer through a selective regrowth technique; and forming a source electrode and a drain electrode on an upper surface of the second regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.

According to the disclosed embodiment, a portion of the patterned photoresist layer is etched in the stacked structure and the first regrowth layer and the second regrowth layer are formed in the etched region, thereby forming the gate recess region during the gate recess process. Accuracy and stability of size can be ensured.

In addition, since the first regrowth layer is in contact with the side surface of the channel layer to achieve low contact resistance, and the barrier layer is removed between the source electrode and the drain electrode and the channel layer, the parasitic resistance component caused by the barrier layer can be reduced. can improve the performance of

On the other hand, the effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description. will be able

1 to 6 are views showing a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention,

7 is a scanning electron microscope photograph showing a state in which the first regrowth layer acts as an etch stop layer in a gate recess process according to an embodiment of the present invention.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.

In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

Examples of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art, and the following examples may be modified in various other forms, and the scope of the present invention is as follows It is not limited to an Example.

Rather, these examples are provided so that this disclosure will be more thorough and complete, and will fully convey the spirit of the invention to those skilled in the art.

In addition, in the following drawings, each configuration is exaggerated for convenience and clarity of description, and the same reference numerals refer to the same elements in the drawings. As used herein, the term “and/or” includes any one and all combinations of one or more of those listed items.

The terminology used herein is used to describe specific embodiments, not to limit the present invention.

As used herein, the singular form may include the plural form unless the context clearly dictates otherwise. Also, as used herein, “comprise” and/or “comprising” refers to specifying the presence of the recited shapes, numbers, steps, actions, members, elements, and/or groups thereof. will,

It does not exclude the presence or addition of one or more other shapes, numbers, movements, members, elements and/or groups.

1 to 6 are views showing a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention.

Referring to FIG. 1 , a stacked structure 110 is formed on a substrate (not shown). The stacked structure 110 may constitute a device unit of a high electron mobility transistor. Here, the substrate (not shown) may support the stacked structure 110 . The substrate (not shown) may be made of a material such as silicon carbide (SiC), sapphire (Al2O3), silicon (Si), or gallium nitride (GaN), but is not limited thereto. Also, the substrate (not shown) may be omitted in some cases.

The stacked structure 110 may be provided on the substrate (not shown). The stacked structure 110 includes a buffer layer 111 , a channel layer 113 , a barrier layer 115 , an etch stop layer 117 , a cap layer 119 , a mask layer 121 , and a photoresist layer 123 . can do.

Each layer of the stacked structure 110 may be sequentially formed on an upper portion of a substrate (not shown) through deposition or growth. Terms such as "deposition" and "growth" used below are used in the same meaning as for forming a layer of a semiconductor material, and the layer or thin film formed through various embodiments of the present invention is formed by metal-organometallic vapor deposition. It can be grown in a growth chamber using organic chemical vapor deposition: MOCVD or molecular beam epitaxy (MBE), and in addition to PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method, It may be deposited and formed by various methods such as a resistance heating method.

When using the metal organometallic vapor deposition (MOCVD) method, the flow rate of the gas injected therein can be determined according to the volume of the MOCVD reaction chamber. properties such as thickness, surface roughness, and doped concentration of the dopant may vary. In particular, the higher the temperature, the better the crystallinity of the thin film can be obtained. In particular, for precise growth, an atomic layer deposition (ALD) method may be used. According to the ALD method, thin film growth can be controlled atomically.

A buffer layer 111 may be provided on a substrate (not shown). The buffer layer 111 serves as a buffer layer to reduce crystal defects caused by mismatch between the crystal lattice of the substrate (not shown) and the material grown on the substrate (not shown), and a current when a high voltage is applied. It can act as a resistive layer to prevent leakage. For example, the buffer layer 111 may be made of at least one of InAlAs, AlGaAs, GaN, InN, AlN, InGaN, AlGaN, and AlInN, but is not limited thereto, and various types of nucleation layers for reducing crystal defects in stages. may be done

A channel layer 113 may be provided on the buffer layer 111 . The channel layer 113 may be made of a material having high electron mobility. For example, the channel layer 115 may be made of a material selected from GaAs, InAs, and InxGa1-xAs, but is not limited thereto.

A barrier layer 115 may be formed on the channel layer 113 . Here, the barrier layer 115 is formed on the channel layer 113 and the buffer layer 111 is formed under the channel layer 113 , so that the barrier layer 115 and the buffer layer 111 are formed on the channel layer 113 . ) to create a quantum well structure.

The barrier layer 115 may have a larger energy bandgap than the channel layer 113 and may be made of a high resistivity material. For example, the barrier layer 115 may be made of InAlAs or AlGaAs, but is not limited thereto.

An etch stop layer 117 may be provided on the barrier layer 115 . The etch stop layer 117 may serve to stop etching so that etching is not performed to the lower portion of the etch stop layer 117 in an etching process (eg, an etching process for a gate recess) to be described later. For example, the etch stop layer 117 may be made of InP or the like.

A capping layer 119 may be provided on the etch stop layer 117 . The cap layer 119 may be made of a material doped with a high concentration to have a low sheet resistance while lowering a contact resistance with an electrode to be formed later. The cap layer 119 may be made of an n-type doped semiconductor material (eg, a material selected from GaAs, InAs, and InxGa1-xAs), but is not limited thereto.

A masking layer 121 may be provided on the cap layer 119 . The mask layer 121 as a hard mask may protect the lower structure of the mask layer 121 in an etching process to be described later. For example, the mask layer 121 may be made of SiN, SiO2, amorphous carbon, or the like, but is not limited thereto.

The photoresist layer 123 may be provided on the mask layer 121 . The photoresist layer 123 may be formed in a predetermined pattern on the mask layer 121 through a lithography process. The photoresist layer 123 may be patterned to be formed in the center of the device unit region of the high electron mobility transistor.

Referring to FIG. 2 , regions other than the patterned photoresist layer 123 in the stacked structure 110 may be etched. In this case, vertical etching may be performed up to a portion of the channel layer 113 . That is, in areas other than the patterned photoresist layer 123 , the mask layer 121 , the cap layer 119 , the etch stop layer 117 , and the barrier layer 115 are etched, and up to a portion of the channel layer 113 . can be etched. Here, the etching may be performed by wet etching or dry etching.

Specifically, the etching may be performed in three steps. First, etching may be performed to remove even the cap layer 119 from areas other than the patterned photoresist layer 125 . Next, etching may be performed to remove the etch stop layer 117 . Next, etching may be performed from the barrier layer 115 to a portion of the channel layer 113 .

In this case, the etched stacked structure 110 ′ has a horizontal surface (a surface etched to a partial depth of the channel layer 113 in FIG. 2 ) S1 exposed by etching and a vertical surface (the mask layer 121 in FIG. 2 ). ) of the lower channel layer 113 , the barrier layer 115 , the etch stop layer 117 , and the cap layer 119 ) ( S2 ).

Meanwhile, as shown in FIG. 3 , when etching a region other than the patterned photoresist layer 123 , the mask layer 121 , the cap layer 119 , the etch stop layer 117 , and the barrier layer 115 . , and even the channel layer 113 may be etched. That is, etching may be performed until the surface of the buffer layer 111 is exposed.

Referring to FIG. 4 , the first regrowth layer 131 may be formed in the etched region of the etched stack structure 110 ′ through a selective regrowth technique. The first regrowth layer 131 may be grown along the surface of the etched stack structure 110 ′. That is, the first regrowth layer 131 may be respectively formed along the horizontal surface S1 and the vertical surface S2 in the etched stack structure 110 ′. When the first regrowth layer 131 is formed along the horizontal surface S1 , it is in electrical contact with the channel layer 113 on the upper surface of the channel layer 113 . In addition, when the first regrowth layer 131 is formed along the vertical surface S2 , it surrounds the side surfaces of the channel layer 113 , the barrier layer 115 , the etch stop layer 117 , and the cap layer 119 . will become

Here, when the first regrowth layer 131 is formed along the vertical surface S2 , it may grow to a height corresponding to the cap layer 119 . The first regrowth layer 131 may be formed of a material having high etch selectivity during a gate recess process, which will be described later. That is, the first regrowth layer 131 may be formed of a material having a higher etch selectivity than the cap layer 119 etched in a gate recess process. In this case, the first regrowth layer 131 is used as an etch stop layer in the etching process for the gate recess. For example, the first regrowth layer 131 may be made of n-type doped InP, but is not limited thereto.

Referring to FIG. 5 , a second regrowth layer 133 may be formed on the first regrowth layer 131 through a selective regrowth technique. That is, the second regrowth layer 133 may be formed through selective regrowth in a region defined by the first regrowth layer 131 . The second regrowth layer 133 may grow to a height of the first regrowth layer 131 (ie, a height corresponding to the cap layer 119 ).

The second regrowth layer 133 may be formed of a semiconductor material doped with a high concentration to have a low sheet resistance while lowering a contact resistance with an electrode. For example, the second regrowth layer 133 may be formed of a semiconductor material doped with n-type (eg, a material selected from GaAs, InAs, and InxGa1-xAs), but is not limited thereto.

In an exemplary embodiment, the first regrowth layer 131 and the second regrowth layer 133 are formed by a metal-organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. can be grown through In this way, the first regrowth layer 131 and the second regrowth layer 133 may be formed in the etched region of the stack structure 110 ′ through a multilayer selective regrowth technique.

Referring to FIG. 6 , each electrode of the high electron mobility transistor 100 may be formed. That is, the source electrode 135 and the drain electrode 137 may be respectively formed on the second regrowth layer 133 , and the gate electrode 139 may be formed on the barrier layer 115 .

Meanwhile, each electrode of the high electron mobility transistor 100 may be formed by a known method. For example, the source electrode 135 and the drain electrode 137 may be respectively formed by removing the mask layer 121 and depositing a conductive material on the second regrowth layer 133 . Next, an insulating layer 141 may be formed on the cap layer 121 between the source electrode 135 and the drain electrode 137 .

Next, the gate electrode 139 may be formed after performing a gate recess process for etching the insulating layer 141 and the cap layer 119 in order to secure a space for forming the gate electrode 139 . have. In an exemplary embodiment, the gate electrode 139 may be formed in a T shape.

Here, since the first regrowth layer 131 is made of a material having a higher etch selectivity than the cap layer 119 , it functions as an etch stop layer during a gate recess process. That is, since the first regrowth layer 131 acts as an etch stop layer on the side surface of the cap layer 119 and the etch stop layer 117 exists under the cap layer 119 , only the cap layer 119 portion is etched. and thus, accuracy and stability with respect to the size of the gate recess (GR) region can be secured, and a device with high reliability and reproducibility can be manufactured. That is, since the size of the gate recess region is limited by the first regrowth layer 131 and the etch stop layer 117 during the gate recess process, accuracy and stability with respect to the size of the gate recess GR region can be secured. be able to do

In the disclosed embodiment, a portion is etched using the patterned photoresist layer 123 in the stacked structure 110 , and the first regrowth layer 131 and the second regrowth layer 133 are formed in the etched region. , it is possible to secure the accuracy and stability of the size of the gate recess region.

In addition, the first regrowth layer 131 contacts the side surface of the channel layer 113 to form a low contact resistance, and the barrier layer 115 is disposed between the source electrode 135 and the drain electrode 137 and the channel layer 113 . ) is removed, it is possible to reduce the parasitic resistance component caused by the barrier layer 115, thereby improving the device performance.

7 is a scanning electron microscope photograph showing a state in which the first regrowth layer 131 acts as an etch stop layer in a gate recess process according to an embodiment of the present invention. Here, InP was used as the first regrowth layer 131 . Referring to FIG. 7 , it can be seen that only the cap layer is removed by etching and the etching is inhibited by the first regrowth layer 131 on the side surface.

The above detailed description is illustrative of the present invention. In addition, the above description shows and describes preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, changes or modifications are possible within the scope of the concept of the invention disclosed herein, the scope equivalent to the written disclosure, and/or within the scope of skill or knowledge in the art. The written embodiment describes the best state for implementing the technical idea of the present invention, and various changes required in specific application fields and uses of the present invention are possible. Accordingly, the detailed description of the present invention is not intended to limit the present invention to the disclosed embodiments. Also, the appended claims should be construed to include other embodiments.

Claims

forming a stacked structure in which a buffer layer, a channel layer, a barrier layer, an etch stop layer, a cap layer, a mask layer, and a patterned photoresist layer are sequentially stacked;

etching a region other than the patterned photoresist layer in the laminate structure;

forming a first regrowth layer and a second regrowth layer, respectively, on the etched region of the stack structure through a selective regrowth technique; and

Forming a source electrode and a drain electrode on an upper surface of the second regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.
The method according to claim 1,

The laminate structure has a horizontal surface and a vertical surface exposed by the etching,

The first regrowth layer,

A method of manufacturing a high-electron mobility transistor, each of which is formed along a horizontal surface and a vertical surface of the laminate structure.
3. The method according to claim 2,

The etching step is

A method of manufacturing a high electron mobility transistor, in which etching is performed from the mask layer to a portion of the channel layer or from the mask layer until a surface of the buffer layer is exposed.
3. The method according to claim 2,

The first regrowth layer,

When formed along the vertical surface, it is formed to a height corresponding to the cap layer, a method of manufacturing a high electron mobility transistor.
5. The method of claim 4,

The forming of the gate electrode includes a gate recess process,

The first regrowth layer,

A method of manufacturing a high electron mobility transistor comprising a material having an etch selectivity higher than that of the cap layer etched in the gate recess process.
6. The method of claim 5,

In the gate recess process, etching is inhibited by the first regrowth layer and the etch stop layer, so that the size of the gate recess region is limited.
3. The method according to claim 2,

The second regrowth layer,

A method of manufacturing a high electron mobility transistor, which is formed in a region defined by the first regrowth layer on the first regrowth layer.
8. The method of claim 7,

The second regrowth layer,

A method of manufacturing a high electron mobility transistor, which is formed up to a height corresponding to the cap layer.
forming a stacked structure including a channel layer, a barrier layer, and a cap layer on the buffer layer;

forming a patterned photoresist layer in the upper center of the stacked structure;

etching regions other than the patterned photoresist layer in the laminate structure such that the laminate structure includes a horizontal surface and a vertical surface exposed by the etching;

forming a first regrowth layer along the horizontal surface and the vertical surface through a selective regrowth technique in the etched region of the laminate structure;

forming a second regrowth layer on the first regrowth layer through a selective regrowth technique; and

Forming a source electrode and a drain electrode on an upper surface of the second regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.
A high electron mobility transistor manufactured by the method for manufacturing a high electron mobility transistor according to any one of claims 1 to 9.