WO2022124868A1 - Transistor à haute mobilité d'électrons et son procédé de fabrication - Google Patents

Transistor à haute mobilité d'électrons et son procédé de fabrication Download PDF

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Publication number
WO2022124868A1
WO2022124868A1 PCT/KR2021/018823 KR2021018823W WO2022124868A1 WO 2022124868 A1 WO2022124868 A1 WO 2022124868A1 KR 2021018823 W KR2021018823 W KR 2021018823W WO 2022124868 A1 WO2022124868 A1 WO 2022124868A1
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WO
WIPO (PCT)
Prior art keywords
layer
regrowth
forming
electron mobility
mobility transistor
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PCT/KR2021/018823
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English (en)
Korean (ko)
Inventor
김대현
조현빈
윤승원
이인근
Original Assignee
경북대학교 산학협력단
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Priority claimed from KR1020210175998A external-priority patent/KR102628555B1/ko
Application filed by 경북대학교 산학협력단 filed Critical 경북대학교 산학협력단
Publication of WO2022124868A1 publication Critical patent/WO2022124868A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

Definitions

  • An embodiment of the present invention relates to a high electron mobility transistor and a method for manufacturing the same.
  • the present invention relates to the Civil-Military Technical Cooperation (R&D) (Ministry of Industry) of the Ministry of Trade, Industry and Energy (Project No.: 1415170814, Project No.: 19-CM-BD-05-MKE, Project Name: 3D TIV integration process for ultra-high frequency band and stacked InP/ GaN device technology development, task management institution: Defense Science Research Institute, research period: 2019.06.28. ⁇ 2022.06.27.)
  • R&D Civil-Military Technical Cooperation
  • High Electron Mobility Transistor is an electronic component that plays a key role in major national infrastructure projects such as national defense and communication fields due to excellent electron mobility characteristics and frequency characteristics.
  • a HEMT device having high frequency performance requires optimization when forming a gate etch region, and optimization of parasitic resistance and capacitance components is essential to improve electrical and frequency characteristics.
  • An object of the present invention is to provide a high electron mobility transistor capable of accurately controlling the size of a gate recess region and a method for manufacturing the same.
  • the method of manufacturing a high electron mobility transistor comprises a stacked structure in which a buffer layer, a channel layer, a barrier layer, an etch stop layer, a cap layer, a mask layer, and a patterned photoresist layer are sequentially stacked. forming; etching a region other than the patterned photoresist layer in the laminate structure; forming a first regrowth layer and a second regrowth layer, respectively, on the etched region of the stack structure through a selective regrowth technique; and forming a source electrode and a drain electrode on an upper surface of the second regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.
  • the laminate structure may include a horizontal surface and a vertical surface exposed by the etching, and the first regrowth layer may be formed along the horizontal surface and the vertical surface of the laminate structure, respectively.
  • the etching may include etching from the mask layer to a portion of the channel layer or from the mask layer until the surface of the buffer layer is exposed.
  • the first regrowth layer may be formed to a height corresponding to the cap layer when formed along the vertical surface.
  • the forming of the gate electrode may include a gate recess process, and the first regrowth layer may be made of a material having a higher etch selectivity than the cap layer etched in the gate recess process.
  • etching is stopped by the first regrowth layer and the etch stop layer, so that the size of the gate recess region may be limited.
  • the second regrowth layer may be formed in a region defined by the first regrowth layer on the first regrowth layer.
  • the second regrowth layer may be formed to a height corresponding to the cap layer.
  • a method of manufacturing a high electron mobility transistor includes: forming a stacked structure including a channel layer, a barrier layer, and a cap layer on a buffer layer; forming a patterned photoresist layer in the upper center of the stacked structure; etching regions other than the patterned photoresist layer in the laminate structure such that the laminate structure includes a horizontal surface and a vertical surface exposed by the etching; forming a first regrowth layer along the horizontal surface and the vertical surface through a selective regrowth technique in the etched region of the laminate structure; forming a second regrowth layer on the first regrowth layer through a selective regrowth technique; and forming a source electrode and a drain electrode on an upper surface of the second regrowth layer, respectively, and forming a gate electrode spaced apart from the source electrode and the drain electrode, respectively.
  • a portion of the patterned photoresist layer is etched in the stacked structure and the first regrowth layer and the second regrowth layer are formed in the etched region, thereby forming the gate recess region during the gate recess process. Accuracy and stability of size can be ensured.
  • the parasitic resistance component caused by the barrier layer can be reduced. can improve the performance of
  • FIG. 1 to 6 are views showing a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention
  • FIG. 7 is a scanning electron microscope photograph showing a state in which the first regrowth layer acts as an etch stop layer in a gate recess process according to an embodiment of the present invention.
  • FIG. 1 to 6 are views showing a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention.
  • a stacked structure 110 is formed on a substrate (not shown).
  • the stacked structure 110 may constitute a device unit of a high electron mobility transistor.
  • the substrate (not shown) may support the stacked structure 110 .
  • the substrate (not shown) may be made of a material such as silicon carbide (SiC), sapphire (Al2O3), silicon (Si), or gallium nitride (GaN), but is not limited thereto. Also, the substrate (not shown) may be omitted in some cases.
  • the stacked structure 110 may be provided on the substrate (not shown).
  • the stacked structure 110 includes a buffer layer 111 , a channel layer 113 , a barrier layer 115 , an etch stop layer 117 , a cap layer 119 , a mask layer 121 , and a photoresist layer 123 . can do.
  • Each layer of the stacked structure 110 may be sequentially formed on an upper portion of a substrate (not shown) through deposition or growth.
  • Terms such as “deposition” and “growth” used below are used in the same meaning as for forming a layer of a semiconductor material, and the layer or thin film formed through various embodiments of the present invention is formed by metal-organometallic vapor deposition. It can be grown in a growth chamber using organic chemical vapor deposition: MOCVD or molecular beam epitaxy (MBE), and in addition to PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method, It may be deposited and formed by various methods such as a resistance heating method.
  • MOCVD organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the flow rate of the gas injected therein can be determined according to the volume of the MOCVD reaction chamber. properties such as thickness, surface roughness, and doped concentration of the dopant may vary. In particular, the higher the temperature, the better the crystallinity of the thin film can be obtained.
  • an atomic layer deposition (ALD) method may be used. According to the ALD method, thin film growth can be controlled atomically.
  • a buffer layer 111 may be provided on a substrate (not shown).
  • the buffer layer 111 serves as a buffer layer to reduce crystal defects caused by mismatch between the crystal lattice of the substrate (not shown) and the material grown on the substrate (not shown), and a current when a high voltage is applied. It can act as a resistive layer to prevent leakage.
  • the buffer layer 111 may be made of at least one of InAlAs, AlGaAs, GaN, InN, AlN, InGaN, AlGaN, and AlInN, but is not limited thereto, and various types of nucleation layers for reducing crystal defects in stages. may be done
  • a channel layer 113 may be provided on the buffer layer 111 .
  • the channel layer 113 may be made of a material having high electron mobility.
  • the channel layer 115 may be made of a material selected from GaAs, InAs, and InxGa1-xAs, but is not limited thereto.
  • a barrier layer 115 may be formed on the channel layer 113 .
  • the barrier layer 115 is formed on the channel layer 113 and the buffer layer 111 is formed under the channel layer 113 , so that the barrier layer 115 and the buffer layer 111 are formed on the channel layer 113 . ) to create a quantum well structure.
  • the barrier layer 115 may have a larger energy bandgap than the channel layer 113 and may be made of a high resistivity material.
  • the barrier layer 115 may be made of InAlAs or AlGaAs, but is not limited thereto.
  • An etch stop layer 117 may be provided on the barrier layer 115 .
  • the etch stop layer 117 may serve to stop etching so that etching is not performed to the lower portion of the etch stop layer 117 in an etching process (eg, an etching process for a gate recess) to be described later.
  • the etch stop layer 117 may be made of InP or the like.
  • a capping layer 119 may be provided on the etch stop layer 117 .
  • the cap layer 119 may be made of a material doped with a high concentration to have a low sheet resistance while lowering a contact resistance with an electrode to be formed later.
  • the cap layer 119 may be made of an n-type doped semiconductor material (eg, a material selected from GaAs, InAs, and InxGa1-xAs), but is not limited thereto.
  • a masking layer 121 may be provided on the cap layer 119 .
  • the mask layer 121 as a hard mask may protect the lower structure of the mask layer 121 in an etching process to be described later.
  • the mask layer 121 may be made of SiN, SiO2, amorphous carbon, or the like, but is not limited thereto.
  • the photoresist layer 123 may be provided on the mask layer 121 .
  • the photoresist layer 123 may be formed in a predetermined pattern on the mask layer 121 through a lithography process.
  • the photoresist layer 123 may be patterned to be formed in the center of the device unit region of the high electron mobility transistor.
  • regions other than the patterned photoresist layer 123 in the stacked structure 110 may be etched.
  • vertical etching may be performed up to a portion of the channel layer 113 . That is, in areas other than the patterned photoresist layer 123 , the mask layer 121 , the cap layer 119 , the etch stop layer 117 , and the barrier layer 115 are etched, and up to a portion of the channel layer 113 . can be etched.
  • the etching may be performed by wet etching or dry etching.
  • the etching may be performed in three steps. First, etching may be performed to remove even the cap layer 119 from areas other than the patterned photoresist layer 125 . Next, etching may be performed to remove the etch stop layer 117 . Next, etching may be performed from the barrier layer 115 to a portion of the channel layer 113 .
  • the etched stacked structure 110 ′ has a horizontal surface (a surface etched to a partial depth of the channel layer 113 in FIG. 2 ) S1 exposed by etching and a vertical surface (the mask layer 121 in FIG. 2 ). ) of the lower channel layer 113 , the barrier layer 115 , the etch stop layer 117 , and the cap layer 119 ) ( S2 ).
  • etching when etching a region other than the patterned photoresist layer 123 , the mask layer 121 , the cap layer 119 , the etch stop layer 117 , and the barrier layer 115 . , and even the channel layer 113 may be etched. That is, etching may be performed until the surface of the buffer layer 111 is exposed.
  • the first regrowth layer 131 may be formed in the etched region of the etched stack structure 110 ′ through a selective regrowth technique.
  • the first regrowth layer 131 may be grown along the surface of the etched stack structure 110 ′. That is, the first regrowth layer 131 may be respectively formed along the horizontal surface S1 and the vertical surface S2 in the etched stack structure 110 ′.
  • the first regrowth layer 131 is formed along the horizontal surface S1 , it is in electrical contact with the channel layer 113 on the upper surface of the channel layer 113 .
  • the first regrowth layer 131 is formed along the vertical surface S2 , it surrounds the side surfaces of the channel layer 113 , the barrier layer 115 , the etch stop layer 117 , and the cap layer 119 .
  • the first regrowth layer 131 when the first regrowth layer 131 is formed along the vertical surface S2 , it may grow to a height corresponding to the cap layer 119 .
  • the first regrowth layer 131 may be formed of a material having high etch selectivity during a gate recess process, which will be described later. That is, the first regrowth layer 131 may be formed of a material having a higher etch selectivity than the cap layer 119 etched in a gate recess process. In this case, the first regrowth layer 131 is used as an etch stop layer in the etching process for the gate recess.
  • the first regrowth layer 131 may be made of n-type doped InP, but is not limited thereto.
  • a second regrowth layer 133 may be formed on the first regrowth layer 131 through a selective regrowth technique. That is, the second regrowth layer 133 may be formed through selective regrowth in a region defined by the first regrowth layer 131 .
  • the second regrowth layer 133 may grow to a height of the first regrowth layer 131 (ie, a height corresponding to the cap layer 119 ).
  • the second regrowth layer 133 may be formed of a semiconductor material doped with a high concentration to have a low sheet resistance while lowering a contact resistance with an electrode.
  • the second regrowth layer 133 may be formed of a semiconductor material doped with n-type (eg, a material selected from GaAs, InAs, and InxGa1-xAs), but is not limited thereto.
  • the first regrowth layer 131 and the second regrowth layer 133 are formed by a metal-organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. can be grown through In this way, the first regrowth layer 131 and the second regrowth layer 133 may be formed in the etched region of the stack structure 110 ′ through a multilayer selective regrowth technique.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • each electrode of the high electron mobility transistor 100 may be formed. That is, the source electrode 135 and the drain electrode 137 may be respectively formed on the second regrowth layer 133 , and the gate electrode 139 may be formed on the barrier layer 115 .
  • each electrode of the high electron mobility transistor 100 may be formed by a known method.
  • the source electrode 135 and the drain electrode 137 may be respectively formed by removing the mask layer 121 and depositing a conductive material on the second regrowth layer 133 .
  • an insulating layer 141 may be formed on the cap layer 121 between the source electrode 135 and the drain electrode 137 .
  • the gate electrode 139 may be formed after performing a gate recess process for etching the insulating layer 141 and the cap layer 119 in order to secure a space for forming the gate electrode 139 .
  • the gate electrode 139 may be formed in a T shape.
  • the first regrowth layer 131 is made of a material having a higher etch selectivity than the cap layer 119 , it functions as an etch stop layer during a gate recess process. That is, since the first regrowth layer 131 acts as an etch stop layer on the side surface of the cap layer 119 and the etch stop layer 117 exists under the cap layer 119 , only the cap layer 119 portion is etched. and thus, accuracy and stability with respect to the size of the gate recess (GR) region can be secured, and a device with high reliability and reproducibility can be manufactured.
  • GR gate recess
  • the size of the gate recess region is limited by the first regrowth layer 131 and the etch stop layer 117 during the gate recess process, accuracy and stability with respect to the size of the gate recess GR region can be secured. be able to do
  • a portion is etched using the patterned photoresist layer 123 in the stacked structure 110 , and the first regrowth layer 131 and the second regrowth layer 133 are formed in the etched region. , it is possible to secure the accuracy and stability of the size of the gate recess region.
  • the first regrowth layer 131 contacts the side surface of the channel layer 113 to form a low contact resistance
  • the barrier layer 115 is disposed between the source electrode 135 and the drain electrode 137 and the channel layer 113 . ) is removed, it is possible to reduce the parasitic resistance component caused by the barrier layer 115, thereby improving the device performance.
  • FIG. 7 is a scanning electron microscope photograph showing a state in which the first regrowth layer 131 acts as an etch stop layer in a gate recess process according to an embodiment of the present invention.
  • InP was used as the first regrowth layer 131 .
  • FIG. 7 it can be seen that only the cap layer is removed by etching and the etching is inhibited by the first regrowth layer 131 on the side surface.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne un transistor à haute mobilité d'électrons et son procédé de fabrication. Un procédé de fabrication d'un transistor à haute mobilité d'électrons selon un mode de réalisation de la présente invention comprend les étapes consistant à : former une structure empilée dans laquelle une couche tampon, une couche de canal, une couche barrière, une couche d'arrêt de gravure, une couche de recouvrement, une couche de masque et une couche de résine photosensible à motifs sont empilées séquentiellement ; graver des régions autres que la couche de résine photosensible à motifs dans la structure empilée ; former chacune d'une première couche de recroissance et d'une seconde couche de recroissance dans les régions gravées de la structure empilée par l'intermédiaire d'une technique de recroissance sélective ; et former chacune d'une électrode de source et d'une électrode de drain sur la surface supérieure de la seconde couche de recroissance, et former une électrode de grille espacée à la fois de l'électrode de source et de l'électrode de drain.
PCT/KR2021/018823 2020-12-11 2021-12-13 Transistor à haute mobilité d'électrons et son procédé de fabrication WO2022124868A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2020-0173523 2020-12-11
KR20200173523 2020-12-11
KR1020210175998A KR102628555B1 (ko) 2020-12-11 2021-12-09 고전자이동도 트랜지스터 및 그 제조방법
KR10-2021-0175998 2021-12-09

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WO2022124868A1 true WO2022124868A1 (fr) 2022-06-16

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070032701A (ko) * 2004-05-20 2007-03-22 크리 인코포레이티드 재성장된 오믹 콘택 영역을 갖는 질화물계 트랜지스터의제조방법 및 재성장된 오믹 콘택 영역을 갖는 질화물계트랜지스터
US20140001478A1 (en) * 2012-06-27 2014-01-02 Triquint Semiconductor, Inc. Group iii-nitride transistor using a regrown structure
WO2014003349A1 (fr) * 2012-06-25 2014-01-03 서울반도체 주식회사 Transistor iii-v et son procédé de fabrication
KR20140100692A (ko) * 2013-02-07 2014-08-18 서울대학교산학협력단 ＡｌＧａＮ／ＧａＮ ＨＥＭＴ 소자의 제조 방법
KR102050012B1 (ko) * 2019-05-09 2019-11-28 경북대학교 산학협력단 트랜지스터 및 트랜지스터 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070032701A (ko) * 2004-05-20 2007-03-22 크리 인코포레이티드 재성장된 오믹 콘택 영역을 갖는 질화물계 트랜지스터의제조방법 및 재성장된 오믹 콘택 영역을 갖는 질화물계트랜지스터
WO2014003349A1 (fr) * 2012-06-25 2014-01-03 서울반도체 주식회사 Transistor iii-v et son procédé de fabrication
US20140001478A1 (en) * 2012-06-27 2014-01-02 Triquint Semiconductor, Inc. Group iii-nitride transistor using a regrown structure
KR20140100692A (ko) * 2013-02-07 2014-08-18 서울대학교산학협력단 ＡｌＧａＮ／ＧａＮ ＨＥＭＴ 소자의 제조 방법
KR102050012B1 (ko) * 2019-05-09 2019-11-28 경북대학교 산학협력단 트랜지스터 및 트랜지스터 제조방법

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