CN114496788A - P-type channel gallium nitride transistor and preparation method thereof - Google Patents
P-type channel gallium nitride transistor and preparation method thereof Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 65
- 108010075750 P-Type Calcium Channels Proteins 0.000 title claims abstract description 53
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 25
- 230000001681 protective effect Effects 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 10
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 7
- 230000006911 nucleation Effects 0.000 claims description 7
- 238000010899 nucleation Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 claims description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 2
- 230000002829 reductive effect Effects 0.000 abstract description 6
- 108091006146 Channels Proteins 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 17
- 239000000463 material Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000004528 spin coating Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Abstract
The invention relates to a P-type channel gallium nitride transistor and a preparation method thereof, wherein the preparation method comprises the following steps: step 1: obtaining a wafer with a P-type channel gallium nitride structure; step 2: epitaxially growing heavy growth layers on two sides of the surface of the wafer, wherein the heavy growth layers are heavily doped group III nitride, and a gap is formed between the two heavy growth layers; and step 3: depositing ohmic metal on the surface of the regrowth layer to form a source ohmic contact and a drain ohmic contact; and 4, step 4: depositing a gate dielectric layer on the surface of the wafer which is not covered by the regrown layer and the surface of part of the regrown layer; and 5: and depositing gate metal on the surface of the gate dielectric layer to form a gate electrode. According to the preparation method, the heavily doped P-type channel layer is directly extended on the lightly doped P-type channel layer, so that the high interface state density caused by etching the P-type channel layer under the gate is avoided, the mobility and transconductance of the transistor are improved, the leakage current is reduced, and the problems of unstable threshold voltage, low reliability and the like of the transistor are solved.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a P-type channel gallium nitride transistor and a preparation method thereof.
Background
The gallium nitride material has the excellent properties of wide forbidden bandwidth, high critical breakdown field strength, relatively high mobility, high electronic saturation velocity, relatively high spontaneous polarization coefficient and the like, and the power electronic diode and the transistor manufactured based on the gallium nitride material have the advantages of small on-resistance, high efficiency, short reverse recovery time, high temperature resistance, irradiation resistance and the like, and have great potential in the fields of consumer electronics, household appliances, new energy automobiles, national power grids, photovoltaic inversion, rail transit and the like.
Gallium nitride power electronic transistors currently employ a heterojunction lateral structure with high electron mobility. In order to realize enhancement mode work, a P-type gallium nitride cap layer is added on the upper surface of a conventional barrier layer/channel layer structure to realize the depletion of channel two-dimensional electron gas, and a device channel is in an off state when the grid voltage bias is zero or is suspended. The P-type gallium nitride cap layer can be used for preparing a P-type channel gallium nitride transistor, so that the P-type channel gallium nitride transistor can be combined with a high electron mobility heterojunction structure with N-type two-dimensional electron gas to realize a gallium nitride complementary field effect transistor phase inverter compatible with a gallium nitride high electron mobility power electronic device.
The preparation method of the conventional P-type channel gallium nitride transistor is realized by a method based on grid groove etching, namely, firstly, preparing a gallium nitride high electron mobility power electronic transistor wafer with a layer of P-type gallium nitride cap layer of about 80nm, etching the wafer in a grid region, partially removing the P-type gallium nitride cap layer, leaving a P-type gallium nitride channel layer of about 15nm, and preparing ohmic contact electrodes in other regions of the original P-type gallium nitride cap layer.
However, the preparation method brings etching damage to the upper surface of the P-type gallium nitride channel in the gate region, so that an additional interface state is introduced, the mobility of the P-type gallium nitride channel is reduced, the current of the P-type gallium nitride channel transistor is reduced, and the stability and reliability of the current of the P-type gallium nitride channel transistor are affected. In addition, the uniformity and batch repeatability of the etching process on large-sized wafers are difficult to control.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a P-channel gan transistor and a method for fabricating the same. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a preparation method of a P-type channel gallium nitride transistor, which comprises the following steps:
step 1: obtaining a wafer with a P-type channel gallium nitride structure;
step 2: epitaxially growing heavy growth layers on two sides of the surface of the wafer, wherein the heavy growth layers are heavily doped group III nitride, and a gap is formed between the two heavy growth layers;
and step 3: depositing ohmic metal on the surface of the regrowth layer to form ohmic contact of a source electrode and ohmic contact of a drain electrode;
and 4, step 4: depositing a gate dielectric layer on the surface of the wafer which is not covered by the regrowth layer and the surface of part of the regrowth layer;
and 5: and depositing gate metal on the surface of the gate dielectric layer to form a gate electrode.
In one embodiment of the invention, the wafer comprises a substrate, a nucleating layer, a buffer layer, an n-type channel layer, a barrier layer and a P-type channel layer which are sequentially stacked from bottom to top.
In one embodiment of the present invention, the step 2 comprises:
step 2.1: depositing a protective dielectric layer on the surface of the wafer;
step 2.2: etching two sides of the protective dielectric layer by adopting a photoetching process, and removing the protective dielectric layers on two sides of the surface of the wafer;
step 2.3: epitaxially growing a regrown layer on the part of the surface of the wafer which is not covered by the protective dielectric layer;
step 2.4: and stripping and removing the protective dielectric layer by adopting BOE.
In an embodiment of the present invention, the material of the regrown layer is gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, and the doping concentration is 1.0 × 1018-1.0×1020cm-3The thickness is 5-200 nm.
In one embodiment of the present invention, the gate dielectric layer is made of aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, or zirconium oxide, and has a thickness of 5-100 nm.
In one embodiment of the invention, the material of the n-type channel layer is unintentionally doped gallium nitride, and the thickness of the n-type channel layer is 50-500 nm;
the barrier layer is made of aluminum gallium nitride, indium aluminum nitride or aluminum nitride, and the thickness of the barrier layer is 5-20 nm;
the P-type channel layer is made of gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, and the doping concentration is 1.0 multiplied by 1018-1.0×1020cm-3The thickness is 5-30 nm.
In an embodiment of the invention, the material of the protective dielectric layer is silicon oxide or silicon nitride, and the thickness thereof is 100-1000 nm.
The invention provides a P-type channel gallium nitride transistor, which is prepared by adopting the method of any one of the embodiments, and comprises the following components:
the substrate, the nucleating layer, the buffer layer, the n-type channel layer, the barrier layer and the P-type channel layer are sequentially stacked from bottom to top;
the regrowth layers are positioned on two sides of the surface of the P-type channel layer, the regrowth layers are heavily doped group III nitride, and a gap is formed between the two regrowth layers;
a source electrode and a drain electrode disposed on the regrowth layer;
the gate dielectric layer is arranged on the surface of the P-type channel layer which is not covered by the regrowth layer and the surface of part of the regrowth layer;
and the gate electrode is arranged on the gate dielectric layer.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the preparation method of the P-type channel gallium nitride transistor, the heavily doped P-type channel layer is directly extended on the lightly doped P-type channel layer, so that high interface state density caused by etching the P-type channel layer under a gate is avoided, the mobility and transconductance of the transistor are improved, the leakage current is reduced, and the problems of unstable threshold voltage, low reliability and the like are solved;
2. the preparation method of the P-type channel gallium nitride transistor is compatible with the conventional process of the existing P-type cap layer gallium nitride high electron mobility power electronic transistor, and has the advantages of simple manufacturing process and low cost.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic view of a method for fabricating a P-channel gan transistor according to an embodiment of the present invention;
FIGS. 2a-2g are flow charts of a process for fabricating a P-channel GaN transistor according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of a P-channel GaN transistor according to an embodiment of the invention;
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a P-channel gan transistor and a method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings and the following detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Example one
Referring to fig. 1, fig. 1 is a schematic view of a method for fabricating a P-channel gan transistor according to an embodiment of the present invention, where the method for fabricating a P-channel gan transistor according to the embodiment includes:
step 1: obtaining a wafer with a P-type channel gallium nitride structure;
in the embodiment, the wafer comprises a substrate, a nucleation layer, a buffer layer, an n-type channel layer, a barrier layer and a P-type channel layer which are sequentially stacked from bottom to top.
Optionally, the material of the substrate is silicon, sapphire, silicon carbide or aluminum nitride.
Optionally, the material of the nucleation layer is aluminum nitride, and the thickness of the nucleation layer is 50-200 nm.
Optionally, the buffer layer is made of high-insulation gallium nitride and has a thickness of 0.5-20 μm.
Optionally, the n-type channel layer is formed of unintentionally doped gallium nitride with a thickness of 50-500 nm.
Optionally, the barrier layer is made of AlGaN, InAlN or AlN and has a thickness of 5-20 nm.
Optionally, the P-type channel layer is made of GaN or InGaN, the doping impurity is Mg or Zn, and the doping impurity is doped with GaN or InGaNThe impurity concentration is 1.0 × 1018-1.0×1020cm-3The thickness is 5-30 nm.
Step 2: epitaxially growing heavy growth layers on two sides of the surface of the wafer, wherein the heavy growth layers are heavily doped group III nitride, and a gap is formed between the two heavy growth layers;
specifically, step 2 comprises:
step 2.1: depositing a protective dielectric layer on the surface of the wafer;
in this embodiment, the material of the protection dielectric layer is silicon oxide or silicon nitride, and the thickness thereof is 100-1000 nm.
Optionally, a protective dielectric layer is deposited on the surface of the P-type channel layer by adopting a PECVD, LPCVD, ICPCVD or APCVD process.
Step 2.2: etching the two sides of the protective medium layer by adopting a photoetching process, and removing the protective medium layers on the two sides of the surface of the wafer;
specifically, a photoresist is coated on the surface of the protective dielectric layer in a spinning mode, a photoetching machine is used for exposing and developing an etching area, then the dielectric layer is etched, the protective dielectric layers on two sides of the surface of the P-type channel layer are removed, and then the photoresist is removed.
Step 2.3: epitaxially growing a regrowth layer on the part of the surface of the wafer which is not covered by the protective dielectric layer;
in this embodiment, the regrown layer is made of gan or ingan, the dopant impurity is Mg or Zn, and the dopant concentration is 1.0 × 1018-1.0×1020cm-3The thickness is 5-200 nm.
It should be noted that the material of the regrowth layer may be different from the material of the P-type channel layer, and the doping impurities thereof should be consistent. The heavy growth layer is heavily doped to form ohmic contacts and the channel layer is lightly doped to form 2DHG channels. Preferably, the material of the regrowth layer is the same as the material of the P-type channel layer, in this embodiment, the material of the regrowth layer and the material of the P-type channel layer are both P-type gallium nitride, and the doping impurity is Mg.
Step 2.4: and stripping and removing the protective dielectric layer by adopting BOE.
And step 3: depositing ohmic metal on the surface of the regrowth layer to form a source ohmic contact and a drain ohmic contact;
in the embodiment, the metal material of the source ohmic contact and the drain ohmic contact is Ni/Au laminated metal, wherein the thickness of Ni is 5-30nm, and the thickness of Au is 5-30 nm.
Specifically, step 3 includes:
spin-coating photoresist on the surfaces of the regrowth layer and the P channel layer, exposing and developing the ohmic contact region by using a photoetching machine, depositing Ni/Au laminated metal on the surface of the regrowth layer by using electron beam evaporation, then removing the photoresist, and finally forming source ohmic contact and drain ohmic contact on the surface of the regrowth layer through annealing treatment.
And 4, step 4: depositing a gate dielectric layer on the surface of the wafer which is not covered by the regrown layer and the surface of part of the regrown layer;
in this embodiment, the gate dielectric layer is made of aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, or zirconium oxide, and has a thickness of 5-100 nm.
Optionally, an aluminum oxide gate dielectric is deposited on the surface of the P-type channel layer and the surface of the partial regrowth layer by Atomic Layer Deposition (ALD).
And 5: and depositing gate metal on the surface of the gate dielectric layer to form a gate electrode.
In this embodiment, the gate metal material is a Ti/Au stacked metal with a thickness of 20-500 nm.
Specifically, step 5 comprises:
and spin-coating photoresist on the surface of the device, exposing and developing the deposited gate metal region by using a photoetching machine, and depositing Ti/Au laminated metal on the surface of the gate dielectric layer to form a gate electrode.
According to the preparation method of the P-type channel gallium nitride transistor, the heavily doped P-type channel layer is directly extended on the lightly doped P-type channel layer in an epitaxial manner, so that the high interface state density caused by etching the P-type channel layer under the gate is avoided, the mobility and transconductance of the transistor are improved, the leakage current is reduced, and the problems of unstable threshold voltage, low reliability and the like are solved.
Example two
In this embodiment, a method for manufacturing a P-channel gan transistor according to the first embodiment is specifically described by taking gan doped with Mg as an example of a regrown layer. Referring to fig. 2a-2g, fig. 2a-2g are flow charts of a process for fabricating a P-channel gan transistor according to an embodiment of the present invention. As shown in the figure, the specific preparation steps include:
step 1: epitaxially growing an AlN nucleation layer 201, a GaN buffer layer 202, a GaN channel layer 203, and Al on a Si substrate 200 in this order0.15Ga0.85An N-barrier layer 204 and a P-type GaN channel layer 205, as shown in fig. 2 a.
In this embodiment, the AlN nucleation layer 201 has a thickness of 0.8nm, the GaN buffer layer 202 has a thickness of 4 μm, the GaN channel layer 203 has a thickness of 300nm, and Al0.15Ga0.85The N barrier layer 204 has a thickness of 15nm, the P-type GaN channel layer 205 has a thickness of 15nm, the doping impurity is Mg, and the doping concentration is 1.0 × 1019cm-3。
Step 2: epitaxially growing SiO on the surface of the P-type GaN channel layer 205 by PECVD2The dielectric layer 1a, having a thickness of 100nm, is shown in FIG. 2 b.
And step 3: in SiO2Spin-coating photoresist on the surface of the dielectric layer 1a, exposing and developing the etched region by using a photoetching machine, and carrying out SiO (silicon dioxide) etching2Etching the dielectric layer 1a to remove SiO on two sides of the surface of the P-type GaN channel layer 2052Dielectric layer 1a and then the photoresist is removed as shown in fig. 2 c.
And 4, step 4: SiO does not form on the P-type GaN channel layer 2052The portion covered by the dielectric layer 1a is epitaxially grown with a P-type gan regrown layer 206 as shown in fig. 2 d.
In this embodiment, the dopant impurity of the regeneration layer is Mg, and the dopant concentration is 3.0 × 1019cm-3And the thickness is 40 nm.
And 5: by BOE to SiO2The dielectric layer 1a is stripped away as shown in fig. 2 e.
Step 6: spin-coating photoresist on the surfaces of the P-type gallium nitride regrowth layer 206 and the P-type GaN channel layer 205, exposing and developing the ohmic contact region by using a photoetching machine, and depositing Ni/Au laminated metal on the surface of the P-type gallium nitride regrowth layer 206 by using electron beam evaporation.
In this example, the thickness of Ni/Au was 15/20 nm;
and 7: after the photoresist is removed, the device is annealed to form a source ohmic contact 207 and a drain ohmic contact 208 on the surface of the P-type gan regrowth layer 206, as shown in fig. 2 f.
In this embodiment, the annealing temperature is 550 ℃, the annealing time is 5mins, and the annealing atmosphere is an oxygen atmosphere to form ohmic contact.
And 8: an aluminum oxide gate dielectric layer 209 is deposited on the surface of the P-type GaN channel layer 205 and on the surface of a portion of the P-type GaN regrown layer 206 using Atomic Layer Deposition (ALD).
In this embodiment, the thickness of the alumina gate dielectric layer 209 is 30 nm.
And step 9: spin-coating photoresist on the surface of the device, exposing and developing the region where the gate metal is deposited by using a photoetching machine, and depositing Ti/Au laminated metal on the surface of the gate dielectric layer 209 to form a gate electrode 210, as shown in FIG. 2 g.
In this example, the thickness of Ti/Au was 20/150 nm.
The preparation method of the P-type channel gallium nitride transistor of the embodiment is compatible with the conventional process of the existing P-type cap layer gallium nitride high electron mobility power electronic transistor, and has the advantages of simple manufacturing process and low cost.
EXAMPLE III
The present embodiment provides a P-channel gan transistor, which is prepared by the method according to the embodiment, please refer to fig. 3, where fig. 3 is a schematic structural diagram of the P-channel gan transistor according to the embodiment of the present invention, and as shown in the figure, the P-channel gan transistor includes: a substrate 300, a nucleation layer 301, a buffer layer 302, an n-type channel layer 303, a barrier layer 304, and a P-type channel layer 305 stacked in this order from bottom to top; regrowth layers 306 are arranged on two sides of the surface of the P-type channel layer 305, the regrowth layers 306 are heavily doped group III nitride, and an interval exists between the two regrowth layers 306; a source electrode 307 and a drain electrode 308 are arranged on the regrowth layer 306; a gate dielectric layer 309 is arranged on the surface of the P-type channel layer 305 which is not covered by the regrowth layer 306 and the surface of part of the regrowth layer 306; a gate electrode 310 is disposed on the gate dielectric layer 309.
In the P-type channel gallium nitride transistor of the embodiment, in the preparation process, a heavily doped P-type channel layer is directly epitaxially grown on the lightly doped P-type channel layer, so that high interface state density caused by etching the P-type channel layer under a gate is avoided, the mobility and transconductance of the transistor are improved, the leakage current is reduced, and the problems of unstable threshold voltage, low reliability and the like of the P-type channel gallium nitride transistor are solved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element. The directional or positional relationships indicated by "up", "down", "left", "right", etc., are based on the directional or positional relationships shown in the drawings, are merely for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be taken as limiting the invention.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (8)
1. A method for preparing a P-type channel gallium nitride transistor is characterized by comprising the following steps:
step 1: obtaining a wafer with a P-type channel gallium nitride structure;
step 2: epitaxially growing heavy growth layers on two sides of the surface of the wafer, wherein the heavy growth layers are heavily doped group III nitride, and a gap is formed between the two heavy growth layers;
and step 3: depositing ohmic metal on the surface of the regrowth layer to form a source ohmic contact and a drain ohmic contact;
and 4, step 4: depositing a gate dielectric layer on the surface of the wafer which is not covered by the regrowth layer and the surface of part of the regrowth layer;
and 5: and depositing gate metal on the surface of the gate dielectric layer to form a gate electrode.
2. The method of claim 1, wherein the wafer comprises a substrate, a nucleation layer, a buffer layer, an n-type channel layer, a barrier layer, and a P-type channel layer stacked in sequence from bottom to top.
3. The method of manufacturing a P-channel gan transistor according to claim 1, wherein the step 2 comprises:
step 2.1: depositing a protective dielectric layer on the surface of the wafer;
step 2.2: etching two sides of the protective dielectric layer by adopting a photoetching process, and removing the protective dielectric layers on two sides of the surface of the wafer;
step 2.3: epitaxially growing a regrown layer on the part of the surface of the wafer which is not covered by the protective dielectric layer;
step 2.4: and stripping and removing the protective dielectric layer by adopting BOE.
4. The method of claim 1, wherein the regrown layer is made of GaN or InGaN, the dopant impurity is Mg or Zn, and the dopant concentration is 1.0 x 1018-1.0×1020cm-3The thickness is 5-200 nm.
5. The method of claim 1, wherein the gate dielectric layer is made of aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, or zirconium oxide, and has a thickness of 5-100 nm.
6. The method of claim 2, wherein the n-type channel layer is formed by unintentionally doped gan with a thickness of 50-500 nm;
the barrier layer is made of aluminum gallium nitride, indium aluminum nitride or aluminum nitride, and the thickness of the barrier layer is 5-20 nm;
the P-type channel layer is made of gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, and the doping concentration is 1.0 multiplied by 1018-1.0×1020cm-3The thickness is 5-30 nm.
7. The method as claimed in claim 3, wherein the protective dielectric layer is made of silicon oxide or silicon nitride and has a thickness of 100-1000 nm.
8. A P-channel gan transistor fabricated by the method of any of claims 1-7, comprising:
the substrate, the nucleating layer, the buffer layer, the n-type channel layer, the barrier layer and the P-type channel layer are sequentially stacked from bottom to top;
the regrowth layers are positioned on two sides of the surface of the P-type channel layer, the regrowth layers are heavily doped group III nitride, and a gap is formed between the two regrowth layers;
a source electrode and a drain electrode disposed on the regrowth layer;
the gate dielectric layer is arranged on the surface of the P-type channel layer which is not covered by the regrowth layer and the surface of part of the regrowth layer;
and the gate electrode is arranged on the gate dielectric layer.
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