KR102050012B1 - Transistor and Method for manufacturing the same - Google Patents

Abstract

Disclosed are a transistor and a transistor manufacturing method. The transistor manufacturing method comprises the steps of: forming an epitaxial layer and a dielectric layer on a substrate; forming a first resist pattern on the dielectric layer; etching the dielectric layer and resist-stripping a first resist based on the first resist pattern; forming a regrowth area by etching a cap layer based on the etched dielectric layer and growing a regrowth material in the formed regrowth area; forming a second resist pattern on the cap layer having the regrowth material; etching one area of the cap layer based on the formed second resist pattern; and depositing a gate in the etched area. Therefore, a transistor with high reliability and reproducibility can be manufactured.

Description

Transistor and Method for manufacturing the same

The present disclosure relates to a transistor and a method for manufacturing the transistor, and more particularly, to a transistor and a method for manufacturing the transistor using the selective regrowth technology.

In general, high electron mobility transistors (HMETs) are electronic components that play a key role in major national infrastructure projects such as defense and telecommunications because of their excellent electron mobility characteristics and excellent frequency characteristics. In order to improve the electrical and frequency characteristics of the device, optimization of parasitic resistance components and capacitance components is essential.

 Specifically, in order to operate a high electron mobility transistor (HMET) device at high power, it is necessary to increase the breakdown voltage (BVDG) by increasing the drain resistance and lowering the source resistance to improve the current density and transconductance of the transistor. It is preferable.

However, in the method of manufacturing a high electron mobility transistor (HMET) device, the conventional gate recess process has a problem that it is difficult to selectively etch the cap layer, and each parasitic component is difficult to accurately control the etching rate. There is a problem that is difficult to optimize them.

In addition, in the conventional process, since the etching is symmetrically, the gate has a symmetrical structure with the source region and the drain region, and the transistor having the symmetrical structure lowers the resistance between the source and the gate by minimizing the distance between the source and the gate. In this case, the drain resistance is also lowered, and when the drain resistance is increased, the source resistance is also increased.

1 is a view for explaining a recess process used in manufacturing a conventional transistor.

Referring to FIG. 1, a transistor includes a resist layer 40 on an epitaxial layer formed of an etch stop layer 20 and a cap layer 30 on a semiconductor substrate 10. When the resist pattern is formed on the resist layer 40 through an exposure process, the cap layer 30 is etched based on the formed pattern. The etching process is performed to make space for the gate deposition. The gate electrode forming process may be performed by depositing a metal material in a region where the empty space of the cap layer 30 is formed, and removing the resist 40 pattern to form the gate electrode.

The conventional gate electrode formation method of FIG. 1 has a problem because it is difficult to accurately control the etching rate of the cap layer 30. Specifically, the etch rate of the empty space of the cap layer 30 may be appropriately etched by the predetermined area (31a, 31b), further etching (32a, 32b), and less etching. It can be divided into (33).

In the case where etching is further performed (32a, 32b), the distance between the gate and the source is increased than the case of proper etching (31a, 31b), so that the source resistance is increased, and the transistor's current density, transconductance, etc. is decreased. Performance drops.

On the contrary, when less etching is performed (33), the distance between the drain and the gate decreases, thereby lowering the breakdown voltage (BVDG), thereby causing degradation, and increasing the gate resistance, thereby reducing the performance of the transistor. .

On the other hand, there is a need for an asymmetric gate structure that can reduce the source resistance and increase the drain resistance in order to improve the performance of the transistor. Existing transistor manufacturing processes require an additional process for forming a gate having an asymmetric structure. Therefore, there are problems such as an increase in process time and an increase in manufacturing cost.

Therefore, there is a need for a method of precisely controlling etching and manufacturing a transistor in a more simplified process.

The present disclosure is to solve the above problems, an object of the present disclosure to provide a transistor manufacturing method for performing a selective etching process using a regrowth material and a transistor manufactured by the above-described manufacturing method.

Method of manufacturing a transistor according to an embodiment of the present disclosure for achieving the above object, the step of forming an epitaxial layer and a dielectric layer including a buffer layer, a channel layer, a barrier layer, an etch stop layer, a cap layer on a substrate Forming a first resist layer on the dielectric layer, and forming a first resist pattern on the first resist layer, based on the first resist pattern Etching the first resist pattern, forming a regrowth region by etching the cap layer based on the etched dielectric layer, and growing a regrowth material in the formed regrowth region; Forming a second resist layer and forming a second resist pattern on the cap layer in which the regrowth material is present, and forming the second resist (Resist) based on the pattern by a step, and depositing a gate on the region formed by the etching for etching one region of the cap layer.

The etching of the region of the cap layer may include etching the region surrounded by the regrowth material and the etch stop layer based on the regrowth material and the etch stop layer that serve as an etch stop barrier.

In addition, the step of forming the regrowth region may be formed by spaced apart from the first region and the second region, the step of forming the regrowth material may be the step of growing the regrowth material in the first region and the second region. have.

In addition, the depositing of the gate may be performed by asymmetrically forming a first gap and a second gap, wherein the first gap is a gap between the first region where the regrowth material is grown and the gate formed, and the second gap is the It may be a gap between the second region where the regrowth material is grown and the formed gate.

The transistor manufacturing method may further include forming a source electrode in a region adjacent to the first region and forming a drain electrode in a region adjacent to the second region, and depositing the gate may include: The first interval may be smaller than the second interval.

The gate may be formed in a T shape.

In addition, the regrowth material and the etch stop layer may include a P component, and the cap layer may include an As component. Specifically, the etch stop layer may be formed of a material that is not etched while the cap layer is etched among the material including the InP component. The cap layer may be formed of a GaAs-based material among materials including an As component.

According to various embodiments of the present disclosure, the transistor manufacturing method may control the etching process by using an etching selectivity of the regrowth material, thereby securing stability of the size of the region where the gate is to be deposited. In the transistor manufacturing method, a transistor having high reliability and high reproducibility can be manufactured.

In addition, the transistor manufacturing method can produce a high performance, high efficiency transistor with optimized parasitic components through an asymmetric structure.

Effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view of a recess process conventionally used in manufacturing a transistor.
2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a transistor according to the present disclosure.
3A and 3B illustrate a transistor according to another embodiment of the present disclosure.
4 is a flowchart illustrating a transistor manufacturing method according to an embodiment of the present disclosure.

Terms used herein will be briefly described, and the present disclosure will be described in detail.

Terms including ordinal numbers such as first and second may be used to describe various components, but these components are not limited by the terms described above. The terms described above are used only for the purpose of distinguishing one component from another.

In this specification, the terms "comprises" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In the description of the present invention, the order of each step is to be understood without limitation unless the preceding step is to be performed logically and temporally prior to the later step. That is, except for the exceptional case described above, even if the process described as the following step is performed in advance of the process described as the preceding step, the nature of the invention is not affected and the scope of rights should be defined regardless of the order of the steps.

In this specification, only essential components necessary for the description of the present invention are described, and components not related to the nature of the present invention are not mentioned. It should not be construed in an exclusive sense that includes only the constituent elements but in a non-exclusive sense, which may also include other components.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the above-described specific embodiment, the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

Hereinafter, various embodiments will be described in more detail with reference to the accompanying drawings. Embodiments described herein may be variously modified. Specific embodiments are depicted in the drawings and may be described in detail in the detailed description. However, the specific embodiments disclosed in the accompanying drawings are only for easily understanding the various embodiments. Therefore, the technical spirit is not limited by the specific embodiments disclosed in the accompanying drawings, and it should be understood to include all equivalents or substitutes included in the spirit and scope of the invention.

As used herein, the terms "deposition" and "growth" are used in the same sense as forming a semiconductor material layer, and the layer or thin film formed through various embodiments of the present invention is organic metal chemical vapor deposition (Metal- Organic Chemical Vapor Deposition (MOCVD) method or Molecular Beam Epitaxy (MBE) method can be grown in the growth chamber (chamber), PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method, It may be deposited and formed by various methods such as resistance heating. In the case of using the organometallic chemical vapor deposition (MOCVD) method, the flow rate of the gas injected therein can be determined according to the volume of the MOCVD reaction chamber, and the thin film is grown according to the type of gas, the pressure inside the reaction chamber, and the temperature conditions. The thickness, surface roughness, doped concentration of the dopant and the like may vary. In particular, the higher the temperature, the better the crystallinity of the thin film can be obtained, which should be limited in consideration of the physical properties of the reaction gas, the temperature at which the reaction occurs. In particular, ALD (Atomic Layer Deposition) method can be used for precise growth. According to the ALD method, the thin film growth can be controlled on an atomic basis.

2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a transistor according to the present disclosure.

Referring to FIG. 2A, a substrate 210 is provided according to an embodiment of a transistor manufacturing method. An epitaxial layer 220 including a buffer layer 221, a channel layer 222, a barrier layer 223, an etch stop layer 224, and a cap layer 225 may be formed on an upper surface of the substrate 210. The dielectric layer 230 may be formed on the epitaxial layer 220. After the first resist layer 240 is coated (or coated) on the upper surface of the dielectric layer 230, a first resist pattern may be formed through lithography.

For example, the first resist may be a photo resist or an E-beam resist. Here, the lithography for forming a resist pattern may be an ultraviolet (UV), deep UV, extreme UV, or lithography using an electron beam. have. The substrate 210 may be a GaAs-based or InP-based material for manufacturing a high electron mobility transistor (HEMT), and may include a single substrate of a semiconductor material.

2B and 2C, a process of forming a regrowth region is shown. The dielectric layer 230 may be etched based on the formed first resist pattern, and the first resist pattern may be stripped. Here, the etching of the dielectric layer 230 may be dry etching or physicochemical reaction etching, for example, SiO ₂ RIE (Reactive Ion Etching). The etched dielectric layer 230 may serve as a hard mask in the etching process of the cap layer 225. The cap layer 225 may be etched based on the etched dielectric layer 230 to form regrowth regions 3a and 3b. The regrowth regions 3a and 3b may be spaced apart from each other. Here, the etch stop layer 224 may be made of a material that is not etched while the cap layer 225 is etched among the material including the InP component. The cap layer 225 may be made of a GaAs-based material among materials including an As component.

2D and 2E, a regrowth process of a regrowth material is shown. In the regrowth process of the regrowth material, the regrowth regions 3a and 3b may serve as hard masks. The regrowth material may be grown in the regrowth regions 3a and 3b formed by etching the cap layer 225 based on the dielectric layer 230. For example, the regrowth material may be an InP-containing material and may be selectively grown using organometallic chemical vapor deposition (MOCVD). Since the regrowth regions 3a and 3b are spaced apart from each other, the regrowth material may be formed to be spaced apart from the first region 3a and the second region 3b. After the etching process, the etchant and the dielectric layer remaining on the epitaxial layer 220 may be removed through a cleaning process. For example, the remaining etchant may be SiO ₂ , and a BOE solution may be used for cleaning.

Referring to FIG. 2F, the second resist layer 250, the PMGI layer 260, and the third resist layer are disposed on the regrowth regions 3a and 3b where the remaining cap layer 225 and the regrowth material are present. 270 may be coated (or applied). For example, the second and third resist layers 250 and 270 may be a photo resist or an E-beam resist.

As shown in FIG. 2F, a wet etching process of etching the PMGI layer 260 after lithography is performed to form a third resist pattern on the third resist layer 270. This can be done. In addition, lithography may be performed to form a second resist pattern on the second resist layer 250 exposed through the etching of the PMGI layer 260. For example, ultraviolet (UV), deep UV, extreme UV, and E-beam may be used for lithography.

The cap layer surrounded by the second resist layer 250, the etch stop layer 224, the first region 3a on which the regrowth material is formed, and the second region 3b based on the second resist pattern. One region of 1 may be wet etched. The width of one region 1 of the enclosed cap layer may be determined by the distance between the first region 3a and the second region 3b on which the regrowth material is formed. The gap between the first region 3a and the second region 3b may be formed in the same manner as the design specification through the above-described process.

In addition, the regrowth material and the etch policy layer 224 formed in the first region 3a and the second region 3b may serve as an etch stop barrier. Thus, even if one region 1 of the enclosed cap layer is wet etched for a sufficiently long time, the region of the encapsulated cap layer can be etched as much as the region conforming to the design without causing problems due to excessive etching. Thus, the size of one region 1 of the enclosed cap layer can be precisely controlled.

 A gate metal may be deposited in one region 1 of the etched enclosed cap layer. In this case, the gate may be a T-shaped gate whose upper portion is wider than the lower portion. For example, the gate metal may be a gate only metal including Ti / Pt / Au.

2G, a transistor manufactured in accordance with one embodiment of the present disclosure is finally shown. In the gate deposition process of forming the gate 280, a gate metal may be deposited on the third resist layer 270 and the second resist layer 250 of FIG. 2F. The gate metal, the second resist layer 250, the PMGI layer 260, and the third resist layer 270 deposited on the second and third resist layers 250 and 270 may be formed. Can be removed together using a lift-off process. For example, acetone may be penetrated between the second resist layer 250 and the cap layer 225 to form the second resist layer 250, the PMGI layer 260, and the third resist. The gate metal deposited on layer 270 and third resist layer 270 may be removed together. As a result, as shown in FIG. 2G, the T-shaped gate electrode 280 may be formed.

2G illustrates a T-shaped gate electrode, but is not limited thereto. For example, the gate shape may be Fin type, the upper part is wider than the lower part (Γ type), the upper and lower gate widths are the same, the lower part is wider than the upper part, and the cross section is dozens of characters. The shape of the gate may be formed in various shapes. Depending on the shape of the gate, some orders of the exposure process and the etching process may be changed, and some of the processes may be added.

3A and 3B illustrate a transistor according to another embodiment of the present disclosure. An interval between the first region 3a on which the regrowth material is formed and the gate 280 is defined as a first interval A, and an interval between the second region 3b on which the regrowth material is formed and the gate 280 is defined as a second interval ( It is defined as B). In the transistor manufacturing method of the present disclosure, as illustrated in FIG. 2G, the first gap A and the second gap B may be symmetrically formed. In addition, the transistor manufacturing method of the present disclosure may form the first interval A and the second interval B asymmetrically without additional process.

Referring to FIG. 3A, a transistor manufacturing process having an asymmetric gate structure may be performed in the same process as the manufacturing process described above with reference to FIGS. 2A to 2G. 2A to 2E, the description of the same process will be omitted and the difference between the processes for generating an asymmetric gate structure will be described. Referring to FIG. 2E, the first and second regions 3a and 3b are spaced apart from each other. The second resist layer 250, the PMGI layer 260, and the third resist layer 270 may be coated (or applied) on the remaining cap layer 225. In addition, an exposure process may be performed on the second resist layer 250 and the third resist layer 270, and a wet etching process may be performed on the PMGI layer 260. However, in order to manufacture a transistor having an asymmetric gate structure, lithography performed on the second resist layer 250 and the third resist layer 270 is performed in the first region 3a. Alternatively, the operation may be performed in close proximity to one of the second regions 3b. Subsequently, when the same etching process, gate deposition process, and lift-off process as the conventional method of fabricating a transistor having a symmetrical structure are performed, a transistor having an asymmetric gate structure as shown in FIG. 3A may be manufactured. Can be.

Here, after the gate electrode 280 is formed adjacent to the first region 3a, a source electrode (not shown) is formed in the cap layer 225 adjacent to the first region 3a, and the cap layer adjacent to the second region 3b. A drain electrode (not shown) may be formed at 225.

Referring to FIG. 3B, FIG. 3B illustrates a case in which a source electrode is formed in a region adjacent to the first region 3a and a drain electrode is formed in a region adjacent to the second region 3b.

Here, the first gap A between the first region 3a and the gate 280 may be smaller than the second gap B between the second region 3b and the gate 280. Since the first gap A between the gate 280 and the first region 3a acts as a source resistance, when the first gap is small, the current density and the transconductance of the transistor are increased, thereby improving the performance of the transistor. In addition, since the second gap B between the gate 280 and the second region 3b acts as a drain resistance, when the mode is set to a large value, the output conductance of the transistor decreases to increase the maximum oscillation frequency. As the breakdown voltage (BVDG) of the liver increases, deterioration characteristics may be improved.

According to another exemplary embodiment of the present disclosure, in the transistor manufacturing method, a lithography of the second resist layer 250 is performed in proximity to one of the first region 3a and the second region 3b. Only a transistor having an asymmetric gate structure can be formed.

Therefore, no further process for manufacturing a transistor of an asymmetrical gate structure is required, and the time and economic losses of the additional process may not occur.

4 is a flowchart illustrating a transistor manufacturing method according to an embodiment of the present disclosure.

Referring to FIG. 4, a transistor manufacturing process according to an embodiment of the present disclosure may include a buffer layer 221, a channel layer 222, a barrier layer 223, an etch stop layer 224, and a cap layer on a substrate 210. An epitaxial layer 220 and a dielectric layer 230 including 225 are formed (S110). In the transistor fabrication process, a first resist layer is formed on the dielectric layer 230, and a first resist pattern is formed on the first resist layer 240 (S120).

For example, the first resist 240 may be a photo resist or an E-beam resist. Here, the lithography for forming a resist pattern may be an ultraviolet (UV), deep UV, extreme UV, or lithography using an electron beam. have. The substrate 210 may be a GaAs-based or InP-based material for manufacturing a high electron mobility transistor (HEMT), and may include a single substrate of a semiconductor material.

In the transistor fabrication process, the dielectric layer 230 is etched based on the formed first resist pattern, and the first resist pattern is resist stripped (S130). Here, the etching of the dielectric layer 230 may be dry etching or physicochemical reaction etching, for example, SiO ₂ RIE (Reactive Ion Etching).

In the transistor fabrication process, the cap layer 225 is etched based on the etched dielectric layer 230 serving as a hard mask. In the transistor manufacturing process, the regrowth material is grown in the regrowth regions 3a and 3b generated by etching the cap layer 225 (S140). In one example, the regrowth material may be a material containing InP, and may be selectively grown using organometallic chemical vapor deposition (MOCVD). In addition, since the regrowth regions 3a and 3b are spaced apart from each other, the regrowth material may also be formed to be spaced apart from the first region 3a and the second region 3b.

In the transistor fabrication process, the second resist layer 250, the PMGI layer 260, and the third resist layer 270 are coated (or applied) on the cap layer 225 where the regrowth material is present. do. For example, the second resist layer 250 and the third resist layer 270 may be a photo resist or an E-beam resist.

The transistor fabrication process forms a third resist pattern on the third resist layer 270 using lithography, and then performs a wet etching process on the PMGI layer 260. In the transistor fabrication process, the second resist layer 250 exposed by etching the PMGI layer 260 is formed using an e-beam lithography to form a second resist pattern (S150). ). Here, the lithography for forming a resist pattern may be an ultraviolet (UV), deep UV, extreme UV, or lithography using an electron beam. have.

In the transistor fabrication process, a cap layer surrounded by the second resist layer 250, the etch stop layer 224, the first region 3a, and the second region 3b is based on the second resist pattern. Wet etching a region (1) of (S160).

The regrowth material present in the first region 3a and the second region 3b may serve as an etch stop barrier, and the size of one region 1 of the enclosed cap layer may be the first region in which the regrowth material exists. 3a) and the second region 3b. Therefore, even if wet etching over a sufficiently long time, it can be etched as much as the area that matches the design without problems due to excessive etching. Thus, the size of one region 1 of the enclosed cap layer can be precisely controlled.

Then, the gate metal is deposited in one region 1 of the etched enclosed cap layer (S170).

Transistor manufacturing method according to an embodiment of the present disclosure can be applied to the HEMT device, the implementation of fine line width wiring, etc., such as devices such as MESFETs, such as a device requiring a gate having a fine and large cross-sectional area, and a precise recess etching process is used Of course, it can be used for the production of the device.

210: semiconductor substrate 220: epitaxial layer
221: buffer layer 222: channel layer
223: barrier layer 224: etch stop layer
225: cap layer
230: dielectric layer 240: first resist layer
250: second resist layer 260: PMGI layer
270: third resist layer 280: gate electrode

Claims (8)

In the method of manufacturing a transistor,
Forming an epitaxial layer and a dielectric layer including an etch stop layer and a cap layer on the substrate;
Forming a first resist layer on the dielectric layer, and forming a first resist pattern on the first resist layer;
Etching the dielectric layer based on the first resist pattern and stripping the first resist pattern;
Forming a regrowth region by etching the cap layer based on the etched dielectric layer, and growing a regrowth material in the formed regrowth region;
Forming a second resist layer on the cap layer in which the regrowth material is present, and forming a second resist pattern;
Etching one region of the cap layer based on the formed second resist pattern; And
And depositing a gate in one region of the etched cap layer. The method of claim 1,
Etching one region of the cap layer may include:
And etching the region surrounded by the regrowth material and the etch stop layer based on the regrowth material and the etch stop layer serving as an etch stop barrier. The method of claim 1,
Forming the regrowth region,
The first region and the second region are formed spaced apart,
Forming the regrowth material,
Growing the regrowth material in the first region and the second region. The method of claim 1,
Deposition of the gate,
Form an asymmetric first and second intervals,
Wherein the first interval is a gap between the first region where the regrowth material is grown and the gate formed, and the second interval is a gap between the second region where the regrowth material is grown and the gate formed. The method of claim 4, wherein
Forming a source electrode in an area adjacent to the first area; And
Forming a drain electrode in an area adjacent to the second area;
Deposition of the gate,
And wherein the first interval is narrower than the second interval. The method of claim 1,
The gate is,
Transistor manufacturing method formed in T shape. The method of claim 1,
The regrowth material and the etch stop layer,
Contains P component,
The cap layer is
A transistor manufacturing method comprising the As component. delete

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