WO2020226453A1 - Transistor and transistor manufacturing method - Google Patents

Transistor and transistor manufacturing method Download PDF

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WO2020226453A1
WO2020226453A1 PCT/KR2020/006093 KR2020006093W WO2020226453A1 WO 2020226453 A1 WO2020226453 A1 WO 2020226453A1 KR 2020006093 W KR2020006093 W KR 2020006093W WO 2020226453 A1 WO2020226453 A1 WO 2020226453A1
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region
layer
transistor
regrowth
forming
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PCT/KR2020/006093
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French (fr)
Korean (ko)
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김대현
백지민
윤도영
조현빈
이인근
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경북대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present disclosure relates to a transistor and a method of manufacturing a transistor, and more particularly, to a transistor and a method of manufacturing a transistor using a selective regrowth technique.
  • HEMT high electron mobility transistor
  • HEMT high electron mobility transistor
  • BV DG breakdown voltage
  • the conventional gate recess process has a problem that it is difficult to selectively etch the cap layer, and it is difficult to accurately control the etching rate, so each parasitic component There is a problem that it is difficult to optimize them.
  • the gate has a symmetric structure with the source and drain regions, and a transistor having a symmetric structure reduces the resistance between the source and the gate by minimizing the distance between the source and the gate. In this case, the drain resistance is also lowered, and when the drain resistance is increased, the source resistance is also increased.
  • 1 is a diagram illustrating a recess process used in manufacturing a conventional transistor.
  • the transistor includes an etch stop layer 20 on a semiconductor substrate 10 and a resist layer 40 on an epitaxial layer formed of a cap layer 30.
  • the cap layer 30 is etched based on the formed pattern.
  • the etching process is performed to secure a space for gate deposition.
  • the gate electrode formation process may be performed by depositing a metal material in a region in which an empty space of the cap layer 30 is formed, and removing all patterns of the resist 40 to form a gate electrode.
  • the conventional method of forming a gate electrode of FIG. 1 has a problem because it is difficult to accurately control an etch rate of the cap layer 30.
  • the etch rate of the empty space of the cap layer 30 is appropriately etched as much as a preset area (31a, 31b), when etching is further performed (32a, 32b), and when etching is less performed. It can be divided into (33).
  • the distance between the gate and the source increases as compared to the case where it is properly etched (31a, 31b), thereby increasing the source resistance and decreasing the current density or transconductance of the transistor. Performance is poor.
  • the present disclosure is to solve the above-described problems, and an object of the present disclosure is to provide a method of manufacturing a transistor using a regrowth material to perform a selective etching process, and a transistor manufactured by the above-described manufacturing method.
  • a method of manufacturing a transistor according to an embodiment of the present disclosure for achieving the above object includes forming an epitaxial layer including a buffer layer, a channel layer, a barrier layer, an etch stop layer, and a cap layer on a substrate, and a dielectric layer.
  • the step of etching one region of the cap layer may be a step of etching a region surrounded by the regrowth material and the etch stop layer based on the regrowth material serving as an etch stop barrier and the etch stop layer.
  • the forming of the regrowth region may be formed by being spaced apart from the first region and the second region, and the forming of the regrowth material may be a step of growing the regrowth material in the first region and the second region. have.
  • a first gap and a second gap are formed asymmetrically, the first gap is a gap between the first region in which the regrowth material is grown and the formed gate, and the second gap is the It may be a gap between the second region in which the regrowth material is grown and the formed gate.
  • the transistor manufacturing method may further include forming a source electrode in a region adjacent to the first region and forming a drain electrode in a region adjacent to the second region, and depositing the gate includes the The first gap may be formed to be narrower than the second gap.
  • the gate may be formed in a T shape.
  • the regrowth material and the etch stop layer may include a P component
  • the cap layer may include an As component
  • the etch stop layer may be formed of a material that is not etched while the cap layer is etched, among materials containing the P component.
  • the cap layer may be implemented with a GaAs-based material among materials containing an As component.
  • the transistor manufacturing method in the method of manufacturing a transistor, by controlling an etching process using an etch selectivity of a regrowth material, stability with respect to the size of a region in which a gate is to be deposited may be secured.
  • the transistor manufacturing method can manufacture a transistor with high reliability and reproducibility.
  • the transistor manufacturing method can manufacture a high-performance, high-efficiency transistor that optimizes parasitic components through an asymmetric structure.
  • 1 is a cross-sectional view of a recess process used in conventional transistor manufacturing.
  • FIGS. 2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a transistor according to the present disclosure.
  • 3A and 3B are diagrams illustrating a transistor according to another exemplary embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a method of manufacturing a transistor according to an exemplary embodiment of the present disclosure.
  • each step should be understood without limitation, unless the preceding step must be performed logically and temporally prior to the subsequent step. That is, except for the above exceptional cases, even if a process described as a subsequent step is performed prior to a process described as a preceding step, the essence of the invention is not affected, and the scope of rights should be defined regardless of the order of the steps.
  • Terms such as “deposition” and “growth” used below have the same meaning as forming a layer of a semiconductor material, and a layer or thin film formed through various embodiments of the present invention may be formed by metal-organic chemical vapor deposition (Metal- Organic Chemical Vapor Deposition (MOCVD) method or molecular beam epitaxy (MBE) method can be used to grow in a growth chamber.
  • MOCVD Metal- Organic Chemical Vapor Deposition
  • MBE molecular beam epitaxy
  • PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method It can be deposited and formed by various methods such as resistance heating method.
  • the flow rate of the gas injected into the MOCVD reaction chamber can be determined according to the volume of the MOCVD reaction chamber, and a thin film that is grown according to the type of gas, the pressure inside the flow rate reaction chamber, and temperature conditions.
  • the properties such as the thickness, surface roughness, and doped concentration of the dopant may vary.
  • the higher the temperature the better the crystallinity of the thin film can be obtained, which should be limitedly determined in consideration of the physical properties of the reaction gas and the temperature at which the reaction occurs.
  • an ALD Atomic Layer Deposition
  • the growth of the thin film can be controlled in atomic units.
  • FIGS. 2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a transistor according to the present disclosure.
  • a substrate 210 is provided according to an embodiment of a method of manufacturing a transistor.
  • An epitaxial layer 220 including a buffer layer 221, a channel layer 222, a barrier layer 223, an etch stop layer 224, and a cap layer 225 may be formed on the upper surface of the substrate 210,
  • a dielectric layer 230 may be formed on the epitaxial layer 220.
  • a first resist pattern may be formed through a lithography process.
  • the first resist may be a photo resist or an E-beam resist.
  • the exposure process (lithography) for forming a resist pattern may be a lithography process using ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam).
  • the substrate 210 may be a GaAs-based or InP-based material to manufacture a high-mobility transistor (HEMT), and may include a single substrate made of a semiconductor material.
  • HEMT high-mobility transistor
  • the dielectric layer 230 may be etched based on the formed first resist pattern, and the first resist pattern may be peeled off (resist strip).
  • etching of the dielectric layer 230 may be dry etching or physicochemical reaction etching, for example, SiO 2 Reactive Ion Etching (RIE).
  • RIE SiO 2 Reactive Ion Etching
  • the etched dielectric layer 230 may serve as a hard mask in an etching process of the cap layer 225.
  • the cap layer 225 may be etched based on the etched dielectric layer 230 to form regrowth regions 3a and 3b.
  • the regrowth regions 3a and 3b may be formed to be spaced apart.
  • the etch stop layer 224 may be formed of a material that is not etched while the cap layer 225 is etched, among materials containing the P component.
  • the cap layer 225 may be implemented with a GaAs-based material among materials containing an As component.
  • a regrowth process of a regrowth material is illustrated.
  • the regrowth regions 3a and 3b may serve as a hard mask.
  • a regrowth material may be grown in the regrowth regions 3a and 3b formed by etching the cap layer 225 based on the dielectric layer 230.
  • the regrowth material may be a material containing InP, and may be selectively grown using an organometallic chemical vapor deposition (MOCVD) method. Since the regrowth regions 3a and 3b are formed to be spaced apart from each other, the regrowth material may also be formed to be spaced apart from the first region 3a and the second region 3b.
  • an etchant and a dielectric layer remaining on the epitaxial layer 220 may be removed through a cleaning process.
  • the remaining etchant may be SiO 2
  • a BOE solution may be used for cleaning.
  • 270 may be coated (or applied).
  • the second and third resist layers 250 and 270 may be photo resists or E-beam resists.
  • a wet etching process of etching the PMGI layer 260 This can be done.
  • a lithography process of forming a second resist pattern on the second resist layer 250 exposed through etching of the PMGI layer 260 may be performed.
  • ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam) may be used for lithography.
  • One area (1) of may be wet etched.
  • the width of one region 1 of the enclosed cap layer may be determined by the spacing between the first region 3a and the second region 3b in which the regrowth material is formed.
  • the spacing between the first region 3a and the second region 3b may be formed to be the same as the design specification through the above-described process process.
  • the regrowth material and the etch stop layer 224 formed in the first region 3a and the second region 3b may serve as an etch stop barrier. Therefore, even if one region 1 of the enclosed cap layer is wet etched over a sufficiently long period of time, a problem due to excessive etching does not occur and as much as a region conforming to the design can be etched. Therefore, the size of the area 1 of the enclosed cap layer can be precisely controlled.
  • a gate metal may be deposited on one region 1 of the etched enclosed cap layer.
  • the gate may be a T-shaped gate whose upper portion is wider than that of the lower portion.
  • the gate metal may be a gate-only metal including Ti/Pt/Au.
  • a transistor manufactured according to an embodiment of the present disclosure is finally shown.
  • a gate metal may be deposited on the third resist layer 270 and the second resist layer 250 of FIG. 2F.
  • the gate metal, the second resist layer 250, the PMGI layer 260, and the third resist layer 270 deposited on the second and third resist layers 250 and 270 are They can be removed together using a lift-off process. For example, acetone is penetrated between the second resist layer 250 and the cap layer 225 to form a second resist layer 250, a PMGI layer 260, and a third resist.
  • the gate metal deposited on the layer 270 and the third resist layer 270 may be removed together.
  • the T-shaped gate electrode 280 may be formed.
  • the T-shaped gate electrode is shown in FIG. 2G, but is not limited thereto.
  • the shape of the gate may be a Fin type, the upper part is wider than the lower part ( ⁇ type), the upper and lower gate widths are the same, the lower part is wider than the upper part, and the cross section is ten.
  • the shape of the gate such as the shape, can be formed in various shapes. Depending on the shape of the gate, the order of the exposure process and the etching process may be changed, and a part of the process may be added.
  • FIG. 3A and 3B are diagrams illustrating a transistor according to another exemplary embodiment of the present disclosure.
  • the interval between the first region 3a where the regrowth material is formed and the gate 280 is defined as a first interval (A), and the interval between the second region 3b where the regrowth material is formed and the gate 280 is a second interval ( B) is defined.
  • the first interval A and the second interval B may be formed symmetrically.
  • the first interval A and the second interval B may be formed asymmetrically without adding a separate process.
  • a process for manufacturing a transistor having an asymmetric gate structure may also be performed in the same process as the manufacturing process described above in FIGS. 2A to 2G. 2A to 2E, the description of the same process will be omitted, and the difference in the process for generating the asymmetric gate structure will be mainly described.
  • the first region 3a and the second region 3b formed spaced apart in FIG. 2E A second resist layer 250, a PMGI layer 260, and a third resist layer 270 may be coated (or applied) on the remaining cap layer 225.
  • a lithography process may be performed on the second resist layer 250 and the third resist layer 270, and a wet etching process may be performed on the PMGI layer 260.
  • a lithography process performed on the second resist layer 250 and the third resist layer 270 is performed in the first region 3a. Alternatively, it may be performed close to one of the second regions 3b. Thereafter, when the same etching process, gate deposition process, and lift-off process as in the conventional method of manufacturing a transistor having a symmetric structure are performed, a transistor having an asymmetric gate structure will be manufactured as shown in FIG. 3A. I can.
  • a source electrode (not shown) is formed on the cap layer 225 adjacent to the first region 3a, and a cap layer adjacent to the second region 3b
  • a drain electrode (not shown) may be formed at 225.
  • FIG. 3B shows a case where a source electrode is formed in a region adjacent to the first region 3a and a drain electrode is formed in a region adjacent to the second region 3b.
  • the first gap A between the first region 3a and the gate 280 may be formed smaller than the second gap B between the second region 3b and the gate 280. Since the first gap A between the gate 280 and the first region 3a acts as a source resistance, when the first gap is small, the current density and transconductance of the transistor increase, thereby improving the performance of the transistor. In addition, since the second gap B between the gate 280 and the second region 3b acts as a drain resistance, if it is set to be appropriately large, the output conductance of the transistor decreases and the maximum oscillation frequency increases, and the drain and gate The breakdown voltage (BV DG ) of the liver increases, so that deterioration characteristics may be improved.
  • BV DG breakdown voltage
  • a lithography process of the second resist layer 250 is performed in proximity to one of the first region 3a or the second region 3b. With just that, a transistor with an asymmetric gate structure can be formed.
  • FIG. 4 is a flowchart of a method of manufacturing a transistor according to an embodiment of the present disclosure.
  • a buffer layer 221, a channel layer 222, a barrier layer 223, an etch stop layer 224, and a cap layer (S110).
  • a first resist layer is formed on the dielectric layer 230 and a first resist pattern is formed on the first resist layer 240 (S120).
  • the first resist 240 may be a photo resist or an E-beam resist.
  • the exposure process (lithography) for forming a resist pattern may be a lithography process using ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam).
  • the substrate 210 may be a GaAs-based or InP-based material to manufacture a high electron mobility transistor (HEMT), and may include a single substrate made of a semiconductor material.
  • HEMT high electron mobility transistor
  • the dielectric layer 230 is etched based on the formed first resist pattern, and the first resist pattern is resist stripped (S130).
  • etching of the dielectric layer 230 may be dry etching or physicochemical reaction etching, for example, SiO 2 Reactive Ion Etching (RIE).
  • the cap layer 225 is etched based on the etched dielectric layer 230 serving as a hard mask.
  • a regrowth material is grown in the regrowth regions 3a and 3b generated by etching the cap layer 225 (S140).
  • the regrowth material may be a material containing InP, and may be selectively grown using an organometallic chemical vapor deposition (MOCVD) method.
  • MOCVD organometallic chemical vapor deposition
  • the regrowth material may be formed to be spaced apart from the first region 3a and the second region 3b.
  • a second resist layer 250, a PMGI layer 260, and a third resist layer 270 are coated (or applied) on the cap layer 225 in which the regrowth material is present. do.
  • the second resist layer 250 and the third resist layer 270 may be a photo resist or an E-beam resist.
  • the transistor manufacturing process after forming a third resist pattern on the third resist layer 270 by using a lithography process, a wet etching process is performed on the PMGI layer 260.
  • the second resist layer 250 exposed by etching the PMGI layer 260 is subjected to an exposure process (E-beam lithography) to form a second resist pattern (S150).
  • the exposure process (lithography) for forming a resist pattern may be a lithography process using ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam). have.
  • the cap layer surrounded by the second resist layer 250, the etch stop layer 224, the first region 3a, and the second region 3b based on the second resist pattern.
  • One area (1) of is wet-etched (S160).
  • the regrowth material present in the first region 3a and the second region 3b may serve as an etch stop barrier, and the size of one region 1 of the enclosed cap layer is the first region ( It is determined by 3a) and the second region 3b. Therefore, even if wet etching is performed over a sufficiently long period of time, a problem due to excessive etching does not occur and as much as an area conforming to the design can be etched. Therefore, the size of the area 1 of the enclosed cap layer can be precisely controlled.
  • a gate metal is deposited on one region 1 of the etched enclosed cap layer (S170).
  • the method of manufacturing a transistor according to an embodiment of the present disclosure may be applied to a HEMT device, a fine line width wiring, etc., and a device requiring a gate having a fine and large cross-sectional area, such as a device such as MESFET, and a precise recess etching process are used. Needless to say, it can be used for the manufacture of devices that can be used.

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Abstract

A transistor and a transistor manufacturing method are disclosed. The transistor manufacturing method comprises the steps of: forming an epitaxial layer and a dielectric layer on a substrate; forming a first resist pattern on the dielectric layer; on the basis of the first resist pattern, etching the dielectric layer and resist-stripping a first resist; on the basis of the etched dielectric layer, forming a regrowth region by etching a cap layer, and growing regrowth material on the regrowth region that has been formed; forming a second resist pattern on the cap layer where the regrowth material is present; etching a region of the cap layer on the basis of the second resist pattern that has been formed; and depositing a gate on the region that has been formed by etching.

Description

트랜지스터 및 트랜지스터 제조방법Transistor and Transistor Manufacturing Method
본 개시는 트랜지스터 및 트랜지스터 제조방법에 대한 것으로, 더욱 상세하게는 선택적 재성장 기술을 응용한 트랜지스터 및 트랜지스터 제조방법에 관한 것이다.The present disclosure relates to a transistor and a method of manufacturing a transistor, and more particularly, to a transistor and a method of manufacturing a transistor using a selective regrowth technique.
일반적으로, 고 전자이동도 트랜지스터(High Electron Mobility Transistor, HEMT)는 우수한 전자 이동도 특성 및 우수한 주파수 특성으로 인하여, 국방, 통신 등의 국가 주요 기반사업에서 핵심적인 역할을 하는 전자부품이다. 소자의 전기적 특성 및 주파수 특성을 향상 시키기 위해서는 기생 저항성분 및 커패시턴스 성분의 최적화가 필수적으로 요구 된다.In general, a high electron mobility transistor (HEMT) is an electronic component that plays a key role in major national infrastructure projects such as defense and telecommunications due to excellent electron mobility characteristics and excellent frequency characteristics. In order to improve the electrical and frequency characteristics of the device, it is essential to optimize the parasitic resistance component and capacitance component.
구체적으로, 고 전자이동도 트랜지스터(HEMT)소자가 고전력에서 동작하기 위해서는 드레인저항을 높여 파괴전압(Breakdown Voltage, BV DG)을 상승시킬 필요가 있으며 소스저항을 낮춰 트랜지스터의 전류밀도와 트랜스컨덕턴스를 개선하는 것이 바람직하다.Specifically, in order for a high electron mobility transistor (HEMT) device to operate at high power, it is necessary to increase the drain resistance to increase the breakdown voltage (BV DG ), and to improve the current density and transconductance of the transistor by lowering the source resistance. It is desirable to do.
다만, 고 전자이동도 트랜지스터(HEMT)소자의 제조방법에서 종래의 게이트 리세스 공정은 캡층을 선택적으로 식각하기 어려운 문제점이 있고, 식각이 되는 정도(Etch Rate)를 정확하게 제어하기 곤란하여 각 기생 성분들을 최적화 하기 어려운 문제점이 있다.However, in the manufacturing method of a high electron mobility transistor (HEMT) device, the conventional gate recess process has a problem that it is difficult to selectively etch the cap layer, and it is difficult to accurately control the etching rate, so each parasitic component There is a problem that it is difficult to optimize them.
또한, 종래의 공정은 식각이 대칭적으로 이루어 지기 때문에 게이트는 소스 영역 및 드레인 영역과 대칭적 구조를 가지며, 대칭적 구조를 가지는 트랜지스터는 소스와 게이트 간의 거리를 최소화함으로써 소스와 게이트 간의 저항을 낮추는 경우 드레인저항도 같이 낮아지며, 드레인저항을 높이는 경우 소스저항도 높아지는 문제점이 존재한다.In addition, in the conventional process, since etching is performed symmetrically, the gate has a symmetric structure with the source and drain regions, and a transistor having a symmetric structure reduces the resistance between the source and the gate by minimizing the distance between the source and the gate. In this case, the drain resistance is also lowered, and when the drain resistance is increased, the source resistance is also increased.
도 1은 종래의 트랜지스터 제조시 사용되는 리세스 공정을 설명하는 도면이다.1 is a diagram illustrating a recess process used in manufacturing a conventional transistor.
도 1을 참조하면, 트랜지스터는 반도체 기판(10)상에 식각정지층(20), 캡층(30)으로 이루어진 에피택셜층 상부에 레지스트층(40)을 포함한다. 레지스트층(40)에 노광공정을 거쳐 레지스트 패턴이 형성되면, 캡층(30)은 형성된 패턴을 기초로 식각된다. 식각 공정은 게이트 증착을 위한 공간을 확보하기 위하여 수행된다. 게이트 전극 형성 공정은 캡층(30)의 빈 공간이 형성된 영역에 금속물질을 증착하고 레지스트(40) 패턴을 모두 제거하여 게이트 전극을 형성하는 방식으로 수행될 수 있다.Referring to FIG. 1, the transistor includes an etch stop layer 20 on a semiconductor substrate 10 and a resist layer 40 on an epitaxial layer formed of a cap layer 30. When a resist pattern is formed on the resist layer 40 through an exposure process, the cap layer 30 is etched based on the formed pattern. The etching process is performed to secure a space for gate deposition. The gate electrode formation process may be performed by depositing a metal material in a region in which an empty space of the cap layer 30 is formed, and removing all patterns of the resist 40 to form a gate electrode.
도 1의 종래 게이트 전극 형성 방법은 캡층(30)의 식각정도(Etch Rate)를 정확하게 제어하기 힘들기 때문에 문제점이 존재한다. 구체적으로 캡층(30)의 빈 공간의 식각정도(rate)는, 기설정된 영역만큼 적절히 식각된 경우(31a, 31b), 식각이 더 수행된 경우(32a, 32b), 및 식각이 덜 수행된 경우(33)로 나눌 수 있다.The conventional method of forming a gate electrode of FIG. 1 has a problem because it is difficult to accurately control an etch rate of the cap layer 30. Specifically, the etch rate of the empty space of the cap layer 30 is appropriately etched as much as a preset area (31a, 31b), when etching is further performed (32a, 32b), and when etching is less performed. It can be divided into (33).
식각이 더 수행된 경우(32a, 32b)에는 적절히 식각된 경우(31a, 31b)보다 게이트와 소스 간의 거리가 증가하게 되어 소스저항이 증가하고, 트랜지스터의 전류밀도나 트랜스컨덕턴스 등이 감소하게 되므로 트랜지스터의 성능이 떨어진다.When the etching is further performed (32a, 32b), the distance between the gate and the source increases as compared to the case where it is properly etched (31a, 31b), thereby increasing the source resistance and decreasing the current density or transconductance of the transistor. Performance is poor.
반대로 식각이 덜 수행된 경우(33)에는 드레인과 게이트 간의 거리가 감소하여 파괴전압(Breakdown Voltage, BV DG)이 낮아져 열화 현상이 발생하고, 게이트 저항이 증가하여 트랜지스터의 성능이 감소되는 문제점이 존재한다. Conversely, when etching is less performed (33), the distance between the drain and the gate decreases, resulting in a lower breakdown voltage (BV DG ), resulting in deterioration, and an increase in gate resistance, resulting in a decrease in transistor performance. do.
한편, 트랜지스터의 성능 향상을 위해 소스저항을 줄이고 드레인저항을 크게 할 수 있는 비대칭적 게이트 구조의 필요성이 존재하는데, 기존의 트랜지스터 제조공정은 비대칭적 구조를 가지는 게이트를 형성하기 위한 추가공정이 필요하기 때문에 공정시간의 증가 및 제조비용의 증가 등의 문제점이 있다.On the other hand, there is a need for an asymmetric gate structure that can reduce the source resistance and increase the drain resistance to improve the performance of the transistor, but the existing transistor manufacturing process requires an additional process to form a gate having an asymmetric structure. Therefore, there are problems such as an increase in processing time and an increase in manufacturing cost.
따라서, 식각을 정확히 제어하고 보다 간소화된 공정으로 트랜지스터를 제조하는 방법이 필요한 실정이다.Accordingly, there is a need for a method of accurately controlling etching and manufacturing a transistor with a more simplified process.
본 개시는 상술한 문제점을 해결하기 위한 것으로, 본 개시의 목적은 재성장 물질을 활용하여 선택적 식각과정을 수행하는 트랜지스터 제조방법 및 상술한 제조방법으로 제조된 트랜지스터를 제공하는 것이다.The present disclosure is to solve the above-described problems, and an object of the present disclosure is to provide a method of manufacturing a transistor using a regrowth material to perform a selective etching process, and a transistor manufactured by the above-described manufacturing method.
이상과 같은 목적을 달성하기 위한 본 개시의 일 실시 예에 따른 트랜지스터의 제조방법은, 기판 상에 버퍼층, 채널층, 배리어층, 식각정지층, 캡층을 포함하는 에피택셜층 및 유전체층을 형성하는 단계, 상기 유전체층 상에 제1 레지스트(resist)층을 형성하고, 상기 제1 레지스트(resist)층에 제1 레지스트(resist) 패턴을 형성하는 단계, 상기 제1 레지스트(resist) 패턴에 기초하여 상기 유전체층을 식각하고, 상기 제1 레지스트(resist) 패턴을 박리(resist strip)하는 단계, 식각된 상기 유전체층에 기초하여 상기 캡층을 식각함으로써 재성장 영역을 형성하고 상기 형성된 재성장 영역에 재성장 물질을 성장시키는 단계, 상기 재성장 물질이 존재하는 상기 캡층 상에 제2 레지스트(resist)층을 형성하고 제2 레지스트(resist) 패턴을 형성하는 단계, 상기 형성된 제2 레지스트(resist) 패턴에 기초하여 상기 캡층의 일 영역을 식각하는 단계, 및 상기 식각으로 형성된 영역에 게이트를 증착하는 단계를 포함한다. A method of manufacturing a transistor according to an embodiment of the present disclosure for achieving the above object includes forming an epitaxial layer including a buffer layer, a channel layer, a barrier layer, an etch stop layer, and a cap layer on a substrate, and a dielectric layer. , Forming a first resist layer on the dielectric layer, and forming a first resist pattern on the first resist layer, the dielectric layer based on the first resist pattern Etching and resisting the first resist pattern, forming a regrowth region by etching the cap layer based on the etched dielectric layer, and growing a regrowth material in the formed regrowth region, Forming a second resist layer on the cap layer in which the regrowth material is present and forming a second resist pattern, a region of the cap layer based on the formed second resist pattern Etching, and depositing a gate in the region formed by the etching.
여기서, 상기 캡층의 일 영역을 식각하는 단계는 식각정지 장벽의 역할을 수행하는 상기 재성장 물질 및 상기 식각정지층에 기초하여 상기 재성장 물질 및 상기 식각정지층으로 둘러싸인 영역을 식각하는 단계 일 수 있다.Here, the step of etching one region of the cap layer may be a step of etching a region surrounded by the regrowth material and the etch stop layer based on the regrowth material serving as an etch stop barrier and the etch stop layer.
또한, 상기 재성장 영역을 형성하는 단계는 제1 영역과 제2 영역이 이격되어 형성되고, 상기 재성장 물질을 형성하는 단계는 상기 제1 영역 및 상기 제2 영역에 상기 재성장 물질을 성장시키는 단계 일 수 있다.In addition, the forming of the regrowth region may be formed by being spaced apart from the first region and the second region, and the forming of the regrowth material may be a step of growing the regrowth material in the first region and the second region. have.
또한, 상기 게이트를 증착하는 단계는 제1 간격과 제2 간격을 비대칭으로 형성하며, 상기 제1 간격은 상기 재성장 물질이 성장된 제1 영역과 상기 형성된 게이트 간의 간격이고, 상기 제2 간격은 상기 재성장 물질이 성장된 제2 영역과 상기 형성된 게이트 간의 간격일 수 있다. In addition, in the step of depositing the gate, a first gap and a second gap are formed asymmetrically, the first gap is a gap between the first region in which the regrowth material is grown and the formed gate, and the second gap is the It may be a gap between the second region in which the regrowth material is grown and the formed gate.
또한, 트랜지스터 제조방법은 상기 제1 영역과 인접한 영역에 소스 전극을 형성하는 단계와 상기 제2 영역과 인접한 영역에 드레인 전극을 형성하는 단계를 더 포함할 수 있고, 상기 게이트를 증착하는 단계는 상기 제1 간격이 상기 제2 간격보다 좁게 형성되는 단계 일 수 있다.In addition, the transistor manufacturing method may further include forming a source electrode in a region adjacent to the first region and forming a drain electrode in a region adjacent to the second region, and depositing the gate includes the The first gap may be formed to be narrower than the second gap.
여기서, 상기 게이트는 T 형상으로 형성 될 수 있다.Here, the gate may be formed in a T shape.
또한, 상기 재성장 물질 및 상기 식각정지층은 P 성분을 포함하고, 상기 캡층은 As 성분을 포함할 수 있다. 구체적으로, 식각정지층은 P 성분을 포함하는 물질 중 캡층이 식각되는 동안 식각이 되지 않은 물질로 구현될 수 있다. 그리고, 캡층은 As 성분을 포함하는 물질 중 GaAs계 물질로 구현될 수 있다.In addition, the regrowth material and the etch stop layer may include a P component, and the cap layer may include an As component. Specifically, the etch stop layer may be formed of a material that is not etched while the cap layer is etched, among materials containing the P component. In addition, the cap layer may be implemented with a GaAs-based material among materials containing an As component.
상술한 본 개시의 다양한 실시 예에 따르면, 트랜지스터 제조방법은 재성장 물질의 식각선택비(Etch Selectivity)를 활용하여 식각과정을 제어함으로써, 게이트가 증착될 영역의 크기에 대한 안정성을 확보할 수 있다. 그리고, 트랜지스터 제조방법은 신뢰성과 재현성이 높은 트랜지스터를 제작할 수 있다.According to various embodiments of the present disclosure described above, in the method of manufacturing a transistor, by controlling an etching process using an etch selectivity of a regrowth material, stability with respect to the size of a region in which a gate is to be deposited may be secured. In addition, the transistor manufacturing method can manufacture a transistor with high reliability and reproducibility.
또한, 트랜지스터 제조방법은 비대칭적 구조를 통하여 기생성분을 최적화한 고성능, 고효율의 트랜지스터를 제작할 수 있다.In addition, the transistor manufacturing method can manufacture a high-performance, high-efficiency transistor that optimizes parasitic components through an asymmetric structure.
본 발명의 효과들은 이상에서 언급한 효과들로 제한되지 않으며, 언급되지 않은 또 다른 효과들은 아래의 기재로부터 통상의 기술자에게 명확하게 이해 될 수 있을 것이다.The effects of the present invention are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art from the following description.
도 1은 종래에 트랜지스터 제조시 사용되는 리세스 공정 단면도이다.1 is a cross-sectional view of a recess process used in conventional transistor manufacturing.
도 2a 내지 도 2g는 본 개시에 의한 트랜지스터 제조방법을 순차적으로 도시한 공정 단면도이다.2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a transistor according to the present disclosure.
도 3a 및 도 3b는 본 개시의 다른 실시 예에 따른 트랜지스터를 설명하는 도면이다.3A and 3B are diagrams illustrating a transistor according to another exemplary embodiment of the present disclosure.
도 4은 본 개시의 일 실시 예에 따른 트랜지스터 제조방법의 흐름도이다.4 is a flowchart of a method of manufacturing a transistor according to an exemplary embodiment of the present disclosure.
본 명세서에서 사용되는 용어에 대해 간략히 설명하고, 본 개시에 대해 구체적으로 설명하기로 한다.The terms used in the present specification will be briefly described, and the present disclosure will be described in detail.
제1, 제2 등과 같이 서수를 포함하는 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 이러한 구성요소들은 상술한 용어에 의해 한정되지는 않는다. 상술한 용어는 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용된다.Terms including ordinal numbers such as first and second may be used to describe various elements, but these elements are not limited by the above-described terms. The above-described terms are used only for the purpose of distinguishing one component from other components.
본 명세서에서, "포함한다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다. In the present specification, terms such as "comprises" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance.
본 발명의 설명에 있어서 각 단계의 순서는 선행 단계가 논리적 및 시간적으로 반드시 후행 단계에 앞서서 수행되어야 하는 경우가 아니라면 각 단계의 순서는 비제한적으로 이해되어야 한다. 즉, 위와 같은 예외적인 경우를 제외하고는 후행 단계로 설명된 과정이 선행단계로 설명된 과정보다 앞서서 수행되더라도 발명의 본질에는 영향이 없으며 권리범위 역시 단계의 순서에 관계없이 정의되어야 한다. In the description of the present invention, the order of each step should be understood without limitation, unless the preceding step must be performed logically and temporally prior to the subsequent step. That is, except for the above exceptional cases, even if a process described as a subsequent step is performed prior to a process described as a preceding step, the essence of the invention is not affected, and the scope of rights should be defined regardless of the order of the steps.
본 명세서에서는 본 발명의 설명에 필요한 필수적인 구성요소만을 설명하며, 본 발명의 본질과 관계가 없는 구성요소는 언급하지 아니한다. 그리고 언급되는 구성요소만을 포함하는 배타적인 의미로 해석되어서는 아니되며 다른 구성요소도 포함할 수 있는 비배타적인 의미로 해석되어야 한다.In this specification, only essential components necessary for the description of the present invention are described, and components not related to the essence of the present invention are not mentioned. In addition, it should not be interpreted as an exclusive meaning including only the mentioned components, but should be interpreted as a non-exclusive meaning that may also include other components.
또한, 이상에서는 본 발명의 바람직한 실시 예에 대하여 도시하고 설명하였지만, 본 발명은 상술한 특정의 실시 예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변형실시가 가능한 것은 물론이고, 이러한 변형실시들은 본 발명의 기술적 사상이나 전망으로부터 개별적으로 이해되어져서는 안될 것이다.In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention claimed in the claims. In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or prospect of the present invention.
이하에서는 첨부된 도면을 참조하여 다양한 실시 예를 보다 상세하게 설명한다. 본 명세서에 기재된 실시 예는 다양하게 변형될 수 있다. 특정한 실시 예가 도면에서 묘사되고 상세한 설명에서 자세하게 설명될 수 있다. 그러나, 첨부된 도면에 개시된 특정한 실시 예는 다양한 실시 예를 쉽게 이해하도록 하기 위한 것일 뿐이다. 따라서, 첨부된 도면에 개시된 특정 실시 예에 의해 기술적 사상이 제한되는 것은 아니며, 발명의 사상 및 기술 범위에 포함되는 모든 균등물 또는 대체물을 포함하는 것으로 이해되어야 한다.Hereinafter, various embodiments will be described in more detail with reference to the accompanying drawings. The embodiments described herein may be variously modified. Certain embodiments may be depicted in the drawings and described in detail in the detailed description. However, specific embodiments disclosed in the accompanying drawings are only intended to facilitate understanding of various embodiments. Therefore, the technical idea is not limited by the specific embodiments disclosed in the accompanying drawings, and it should be understood to include all equivalents or substitutes included in the spirit and scope of the invention.
이하에서 사용하는 "증착", "성장" 등의 용어는 반도체 물질 층을 형성한다는 의미와 같은 의미로 쓰이는 것이고, 본 발명의 다양한 실시 예들을 통해 형성되는 층 혹은 박막은 유기금속화학증착(Metal-Organic Chemical Vapor Deposition, MOCVD)법 또는 분자선 성장(Molecular Beam Epitaxy, MBE)법을 이용하여 성장용 챔버(chamber) 내에서 성장될 수 있으며, 이 밖에도 PECVD, APCVD, LPCVD, UHCVD, PVD, 전자빔 방식, 저항 가열방식 등 다양한 방식에 의해 증착되어 형성될 수 있다. 유기금속화학증착(MOCVD) 방식을 이용할 경우, MOCVD 반응 챔버의 용적에 따라, 그 안에 주입되는 기체의 유속을 결정할 수 있으며, 기체의 종류, 유속 반응 챔버 내부의 압력, 온도 조건 등에 따라 성장되는 박막의 두께, 표면 거칠기, 도펀트의 도핑된 농도 등의 특성이 달라질 수 있다. 특히, 고온일수록 박막의 우수한 결정성을 얻을 수 있는데, 이는 반응 기체의 물성, 반응이 일어나는 온도 등을 고려하여 제한적으로 결정 되어야 할 사항이다. 특히, 정밀한 성장을 위해선 ALD(Atomic Layer Deposition) 방식을 이용할 수 있다. ALD 방식에 의하면 박막 성장이 원자 단위로 제어될 수 있다. Terms such as "deposition" and "growth" used below have the same meaning as forming a layer of a semiconductor material, and a layer or thin film formed through various embodiments of the present invention may be formed by metal-organic chemical vapor deposition (Metal- Organic Chemical Vapor Deposition (MOCVD) method or molecular beam epitaxy (MBE) method can be used to grow in a growth chamber. In addition, PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method, It can be deposited and formed by various methods such as resistance heating method. When using the organometallic chemical vapor deposition (MOCVD) method, the flow rate of the gas injected into the MOCVD reaction chamber can be determined according to the volume of the MOCVD reaction chamber, and a thin film that is grown according to the type of gas, the pressure inside the flow rate reaction chamber, and temperature conditions. The properties such as the thickness, surface roughness, and doped concentration of the dopant may vary. In particular, the higher the temperature, the better the crystallinity of the thin film can be obtained, which should be limitedly determined in consideration of the physical properties of the reaction gas and the temperature at which the reaction occurs. In particular, for precise growth, an ALD (Atomic Layer Deposition) method can be used. According to the ALD method, the growth of the thin film can be controlled in atomic units.
도 2a 내지 도 2g는 본 개시에 의한 트랜지스터 제조방법을 순차적으로 도시한 공정 단면도이다.2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a transistor according to the present disclosure.
도 2a를 참조하면, 트랜지스터 제조방법의 일 실시 예에 따라 기판(210)이 마련된다. 기판(210) 상면에 버퍼층(221), 채널층(222), 배리어층(223), 식각정지층(224), 및 캡층(225)을 포함하는 에피택셜층(220)이 형성될 수 있고, 에피택셜층(220) 상면에 유전체층(230)이 형성될 수 있다. 유전체층(230) 상면에 제1 레지스트(resist)층(240)이 코팅(또는 도포)된 후, 노광공정(lithography)을 통해 제1 레지스트(resist) 패턴이 형성될 수 있다.Referring to FIG. 2A, a substrate 210 is provided according to an embodiment of a method of manufacturing a transistor. An epitaxial layer 220 including a buffer layer 221, a channel layer 222, a barrier layer 223, an etch stop layer 224, and a cap layer 225 may be formed on the upper surface of the substrate 210, A dielectric layer 230 may be formed on the epitaxial layer 220. After the first resist layer 240 is coated (or coated) on the upper surface of the dielectric layer 230, a first resist pattern may be formed through a lithography process.
예를 들어, 제1 레지스트(resist)는 포토 레지스트(photo resist) 또는 전자빔 레지스트(E-beam resist) 일 수 있다. 여기서, 레지스트(resist) 패턴 형성을 위한 노광공정(lithography)은 자외선(UV), 깊은 자외선(Deep UV), 극 자외선(Extreme UV), 전자빔(E-beam)을 이용한 노광공정(lithography) 일 수 있다. 기판(210)은 고전자이동도 트랜지스터(HEMT)를 제조하기 위하여 GaAs계 또는 InP계 물질일 수 있고, 반도체 물질의 단일 기판을 포함할 수 있다. For example, the first resist may be a photo resist or an E-beam resist. Here, the exposure process (lithography) for forming a resist pattern may be a lithography process using ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam). have. The substrate 210 may be a GaAs-based or InP-based material to manufacture a high-mobility transistor (HEMT), and may include a single substrate made of a semiconductor material.
도 2b 및 도 2c를 참조하면, 재성장 영역이 형성되는 공정이 도시되어 있다. 형성된 제1 레지스트(resist) 패턴을 기초로 유전체층(230)이 식각 되고, 제1 레지스트(resist) 패턴은 박리(resist strip)될 수 있다. 여기서, 유전체층(230)의 식각은 건식식각 또는 물리 화학적 반응식각 일 수 있고, 일례로 SiO 2 RIE(Reactive Ion Etching)일 수 있다. 그리고, 식각된 유전체층(230)은 캡층(225)의 식각공정에서 하드 마스크 역할을 수행할 수 있다. 식각된 유전체층(230)을 기초로 캡층(225)이 식각되어 재성장 영역(3a, 3b)이 형성될 수 있다. 여기서 재성장 영역(3a, 3b)은 이격되어 형성될 수 있다. 여기서, 식각정지층(224)은 P 성분을 포함하는 물질 중 캡층(225)이 식각되는 동안 식각이 되지 않은 물질로 구현될 수 있다. 그리고, 캡층(225)은 As 성분을 포함하는 물질 중 GaAs계 물질로 구현될 수 있다.2B and 2C, a process of forming a regrowth region is illustrated. The dielectric layer 230 may be etched based on the formed first resist pattern, and the first resist pattern may be peeled off (resist strip). Here, etching of the dielectric layer 230 may be dry etching or physicochemical reaction etching, for example, SiO 2 Reactive Ion Etching (RIE). In addition, the etched dielectric layer 230 may serve as a hard mask in an etching process of the cap layer 225. The cap layer 225 may be etched based on the etched dielectric layer 230 to form regrowth regions 3a and 3b. Here, the regrowth regions 3a and 3b may be formed to be spaced apart. Here, the etch stop layer 224 may be formed of a material that is not etched while the cap layer 225 is etched, among materials containing the P component. In addition, the cap layer 225 may be implemented with a GaAs-based material among materials containing an As component.
도 2d 및 도 2e를 참조하면, 재성장 물질의 재성장 공정이 도시되어 있다. 재성장 물질의 재성장 공정에서 재성장 영역(3a, 3b)은 하드 마스크 역할을 수행할 수 있다. 유전체층(230)을 기초로 캡층(225)이 식각되어 형성된 재성장 영역(3a, 3b)에 재성장 물질이 성장 될 수 있다. 예를 들어, 재성장 물질은 InP이 포함된 물질일 수 있고, 유기금속화학증착법(MOCVD)을 이용하여 선택적으로 성장 될 수 있다. 재성장 영역(3a, 3b)이 이격되어 형성되므로 재성장 물질도 제1 영역(3a)과 제2 영역(3b)에 이격되어 형성될 수 있다. 식각공정 이후 에피택셜층(220) 상에 잔존하는 물질(etchant)과 유전체층이 세정공정(cleaning)을 통해 제거 될 수 있다. 예를 들어, 잔존하는 물질(etchant)은 SiO 2 일 수 있고, 세정공정(cleaning)에는 BOE용액이 사용될 수 있다. 2D and 2E, a regrowth process of a regrowth material is illustrated. In the regrowth process of the regrowth material, the regrowth regions 3a and 3b may serve as a hard mask. A regrowth material may be grown in the regrowth regions 3a and 3b formed by etching the cap layer 225 based on the dielectric layer 230. For example, the regrowth material may be a material containing InP, and may be selectively grown using an organometallic chemical vapor deposition (MOCVD) method. Since the regrowth regions 3a and 3b are formed to be spaced apart from each other, the regrowth material may also be formed to be spaced apart from the first region 3a and the second region 3b. After the etching process, an etchant and a dielectric layer remaining on the epitaxial layer 220 may be removed through a cleaning process. For example, the remaining etchant may be SiO 2 , and a BOE solution may be used for cleaning.
도 2f를 참조하면, 남은 캡층(225)과 재성장 물질이 존재하는 재성장 영역(3a, 3b) 상부에 제2 레지스트(resist)층(250), PMGI층(260) 및 제3 레지스트(resist)층(270)이 코팅(또는 도포)될 수 있다. 예를 들어, 제2 및 제3 레지스트(resist)층(250, 270)은 포토 레지스트(photo resist) 또는 전자빔 레지스트(E-beam resist) 일 수 있다.Referring to FIG. 2F, a second resist layer 250, a PMGI layer 260, and a third resist layer over the regrowth regions 3a and 3b in which the remaining cap layer 225 and the regrowth material are present. 270 may be coated (or applied). For example, the second and third resist layers 250 and 270 may be photo resists or E-beam resists.
도 2f에 도시된 바와 같이, 제3 레지스트(resist)층(270)에 제3 레지스트(resist) 패턴을 형성하는 노광공정(lithography)이 수행된 후, PMGI층(260)을 식각하는 습식식각 공정이 수행될 수 있다. 그리고, PMGI층(260)의 식각을 통하여 노출된 제2 레지스트(resist)층(250)에 제2 레지스트(resist) 패턴을 형성하는 노광공정(lithography)이 수행될 수 있다. 예를들어, 노광공정(lithography)에는 자외선(UV), 깊은 자외선(Deep UV), 극 자외선(Extreme UV) 및 전자빔(E-beam)이 이용될 수 있다As shown in FIG. 2F, after a lithography process of forming a third resist pattern on the third resist layer 270 is performed, a wet etching process of etching the PMGI layer 260 This can be done. In addition, a lithography process of forming a second resist pattern on the second resist layer 250 exposed through etching of the PMGI layer 260 may be performed. For example, ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam) may be used for lithography.
그리고, 제2 레지스트(resist) 패턴을 기초로 제2 레지스트(resist)층(250), 식각정지층(224), 재성장 물질이 형성된 제1 영역(3a) 및 제2 영역(3b)으로 둘러싸인 캡층의 일 영역(1)이 습식식각 될 수 있다. 둘러싸인 캡층의 일 영역(1)의 폭은 재성장 물질이 형성된 제1 영역(3a) 및 제2 영역(3b)의 간격에 의하여 결정될 수 있다. 제1 영역(3a) 및 제2 영역(3b)의 간격은 상술한 공정 과정을 통해 설계 사양과 동일하게 형성될 수 있다. The cap layer surrounded by the second resist layer 250, the etch stop layer 224, the first region 3a and the second region 3b on which the regrowth material is formed based on the second resist pattern. One area (1) of may be wet etched. The width of one region 1 of the enclosed cap layer may be determined by the spacing between the first region 3a and the second region 3b in which the regrowth material is formed. The spacing between the first region 3a and the second region 3b may be formed to be the same as the design specification through the above-described process process.
그리고, 제1 영역(3a) 및 제2 영역(3b)에 형성된 재성장물질 및 식각정치층(224)은 식각정지 장벽의 역할을 수행할 수 있다. 따라서 둘러싸인 캡층의 일 영역(1)은 충분히 오랜 시간에 걸쳐서 습식식각 되더라도, 과도한 식각으로 인한 문제가 발생하지 않고 설계에 합치하는 영역만큼 식각될 수 있다. 따라서, 둘러싸인 캡층의 일 영역(1)의 크기는 정밀하게 제어 될 수 있다.In addition, the regrowth material and the etch stop layer 224 formed in the first region 3a and the second region 3b may serve as an etch stop barrier. Therefore, even if one region 1 of the enclosed cap layer is wet etched over a sufficiently long period of time, a problem due to excessive etching does not occur and as much as a region conforming to the design can be etched. Therefore, the size of the area 1 of the enclosed cap layer can be precisely controlled.
식각된 둘러싸인 캡층의 일 영역(1)에 게이트 금속이 증착될 수 있다. 이때, 게이트는 상부가 하부보다 넓은 T형 모양의 게이트 일 수 있다. 예를 들어, 게이트 금속은 Ti/Pt/Au를 포함한 게이트 전용 금속일 수 있다. A gate metal may be deposited on one region 1 of the etched enclosed cap layer. In this case, the gate may be a T-shaped gate whose upper portion is wider than that of the lower portion. For example, the gate metal may be a gate-only metal including Ti/Pt/Au.
도 2g를 참조하면, 본 개시의 일 실시 예에 따라 제조된 트랜지스터가 최종적으로 도시되어 있다. 게이트(280)를 형성하는 게이트 증착공정에서 도 2f의 제3 레지스트(resist)층(270) 및 제2 레지스트(resist)층(250) 상에 게이트 금속이 증착될 수 있다. 제2 및 제3 레지스트(resist)층(250, 270) 상에 증착된 게이트 금속, 제2 레지스트(resist)층(250), PMGI층(260) 및 제3 레지스트(resist)층(270)은 리프트-오프(lift-off) 공정을 이용하여 함께 제거될 수 있다. 일례로, 아세톤(aceton)을 제2 레지스트(resist)층(250)과 캡층(225) 사이에 침투시켜 제2 레지스트(resist)층(250), PMGI층(260), 제3 레지스트(resist)층(270) 및 제3 레지스트(resist)층(270) 상에 증착된 게이트 금속은 함께 제거될 수 있다. 그 결과 도 2g에 도시한 바와 같이 T형상의 게이트 전극(280)이 형성될 수 있다.Referring to FIG. 2G, a transistor manufactured according to an embodiment of the present disclosure is finally shown. In the gate deposition process of forming the gate 280, a gate metal may be deposited on the third resist layer 270 and the second resist layer 250 of FIG. 2F. The gate metal, the second resist layer 250, the PMGI layer 260, and the third resist layer 270 deposited on the second and third resist layers 250 and 270 are They can be removed together using a lift-off process. For example, acetone is penetrated between the second resist layer 250 and the cap layer 225 to form a second resist layer 250, a PMGI layer 260, and a third resist. The gate metal deposited on the layer 270 and the third resist layer 270 may be removed together. As a result, as shown in FIG. 2G, the T-shaped gate electrode 280 may be formed.
상기 도 2g에는 T형상의 게이트 전극을 도시하고 있는데, 이에 한정하지 않는다. 예를들어, 게이트의 형상은 Fin 타입일 수 있고, 상부가 하부보다 넓은 형상(Γ형), 상부와 하부의 게이트 폭이 동일한 일자형, 하부가 상부보다 넓은 빗살형상, 단면이 십(十)자 형상 등 게이트의 형상은 다양한 모양으로 형성 될 수 있다. 게이트의 형상에 따라 노광공정 및 식각공정의 일부순서가 변경 될 수 있고 공정의 일부가 추가 될 수 있다.The T-shaped gate electrode is shown in FIG. 2G, but is not limited thereto. For example, the shape of the gate may be a Fin type, the upper part is wider than the lower part (Γ type), the upper and lower gate widths are the same, the lower part is wider than the upper part, and the cross section is ten. The shape of the gate, such as the shape, can be formed in various shapes. Depending on the shape of the gate, the order of the exposure process and the etching process may be changed, and a part of the process may be added.
도 3a 및 도 3b는 본 개시의 다른 실시 예에 따른 트랜지스터를 설명하는 도면이다. 재성장 물질이 형성된 제1 영역(3a)과 게이트(280) 간의 간격을 제1 간격(A)이라고 정의하고, 재성장 물질이 형성된 제2 영역(3b)와 게이트(280) 간의 간격을 제2 간격(B)이라고 정의한다. 본 개시의 트랜지스터 제조 방법은 도 2g에 도시된 바와 같이, 제1 간격(A)과 제2 간격(B)을 대칭으로 형성할 수 있다. 또한, 본 개시의 트랜지스터 제조 방법은 별도 공정 추가 없이 제1 간격(A)과 제2 간격(B)을 비대칭으로 형성할 수도 있다.3A and 3B are diagrams illustrating a transistor according to another exemplary embodiment of the present disclosure. The interval between the first region 3a where the regrowth material is formed and the gate 280 is defined as a first interval (A), and the interval between the second region 3b where the regrowth material is formed and the gate 280 is a second interval ( B) is defined. In the method of manufacturing the transistor of the present disclosure, as illustrated in FIG. 2G, the first interval A and the second interval B may be formed symmetrically. In addition, in the method of manufacturing a transistor of the present disclosure, the first interval A and the second interval B may be formed asymmetrically without adding a separate process.
도 3a를 참조하면, 비대칭적 게이트 구조를 가지는 트랜지스터 제조공정도 도 2a 내지 도 2g에서 상술한 제조 공정과 동일공정으로 수행될 수 있다. 도2a 내지 도 2e까지 동일한 공정의 설명을 생략하고 비대칭적 게이트 구조를 생성하기 위한 공정의 차이를 중심으로 설명하면, 도 2e에서 이격되어 형성된 제1 영역(3a) 및 제2 영역(3b)과 남은 캡층(225)의 상부에 제2 레지스트(resist)층(250), PMGI층(260) 및 제3 레지스트(resist)층(270)이 코팅(또는 도포)될 수 있다. 그리고, 제2 레지스트(resist)층(250) 및 제3 레지스트(resist)층(270)에는 노광공정(lithography)이 수행되고, PMGI층(260)에는 습식식각 공정이 수행될 수 있다. 다만, 비대칭적 게이트 구조를 가지는 트랜지스터를 제조하기 위하여 제2 레지스트(resist)층(250) 및 제3 레지스트(resist)층(270) 상에 수행되는 노광공정(lithography)이 제1 영역(3a) 또는 제2 영역(3b) 중 하나의 영역에 근접하여 수행될 수 있다. 이후, 기존의 대칭적 구조를 가지는 트랜지스터 제조 방법과 동일한 식각 공정, 게이트 증착공정 및 리프트-오프(lift-off)공정이 수행되면 도 3a에서 도시한 바와 같이 비대칭적 게이트 구조를 가지는 트랜지스터가 제조될 수 있다.Referring to FIG. 3A, a process for manufacturing a transistor having an asymmetric gate structure may also be performed in the same process as the manufacturing process described above in FIGS. 2A to 2G. 2A to 2E, the description of the same process will be omitted, and the difference in the process for generating the asymmetric gate structure will be mainly described. The first region 3a and the second region 3b formed spaced apart in FIG. 2E A second resist layer 250, a PMGI layer 260, and a third resist layer 270 may be coated (or applied) on the remaining cap layer 225. In addition, a lithography process may be performed on the second resist layer 250 and the third resist layer 270, and a wet etching process may be performed on the PMGI layer 260. However, in order to manufacture a transistor having an asymmetric gate structure, a lithography process performed on the second resist layer 250 and the third resist layer 270 is performed in the first region 3a. Alternatively, it may be performed close to one of the second regions 3b. Thereafter, when the same etching process, gate deposition process, and lift-off process as in the conventional method of manufacturing a transistor having a symmetric structure are performed, a transistor having an asymmetric gate structure will be manufactured as shown in FIG. 3A. I can.
여기서, 게이트 전극(280)이 제1 영역(3a)에 근접하여 형성된 후, 제1 영역(3a)에 인접한 캡층(225)에 소스 전극(미도시)이, 제2 영역(3b)에 인접한 캡층(225)에 드레인 전극(미도시)이 형성 될 수 있다.Here, after the gate electrode 280 is formed close to the first region 3a, a source electrode (not shown) is formed on the cap layer 225 adjacent to the first region 3a, and a cap layer adjacent to the second region 3b A drain electrode (not shown) may be formed at 225.
도 3b를 참조하면, 도 3b는 소스 전극이 제1 영역(3a)과 인접한 영역에, 드레인 전극이 제2 영역(3b)과 인접한 영역에 형성된 경우를 도시한다. Referring to FIG. 3B, FIG. 3B shows a case where a source electrode is formed in a region adjacent to the first region 3a and a drain electrode is formed in a region adjacent to the second region 3b.
여기서, 제1 영역(3a)과 게이트(280) 간의 제1 간격(A)이 제2 영역(3b)과 게이트(280)의 제2 간격(B)보다 작게 형성 될 수 있다. 게이트(280)와 제1 영역(3a) 간의 제1 간격(A)은 소스 저항으로 작용하게 되므로 제1 간격이 작은 경우, 트랜지스터의 전류밀도 및 트랜스컨덕턴스가 증가하게 되므로 트랜지스터의 성능이 향상된다. 또한, 게이트(280)와 제2 영역(3b) 간의 제2 간격(B)은 드레인 저항으로 작용하게 되므로, 적당히 크게 설정될 경우 트랜지스터의 출력 컨덕턴스가 감소하여 최대 발진 주파수가 증가하고, 드레인과 게이트 간의 파괴전압(Breakdown Voltage, BV DG)이 증가하게 되어 열화 특성이 개선될 수 있다.Here, the first gap A between the first region 3a and the gate 280 may be formed smaller than the second gap B between the second region 3b and the gate 280. Since the first gap A between the gate 280 and the first region 3a acts as a source resistance, when the first gap is small, the current density and transconductance of the transistor increase, thereby improving the performance of the transistor. In addition, since the second gap B between the gate 280 and the second region 3b acts as a drain resistance, if it is set to be appropriately large, the output conductance of the transistor decreases and the maximum oscillation frequency increases, and the drain and gate The breakdown voltage (BV DG ) of the liver increases, so that deterioration characteristics may be improved.
본 개시의 다른 실시예에 따른 트랜지스터 제조방법은 제2 레지스트(resist)층(250)의 노광공정(lithography)이 제1 영역(3a) 또는 제2 영역(3b) 중 한 영역에 근접하여 수행되는 것 만으로 비대칭 게이트 구조를 가지는 트랜지스터가 형성 될 수 있다.In the method of manufacturing a transistor according to another embodiment of the present disclosure, a lithography process of the second resist layer 250 is performed in proximity to one of the first region 3a or the second region 3b. With just that, a transistor with an asymmetric gate structure can be formed.
따라서, 비대칭적 게이트 구조의 트랜지스트를 제조하기 위한 공정이 추가로 요구되지 않고, 추가 공정에 따른 시간적, 경제적 손실이 발생하지 않을 수 있다.Therefore, an additional process for manufacturing a transistor having an asymmetric gate structure is not required, and time and economic loss may not occur due to the additional process.
도 4는 본 개시의 일 실시 예에 따른 트랜지스터 제조방법의 흐름도이다.4 is a flowchart of a method of manufacturing a transistor according to an embodiment of the present disclosure.
도 4을 참조하면, 본 개시의 일 실시예에 따른 트랜지스터 제조공정은 기판(210) 상에 버퍼층(221), 채널층(222), 배리어층(223), 식각정지층(224), 캡층(225)을 포함하는 에피택셜층(220) 및 유전체층(230)을 형성한다(S110). 그리고, 트랜지스터 제조공정은 유전체층(230) 상에 제1 레지스트(resist)층을 형성하고, 제1 레지스트(resist)층(240)에 제1 레지스트(resist) 패턴을 형성한다(S120).Referring to FIG. 4, in a transistor manufacturing process according to an embodiment of the present disclosure, a buffer layer 221, a channel layer 222, a barrier layer 223, an etch stop layer 224, and a cap layer ( The epitaxial layer 220 and the dielectric layer 230 including 225 are formed (S110). In the transistor manufacturing process, a first resist layer is formed on the dielectric layer 230 and a first resist pattern is formed on the first resist layer 240 (S120).
예를 들어, 제1 레지스트(resist)(240)는 포토 레지스트(photo resist) 또는 전자빔 레지스트(E-beam resist) 일 수 있다. 여기서, 레지스트(resist) 패턴 형성을 위한 노광공정(lithography)은 자외선(UV), 깊은 자외선(Deep UV), 극 자외선(Extreme UV), 전자빔(E-beam)을 이용한 노광공정(lithography) 일 수 있다. 기판(210)은 고 전자이동도 트랜지스터(HEMT)를 제조하기 위하여 GaAs계 또는 InP계 물질일 수 있고, 반도체 물질의 단일 기판을 포함할 수 있다. For example, the first resist 240 may be a photo resist or an E-beam resist. Here, the exposure process (lithography) for forming a resist pattern may be a lithography process using ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam). have. The substrate 210 may be a GaAs-based or InP-based material to manufacture a high electron mobility transistor (HEMT), and may include a single substrate made of a semiconductor material.
트랜지스터 제조공정은 형성된 제1 레지스트(resist) 패턴을 기초로 유전체층(230)이 식각되고, 제1 레지스트(resist) 패턴은 박리(resist strip)된다(S130). 여기서, 유전체층(230)의 식각은 건식식각 또는 물리 화학적 반응식각 일 수 있고, 일례로 SiO 2 RIE(Reactive Ion Etching)일 수 있다.In the transistor manufacturing process, the dielectric layer 230 is etched based on the formed first resist pattern, and the first resist pattern is resist stripped (S130). Here, etching of the dielectric layer 230 may be dry etching or physicochemical reaction etching, for example, SiO 2 Reactive Ion Etching (RIE).
그리고, 트랜지스터 제조공정은 하드 마스크 역할을 수행하는 식각된 유전체층(230)을 기초로 캡층(225)을 식각한다. 트랜지스터 제조공정은 캡층(225)이 식각되어 생성된 재성장 영역(3a, 3b)에 재성장 물질을 성장시킨다(S140). 일례로, 재성장 물질은 InP이 포함된 물질일 수 있고, 유기금속화학증착법(MOCVD)을 이용하여 선택적으로 성장 될 수 있다. 또한 재성장 영역(3a, 3b)이 이격되어 형성되므로 재성장 물질도 제1 영역(3a)과 제2 영역(3b)에 이격되어 형성될 수 있다.In the transistor manufacturing process, the cap layer 225 is etched based on the etched dielectric layer 230 serving as a hard mask. In the transistor manufacturing process, a regrowth material is grown in the regrowth regions 3a and 3b generated by etching the cap layer 225 (S140). As an example, the regrowth material may be a material containing InP, and may be selectively grown using an organometallic chemical vapor deposition (MOCVD) method. Also, since the regrowth regions 3a and 3b are formed to be spaced apart from each other, the regrowth material may be formed to be spaced apart from the first region 3a and the second region 3b.
그리고, 트랜지스터 제조공정은 재성장 물질이 존재하는 캡층(225) 상부에 제2 레지스트(resist)층(250), PMGI층(260) 및 제3 레지스트(resist)층(270)을 코팅(또는 도포)한다. 예를 들어, 제2 레지스트(resist)층(250) 및 제3 레지스트(resist)층(270)은 포토 레지스트(photo resist) 또는 전자빔 레지스트(E-beam resist) 일 수 있다. In addition, in the transistor manufacturing process, a second resist layer 250, a PMGI layer 260, and a third resist layer 270 are coated (or applied) on the cap layer 225 in which the regrowth material is present. do. For example, the second resist layer 250 and the third resist layer 270 may be a photo resist or an E-beam resist.
트랜지스터 제조공정은 노광공정(lithography)을 이용하여 제3 레지스트(resist)층(270)에 제3 레지스트(resist) 패턴을 형성한 후, PMGI층(260)에 습식식각 공정을 수행한다. 그리고, 트랜지스터 제조공정은 PMGI층(260)이 식각되어 노출된 제2 레지스트(resist)층(250)을 노광공정(E-beam lithography)을 이용하여 제2 레지스트(resist) 패턴을 형성한다(S150). 여기서, 레지스트(resist) 패턴 형성을 위한 노광공정(lithography)은 자외선(UV), 깊은 자외선(Deep UV), 극 자외선(Extreme UV), 전자빔(E-beam)을 이용한 노광공정(lithography) 일 수 있다.In the transistor manufacturing process, after forming a third resist pattern on the third resist layer 270 by using a lithography process, a wet etching process is performed on the PMGI layer 260. In the transistor manufacturing process, the second resist layer 250 exposed by etching the PMGI layer 260 is subjected to an exposure process (E-beam lithography) to form a second resist pattern (S150). ). Here, the exposure process (lithography) for forming a resist pattern may be a lithography process using ultraviolet (UV), deep ultraviolet (Deep UV), extreme ultraviolet (Extreme UV), and electron beam (E-beam). have.
그리고, 트랜지스터 제조공정은 제2 레지스트(resist) 패턴을 기초로 제2 레지스트(resist)층(250), 식각정지층(224), 제1 영역(3a) 및 제2 영역(3b)으로 둘러싸인 캡층의 일 영역(1)을 습식식각 한다(S160). In the transistor manufacturing process, the cap layer surrounded by the second resist layer 250, the etch stop layer 224, the first region 3a, and the second region 3b based on the second resist pattern. One area (1) of is wet-etched (S160).
제1 영역(3a) 및 제2 영역(3b)에 존재하는 재성장물질은 식각정지 장벽의 역할을 수행할 수 있고, 둘러싸인 캡층의 일 영역(1)의 크기는 재성장물질이 존재하는 제1 영역(3a) 및 제2 영역(3b)에 의하여 결정된다. 따라서 충분히 오랜 시간에 걸쳐서 습식식각 되더라도, 과도한 식각으로 인한 문제가 발생하지 않고 설계에 합치하는 영역만큼 식각될 수 있다. 따라서, 둘러싸인 캡층의 일 영역(1)의 크기는 정밀하게 제어 될 수 있다. The regrowth material present in the first region 3a and the second region 3b may serve as an etch stop barrier, and the size of one region 1 of the enclosed cap layer is the first region ( It is determined by 3a) and the second region 3b. Therefore, even if wet etching is performed over a sufficiently long period of time, a problem due to excessive etching does not occur and as much as an area conforming to the design can be etched. Therefore, the size of the area 1 of the enclosed cap layer can be precisely controlled.
그리고, 식각된 둘러싸인 캡층의 일 영역(1)에 게이트 금속이 증착된다(S170). Then, a gate metal is deposited on one region 1 of the etched enclosed cap layer (S170).
본 개시의 일 실시 예에 따른 트랜지스터 제조 방법은 HEMT 소자, 미세 선폭 배선 구현 등에 적용될 수 있고, MESFET 등의 소자와 같이 미세하면서도 큰 단면적을 갖는 게이트가 요구되는 소자, 그리고 정밀한 리세스 식각 공정이 사용되는 소자의 제작에 이용할 수 있음은 물론이다.The method of manufacturing a transistor according to an embodiment of the present disclosure may be applied to a HEMT device, a fine line width wiring, etc., and a device requiring a gate having a fine and large cross-sectional area, such as a device such as MESFET, and a precise recess etching process are used. Needless to say, it can be used for the manufacture of devices that can be used.

Claims (7)

  1. 트랜지스터의 제조방법에 있어서,In the method of manufacturing a transistor,
    기판 상에 식각정지층, 캡층을 포함하는 에피택셜층 및 유전체층을 형성하는 단계;Forming an etch stop layer, an epitaxial layer including a cap layer, and a dielectric layer on a substrate;
    상기 유전체층 상에 제1 레지스트(resist)층을 형성하고, 상기 제1 레지스트(resist)층에 제1 레지스트(resist) 패턴을 형성하는 단계;Forming a first resist layer on the dielectric layer, and forming a first resist pattern on the first resist layer;
    상기 제1 레지스트(resist) 패턴에 기초하여 상기 유전체층을 식각하고, 상기 제1 레지스트(resist) 패턴을 박리(resist strip) 하는 단계; Etching the dielectric layer based on the first resist pattern and stripping the first resist pattern;
    상기 식각된 유전체층에 기초하여 상기 캡층을 식각함으로써 재성장 영역을 형성하고, 상기 형성된 재성장 영역에 재성장 물질을 성장시키는 단계;Forming a regrowth region by etching the cap layer based on the etched dielectric layer, and growing a regrowth material in the formed regrowth region;
    상기 재성장 물질이 존재하는 상기 캡층 상에 제2 레지스트(resist)층을 형성하고, 제2 레지스트(resist) 패턴을 형성하는 단계;Forming a second resist layer on the cap layer in which the regrowth material is present, and forming a second resist pattern;
    상기 형성된 제2 레지스트(resist) 패턴에 기초하여 상기 캡층의 일 영역을 식각하는 단계; 및Etching a region of the cap layer based on the formed second resist pattern; And
    상기 식각된 캡층의 일 영역에 게이트를 증착하는 단계;를 포함하는 트랜지스터 제조방법. And depositing a gate on a region of the etched cap layer.
  2. 제1항에 있어서,The method of claim 1,
    상기 캡층의 일 영역을 식각하는 단계는,Etching a region of the cap layer,
    식각정지 장벽의 역할을 수행하는 상기 재성장 물질 및 상기 식각정지층에 기초하여 상기 재성장 물질 및 상기 식각정지층으로 둘러싸인 영역을 식각하는, 트랜지스터 제조방법.A method of manufacturing a transistor, wherein a region surrounded by the regrowth material and the etch stop layer is etched based on the regrowth material and the etch stop layer serving as an etch stop barrier.
  3. 제1항에 있어서,The method of claim 1,
    상기 재성장 영역을 형성하는 단계는,The step of forming the regrowth region,
    제1 영역과 제2 영역이 이격되어 형성되고,The first region and the second region are formed to be spaced apart,
    상기 재성장 물질을 형성하는 단계는,The step of forming the regrowth material,
    상기 제1 영역 및 상기 제2 영역에 상기 재성장 물질을 성장시키는, 트랜지스터 제조방법.The method of manufacturing a transistor, wherein the regrowth material is grown in the first region and the second region.
  4. 제1항에 있어서,The method of claim 1,
    상기 게이트를 증착하는 단계는,The step of depositing the gate,
    제1 간격과 제2 간격을 비대칭으로 형성하며,Forming the first gap and the second gap asymmetrically,
    상기 제1 간격은 상기 재성장 물질이 성장된 제1 영역과 상기 형성된 게이트 간의 간격이고, 상기 제2 간격은 상기 재성장 물질이 성장된 제2 영역과 상기 형성된 게이트 간의 간격인, 트랜지스터 제조방법.The first gap is a gap between a first region in which the regrowth material is grown and the formed gate, and the second gap is a gap between a second region in which the regrowth material is grown and the formed gate.
  5. 제4항에 있어서,The method of claim 4,
    상기 제1 영역과 인접한 영역에 소스 전극을 형성하는 단계; 및Forming a source electrode in a region adjacent to the first region; And
    상기 제2 영역과 인접한 영역에 드레인 전극을 형성하는 단계;를 더 포함하고,Forming a drain electrode in a region adjacent to the second region; further comprising,
    상기 게이트를 증착하는 단계는,The step of depositing the gate,
    상기 제1 간격이 상기 제2 간격보다 좁게 형성되는, 트랜지스터 제조방법.The method of manufacturing a transistor, wherein the first gap is formed to be narrower than the second gap.
  6. 제1항에 있어서,The method of claim 1,
    상기 게이트는,The gate,
    T 형상으로 형성되는, 트랜지스터 제조방법.Formed in a T shape, a method of manufacturing a transistor.
  7. 제1항에 있어서,The method of claim 1,
    상기 재성장 물질 및 상기 식각정지층은,The regrowth material and the etch stop layer,
    P 성분을 포함하고,Contains the P component,
    상기 캡층은The cap layer
    As 성분을 포함하는, 트랜지스터 제조방법.Containing an As component, a method of manufacturing a transistor.
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