KR100259068B1 - Method for manufacturing mosfet of soi structure - Google Patents

Abstract

PURPOSE: A fabrication method of MOSFET having an SOI(silicon on insulator) is provided to simplify the manufacturing process and to stabilize a threshold voltage by forming a second epi-silicon layer having higher height compared to a second insulating layer using double epitaxial growing. CONSTITUTION: After sequentially forming a first insulating layer(2) and a first epi-silicon layer(3) on a semiconductor substrate(1), an active region is defined by selectively etching the first epi-silicon layer(3). After forming a second insulating layer(4) on the resultant structure, a hole is formed by selectively etching the second insulating layer(4) to expose a gate region. A second epi-silicon layer(5) is then grown by using the surface of the exposed active region as a seed, in which the height of the second epi-silicon layer(5) is higher than that of the second insulating layer(4). Then, a third insulating layer(6) and a gate(7) are sequentially formed.

Description

SOI structure MOSFET

1A to 1F are cross-sectional views of a conventional SOI structure MOSFET process

2 (a) to 2 (f) are cross-sectional views of the SOI structure MOSFET process of the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 first insulating film

3: first episilicon layer 4: second insulating film

5: second episilicon layer 6: third insulating film

7: gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon on insulator (MOSI) structure MOSFET, and more particularly, to a method for manufacturing an SOI structure MOSFET having a large depletion region suitable for threshold stabilization.

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a conventional SOI structure MOSFET, and the process will be described as follows.

First, as shown in (a), a first insulating film 2 is formed on the semiconductor substrate 1, and a first epi-silicon 3 is used as the active layer on the first insulating film 2 as a laser single crystal deposition method. And molecular beam deposition.

Then, the second episilicon 5 is formed locally using the first episilicon 3 exposed as a seed as shown in (c), and then the episilicon 3, 5 as shown in (d). ) Is etched back with a mask to remove the second insulating film 4.

Next, after depositing the third insulating film 6 for gate insulation and the polysilicon for gate on the exposed entire surface, the gate 7 is patterned by removing the remaining portions except the gate region of the polysilicon, and the first epitaxial layer is removed. Impurity ions are implanted into the source / drain regions of silicon 3.

Next, as shown in (e), the third insulating film 6 and the gate 7 on the active region are masked, and the third insulating film 6 of the remaining portion is removed, and then the fourth insulating film 8 is deposited on the entire surface. By etching back, the third insulating film 6 remaining on the source / drain side is removed.

In a conventional SOI structure MOSFET having such a structure, the same semiconductor layer is formed between the drain / source terminals (channels) when a gate voltage or more is applied to the gate.

Therefore, if there is a voltage difference between the source and the drain, a current flows and the MOSFET operates.

However, such a conventional technique has a problem of stabilization of channel formation due to a complicated process to form a high gate stage in manufacturing a MOSFET and a large step in forming a gate, and formation of a metal or an insulating film in a subsequent process. Due to the step difference due to the gate part formed at high time, there is a problem of cracking in forming a subsequent deposition layer and a depth of focus (DOF) in a photo-etching process.

The present invention has been made to solve the problems of the prior art as described above, the second episilicon layer is formed so as to cover the upper side of the second insulating film to form a gate and source / drain at the same height as a general MOSFET There is this.

DETAILED DESCRIPTION Embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

2 shows a manufacturing process diagram of an SOI structure MOSFET for explaining the present invention.

As shown in (a), the first insulating film 2 is formed on the semiconductor substrate 1 to a thickness of about 6000-10000 Å, and as shown in (b), a molecular vapor deposition method or a laser single crystal deposition method is provided on the upper side of the first insulating film 2. After the first epi-silicon (EPI-SILIWN) (3) for forming the active region to form a thickness of 200-300Å and the epi-silicon (3) by a photo-etching process to form a pattern to leave the active layer region of the transistor and forming a second insulating film 4 on the exposed entire surface as shown in (c) to a thickness of 10000 Å, and then forming the second insulating film 4 by photo-etching process as shown in (d). A pattern is formed so that the gate region of (3) is exposed, and the exposed first episilicon 3 is seeded as shown in (e), and the second epi is formed at a temperature range of 1000-1200 Pa on the upper side thereof. The silicon layer 5 is formed at about 1500 kPa higher than the upper surface of the second insulating film 4.

Next, as shown in (f), impurity ions for controlling the threshold voltage are implanted into the gate region of the second episilicon layer 5, and the third insulating film 6 for gate insulation is formed on the entire surface to a thickness of about 100 GPa. Thereafter, polysilicon is formed thereon as the first conductor.

Subsequently, the gate 7 is formed by removing only the remaining regions of the polysilicon and the third insulating layer 6 and removing the remaining portions to form a source / drain.

In addition, another embodiment of the above technology can be applied by a method of greatly improving the refresh characteristics by forming a capacitor in the episilicon layer in the insulator to remove the leakage current.

The technique of the present invention as described above by performing the same epi-silicon growth process twice to form a gate region of the MOSFET to ensure a sufficient depletion region (channel) to have a stable threshold voltage, Unlike the conventional SOI structure MOSFET, there is almost no step, so there is no disadvantage in the subsequent process, and the gate region is formed at the same height as the source / drain regions, thereby forming channel. It is close to the general MOSFET and reduces the number of process steps, which improves process time and device reliability.

Claims (3)

Forming an active region 3 by sequentially forming a first insulating film 2 and a first episilicon layer on the semiconductor substrate 1, and removing unnecessary portions of the first episilicon layer; an exposed entire surface Forming a hole by forming a second insulating film 4 in the second insulating film 4 and selectively removing an upper portion of the active region 3 in the second insulating film 4, Forming a second episilicon layer 5 higher than the second insulating film 4 by using the exposed surface of the active region 3 as a seed, And forming a third insulating film (6) and a gate (7) in the upper portion of the hole in the surface of the second episilicon layer (5). The method of claim 1, wherein a thickness from the surface of the second insulating film (4) is increased to about 1500 kPa when forming the second episilicon (5). The method of claim 1, wherein the thickness of the first episilicon layer (3) for forming the active region is 200-300 GPa.