KR970011502B1 - Thin film transistor manufacturing method - Google Patents
Thin film transistor manufacturing method Download PDFInfo
- Publication number
- KR970011502B1 KR970011502B1 KR1019930019651A KR930019651A KR970011502B1 KR 970011502 B1 KR970011502 B1 KR 970011502B1 KR 1019930019651 A KR1019930019651 A KR 1019930019651A KR 930019651 A KR930019651 A KR 930019651A KR 970011502 B1 KR970011502 B1 KR 970011502B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- thin film
- manufacturing
- film transistor
- forming
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 239000001301 oxygen Substances 0.000 claims abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 93
- 238000000034 method Methods 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000012495 reaction gas Substances 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 17
- 239000007789 gas Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- -1 oxygen ions Chemical class 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 150000003377 silicon compounds Chemical group 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Plasma & Fusion (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
제1도는 종래의 다결정실리콘 박막트랜지스터의 단면구조도.1 is a cross-sectional view of a conventional polysilicon thin film transistor.
제2도는 종래의 다결정실리콘 박막트랜지스터의 제조 공정순서도.2 is a manufacturing process flowchart of a conventional polysilicon thin film transistor.
제3도는 본 발명의 일실시예에 따른 다결정실리콘 박막트랜지스터의 제조 공정순서도.Figure 3 is a flow chart of the manufacturing process of a polysilicon thin film transistor according to an embodiment of the present invention.
제4도는 본 발명의 다른 실시예를 도시한 도면.4 shows another embodiment of the present invention.
제5도는 본 발명의 도 다른 실시예를 도시한 도면.5 illustrates another embodiment of the present invention.
제6도 및 제7도는 본 발명의 효과를 설명하기 위한 도면.6 and 7 are views for explaining the effect of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판2 : 초기산화막1 substrate 2 initial oxide film
3 : 다결정실리콘4,5 : 소오스/드레인3: polycrystalline silicon 4,5 source / drain
7 : 게이트8 : 층간절연막7: gate 8: interlayer insulating film
9 : 소오스/드레인전극10 : ECR산소 플라즈마에 의한 산화막9 source / drain electrode 10 oxide film by ECR oxygen plasma
11 : CVD산화막12 : 절화막11: CVD oxide film 12: cut film
13 : ECR산소 플라즈마에 의한 산화막13: oxide film by ECR oxygen plasma
본 발명은 액정표시장치(Liquid Crystal Display)에 이용되는 다결정실리콘 박막트랜지스터(Thin Film Transistor : 이하 TFT라 한다.)의 제조방법에 관한 것으로, 특히 저온 공정이 가능하며 다결정실리콘의 전자 이동도를 높일 수 있는 다결정실리콘 TFT의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polysilicon thin film transistor (hereinafter referred to as a TFT) used in a liquid crystal display. In particular, a low temperature process is possible and the electron mobility of a polysilicon is increased. It relates to a method for producing a polysilicon TFT that can be.
다결정실리콘 TFT는 제1도에 도시된 바와 같이 활성영역(3)을 다결정실리콘을 이용하여 형성하는 것으로 소오스/드레인(4,5)을 게이트(7)에 셀프 얼라인(Self-align) 되게 형성할 수 있다는 장점이 있으며, 무엇보다도 다결정실리콘의 전자이동도가 크기 때문에 액정표시장치의 구동회로로 다결정실리콘 TFT를 이용할 경우 구동회로를 화소와 같이 기판에 내장시킬 수 있는 커다란 장점이 있다(제1도에서 미설명부호 1은 기판, 2는 초기산화막, 6은 게이트절연막, 8은 층간절연막, 9는 A1 소오스/드레인전극을 각각 나타낸다.)The polysilicon TFT is formed by forming the active region 3 using polysilicon as shown in FIG. 1 so that the source / drain 4 and 5 are self-aligned to the gate 7. In particular, since the poly-silicon has high electron mobility, the polysilicon TFT is used as the driving circuit of the liquid crystal display device, so that the driving circuit can be embedded in the substrate like a pixel. In the drawing, reference numeral 1 denotes a substrate, 2 an initial oxide film, 6 a gate insulating film, 8 an interlayer insulating film, and 9 an A1 source / drain electrode.)
제2도를 참조하여 종래의 다결정실리콘 TFT의 제조방법을 설명하면 다음과 같다.Referring to FIG. 2, the manufacturing method of the conventional polysilicon TFT is as follows.
먼저, 제2도(a)에 도시된 바와 같이 기판(1)상에 초기산화막(2)을 형성하고 이어서 다결정실리콘(3)을 증착한후 소정 패턴으로 패터닝한다.First, as shown in FIG. 2A, an initial oxide film 2 is formed on a substrate 1, and then polycrystalline silicon 3 is deposited and patterned in a predetermined pattern.
이어서 제2도(b)에 도시된 바와 같이 게이트절연막(6)으로서 상기 다결정실리콘(3)을 열산화시켜 1000Å정도 두께의 열산화막으로 형성한다.Subsequently, as shown in FIG. 2 (b), the polysilicon 3 is thermally oxidized as the gate insulating film 6 to form a thermal oxide film having a thickness of about 1000 kPa.
이때, 게이트절연막으로 열산화막대신 CVD(Chemical Vapor Deposition)산화막을 형성하기로 하며, 또한 열산화막과 CVD산화막으로 이루어진 이중산화막을 형성하기도 한다.In this case, a CVD (Chemical Vapor Deposition) oxide film is formed instead of the thermal oxide film as the gate insulating film, and a double oxide film composed of the thermal oxide film and the CVD oxide film is also formed.
다음에 제2도(c)에 도시된 바와 같이 다결정실리콘을 2000Å∼4000Å 두께로 CVD방법에 의해 증착한 후, 상기 게이트 산화막(6)과 함께 게이트 패턴으로 패터닝하여 게이트(7)를 형성한 다음, 소오스/드레인 형성을 위한 이온 주입공정을 행한다.Next, as shown in FIG. 2 (c), polysilicon is deposited by a CVD method to a thickness of 2000 GPa to 4000 GPa, and then patterned together with the gate oxide film 6 in a gate pattern to form a gate 7. Then, an ion implantation step for source / drain formation is performed.
이어서 제2도(d)에 도시된 바와 같이 상기 결과물 전면에 층간절연막(8)으로서 CVD산화막을 2000Å∼4000Å두께로 증착한다.Subsequently, as shown in FIG. 2 (d), a CVD oxide film is deposited to a thickness of 2000 kV to 4000 kPa as the interlayer insulating film 8 on the entire surface of the resultant product.
이때 상기 주입된 이온이 활성화되어 소오스/드레인(4,5)이 형성되게 된다.At this time, the implanted ions are activated to form the source / drain (4, 5).
이어서 소오스/드레인(4,5)의 소정 부분을 노출시키는 콘택개구부를 상기 층간절연막(8)에 형성한후, 결과물상에 A1을 증착하고 패터닝하여 상기 콘택 개구부를 통해 소오스/드레인(4,5)과 연결되는 소오스/드레인 전극(9)을 형성한다.Subsequently, a contact opening for exposing a predetermined portion of the source / drain 4,5 is formed in the interlayer insulating film 8, and then A1 is deposited and patterned on the resultant source / drain 4,5 through the contact opening. Source / drain electrodes 9 are connected to each other.
상술한 종래 기술에 있어서 다결정실리콘을 열산화시켜 게이트산화막을 형성하는 경우, 다결정실리콘의 그레인(Grain)경계에서의 산소 원자 및 분자의 확산속도가 그레인경제이외의 영역에서의 산소원자 및 분자의 확산속도보다 빠르기 때문에 형성된 게이트 산화막(6)과 활성층인 다결정실리콘(3)의 경제면이 상기한 바와 같은 산소원자 및 분자의 확산속도 차이로 인해 평탄하지 않게 된다.In the above-mentioned prior art, in the case of forming a gate oxide film by thermally oxidizing polycrystalline silicon, the diffusion rate of oxygen atoms and molecules in the grain boundary of the polycrystalline silicon is different from the grain economy. Since it is faster than the speed, the economic surface of the formed gate oxide film 6 and the active layer polysilicon 3 is not flat due to the difference in diffusion rate of oxygen atoms and molecules as described above.
또한 상기와 같이 게이트 절연막을 열산화막으로 형성할 경우 고온에서 공정이 진행되므로 석영(Quartz)과 같은 고가의 기판을 사용해야 하는 단점이 있다.In addition, as described above, when the gate insulating film is formed of a thermal oxide film, the process proceeds at a high temperature, and thus a disadvantage is that an expensive substrate such as quartz is used.
또한, CVD산화막으로 게이트절연막을 형성할 경우에는 활성층인 다결층인 다결정실리콘(3)의 표면이 게이트산화막(6)과 채널사이의 계면이 되므로 계면 포획상태(trap state)가 커서 역시 전자 이동도가 낮아지게 된다.In addition, when the gate insulating film is formed of the CVD oxide film, the surface of the polysilicon layer 3, which is the active layer, becomes the interface between the gate oxide film 6 and the channel, so that the interface trap state is large, which also causes electron mobility. Will be lowered.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 저온 공정이 가능하며, 다결정 실리콘의 전자 이동도를 증가시켜 다결정실리콘 TFT의 구동능력을 향상시킬 수 있는 다결정실리콘 TFT의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and a low temperature process is possible, and a method of manufacturing a polysilicon TFT capable of improving the driving ability of the polycrystalline silicon TFT by increasing the electron mobility of the polycrystalline silicon is provided. have.
상기 목적을 달성하기 위해 본 발명은 다결정실리콘 바막트랜지스터의 게이트 절연막을 ECR(Electron Cyclotron Resonance)에 의한 산소 플라즈마를 이용하여 형성한 얇은 산화막으로 형성한다.In order to achieve the above object, the present invention forms a gate insulating film of a polysilicon bar film transistor as a thin oxide film formed using oxygen plasma by ECR (Electron Cyclotron Resonance).
ECR 산소 플라즈마는 기판에 수직인 방향으로 수십 eV정도의에너지를 갖는 산소이온과 산소원자가 존재하여 100Å∼400Å정도 두께의 얇은 산화막을 형성하는 것이 가능하다.In the ECR oxygen plasma, oxygen ions and oxygen atoms having an energy of about several tens of eV in a direction perpendicular to the substrate can be formed to form a thin oxide film having a thickness of about 100 kPa to about 400 kPa.
따라서 활성영역이 되는 다결정실리콘층을 형성한후, 다결정실리콘 표면부위에 ECR 산소 플라즈마를 이용하여 산화막을 얇게 형성할 수 있으며, 채널부분이 되는 상기 다결정실리콘 표면과 산화막간의 우수한 계면상태를 얻을 수 있다.Therefore, after forming the polysilicon layer serving as an active region, an oxide film can be formed thinly on the surface of the polysilicon using ECR oxygen plasma, and an excellent interface state between the surface of the polysilicon and the oxide layer serving as the channel portion can be obtained. .
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3도에 본 발명의 일실시예에 따른 다결정실리콘 TFT의 제조를 위한 공정 순서도를 나타내었다.3 shows a process flow chart for manufacturing a polysilicon TFT according to an embodiment of the present invention.
먼저, 제3도(a)에 도시된 바와 같이 기판(1)상에 초기산화막(2)으로서 CVD산화막을 5000Å정도의 두께로 형성한 후, 다결정실리콘을 증착하고 이를 소정 패턴으로 패터닝한다.First, as shown in FIG. 3A, a CVD oxide film is formed on the substrate 1 as the initial oxide film 2 to a thickness of about 5000 kPa, and then polycrystalline silicon is deposited and patterned into a predetermined pattern.
이어서 제3도(b)에 도시된 바와 같이 챔버내 압력을 0.5∼2mTorr, 예컨대, 1.2mtorr로 하고, 기판 온도는 100℃∼400℃ 산소 유량 6sccm, 아르곤유량 8sccm으로 한 공정 조건하에서 ECR산소 플라즈마에 의해 산화막(10)을 다결정실리콘 표면에 150Å∼450Å 두께로 얇게 형성한다.Subsequently, as shown in FIG. 3 (b), the chamber pressure is 0.5 to 2 mTorr, for example, 1.2 mtorr, and the substrate temperature is 100 ° C. to 400 ° C. at an oxygen flow rate of 6 sccm and an argon flow rate of 8 sccm. Thus, the oxide film 10 is thinly formed on the surface of the polycrystalline silicon with a thickness of 150 kV to 450 kV.
이어서 제3도(c)에 도시된 바와 같이 상기 ECR산화막(10)상에 CVD산화막(11)을 증착한다.Subsequently, a CVD oxide film 11 is deposited on the ECR oxide film 10 as shown in FIG.
이때 ECR산화막과 CVD산화막을 합한 두께가 800Å∼1500Å가 되도록 CVD산화막을 증착한다.At this time, the CVD oxide film is deposited so that the total thickness of the ECR oxide film and the CVD oxide film is 800 mW to 1500 mW.
이어서 상기 CVD산화막(11)상에 다결정실리콘 또는 비정질실리콘을 CVD방법에 의해 2000Å∼4000Å 증착한다.Subsequently, polysilicon or amorphous silicon is deposited on the CVD oxide film 11 by 2000 kV to 4000 kV by the CVD method.
다음에 제3도에(d)에 도시된 바와 같이 상기 증착된 다결정실리콘 또는 비정질실리콘을 게이트 패턴으로 패터닝하여 게이트(7)를 형성한 후, 소오스/드레인(4,5)을 형성하기 위한 이온 주입 공정을 행하고, 상기 결과물 전면에 층간절연막(8)으로서 CVD산화막을 3000Å∼4000Å 형성한 후, 소오스/드레인(4,5)의 소정 부분이 노출되도록 상기 CVD산화막(8)에 콘택 개구부를 형성한 다음 결과물 전면에 A1을 증착하고 소정 패턴으로 패터닝하여 상기 콘택 개구부를 통해 소오스/드레인(4,5)과 연결되는 소오스/드레인전극(9)을 형성한다.Next, as shown in (d) of FIG. 3, the deposited polycrystalline silicon or amorphous silicon is patterned in a gate pattern to form a gate 7, and then ions for forming the source / drain 4 and 5 are formed. An implantation process is performed, and a CVD oxide film is formed in the entire surface of the resultant as the interlayer insulating film 8, and the CVD oxide film 8 is formed so that a predetermined portion of the source / drain 4 and 5 is exposed. Then, A1 is deposited on the entire surface of the resultant and patterned in a predetermined pattern to form a source / drain electrode 9 connected to the source / drain 4 and 5 through the contact opening.
본 발명의 다른 실시예로서 게이트 절연막을 ECR산소 플라즈마를 이용한 ONO(Oxide/Nitride/Oxide)막을 형성할 수 있다.As another embodiment of the present invention, an ONO (Oxide / Nitride / Oxide) film using a gate insulating film as an ECR oxygen plasma may be formed.
즉, 제4도에 도시한 바와 같이 상술한 본 발명의 일실시예와 동일한 공정에 의해 다결정실리콘 패턴(3)까지 형성한 다음 다결정실리콘 표면에 상기 일실시예의 공정조건과 동일한 공정조건하에서 ECR 산소 플라즈마에 의해 얇은 산화막(10)을 형성한 후, 반응 가스인 산소와 캐리어가스인 아르곤가스만을 실리콘 화합물 가스와 질소 또는 질소 화합물 가스로서 예컨대, SiH4와 N2가스로 교체하여 공정을 진행하여 질화막(12)을 형성한 다음 다시 SiH4와 N2가스를 O2와 Ar으로 교체하여 ECR산소 플라즈마에 의한 산화막(13)을 형성함으로서 ONO막을 형성한다.That is, as shown in FIG. 4, the polysilicon pattern 3 is formed by the same process as in the above-described embodiment of the present invention, and then ECR oxygen is formed on the surface of the polycrystalline silicon under the same process conditions as those of the embodiment. After the thin oxide film 10 is formed by plasma, only the oxygen gas and the argon gas as the carrier gas are replaced with silicon compound gas and nitrogen or nitrogen compound gas, for example, SiH 4 and N 2 gas, and the process proceeds to the nitride film. (12) was formed, and then SiH 4 and N 2 gases were replaced with O 2 and Ar to form an oxide film 13 by ECR oxygen plasma, thereby forming an ONO film.
이때 ONO막 형성후, 산소 및 질소 이온과 원자들의 활성화를 위해서 500∼600℃에서 열처리 공정을 행한다.At this time, after the ONO film is formed, a heat treatment is performed at 500 to 600 ° C. to activate oxygen, nitrogen ions, and atoms.
본 발명의 또 다른 실시예로서 상기 실시예에서와 같이 게이트 절연막을 ECR산화막과 CVD산화막으로 이루어진 이중 구조의 산화막 또는 ECR산화막과 질화막 및 ECR산화막으로 된 ONO막으로 형성하지 않고, 상술한 ECR산화막 형성 공정 조건과 동일한 공정 조건하에서 제5도에 도시된 바와 같이 ECR산소 플라즈마에 의해 400Å정도의 산화막(10)을 형성하고 이를 500∼600℃의 온도에서 열처리하여 ECR산소 플라즈마에 의한 산화막의 단일막을 게이트 절연막으로 사용할 수도 있다.As another embodiment of the present invention, the gate insulating film is not formed of an oxide film having a dual structure consisting of an ECR oxide film and a CVD oxide film or an ONO film made of an ECR oxide film, a nitride film, and an ECR oxide film, as in the above embodiment. As shown in FIG. 5 under the same process conditions as the process conditions, an oxide film 10 of about 400 kV is formed by an ECR oxygen plasma and heat-treated at a temperature of 500 to 600 ° C. to gate a single film of the oxide film by ECR oxygen plasma. It can also be used as an insulating film.
제6도는 TFT 제조 공정시의 최대 온도가 950℃이고, 게이트 산화막으로서 ECR 산소 플라즈마에 의한 산화막의 두께가 330Å이고 이 ECR 산화막을 포함한 전체 게이트 산화막의 두께가 850Å이며, 게이트 폭(W) 및 길이(L)의 비가 W/L=20/20㎛인 다결정 실리콘 TFT의 ID-VG(게이트에 인가되는 전압 대 드레인 전류) 특성을 나타낸 것으로의 식으로 부터(여기서, μ는 전자 이동도, Cox는 게이트 절연막의 단위면적당 커패시턴스, VD는 드레인 전압을 각각 나타낸다) 채널영역에서의 전자 이동도가 115cm2/V·sec가 얻어짐을 알 수 있다.6, the maximum temperature in the TFT fabrication process is 950 DEG C, the oxide film by the ECR oxygen plasma is 330 kPa as the gate oxide film, the total gate oxide film including the ECR oxide film is 850 kPa, the gate width W and the length. I D -V G (voltage vs. drain current applied to the gate) of polycrystalline silicon TFTs with a ratio of (L) of W / L = 20 / 20㎛ It can be seen from the equation that μ is the electron mobility, Cox is the capacitance per unit area of the gate insulating film, and V D is the drain voltage, respectively, and the electron mobility in the channel region is 115 cm 2 / V · sec. have.
제7도는 공정의 최대 온도가 600℃이고, ECR산화막의 두께가 400Å, 전체 게이트 산화막의 두께가 800Å이며, 게이트의 W/L가 50/20㎛인 TFT의 ID-VG특성을 나타낸 것으로, 이 경우 상기의 식으로 부터 안정하게 51cm2/V·sec의 전자 이동도가 얻어지는바 본 발명에 있어서 600℃이하의 공정에서도 비교적 높은 전자 이동도를 얻을 수 있음을 알 수 있다.7 shows the I D -V G characteristics of a TFT having a maximum temperature of 600 ° C., an ECR oxide thickness of 400 μs, an entire gate oxide thickness of 800 μs, and a gate W / L of 50/20 μm. In this case, the electron mobility of 51 cm 2 / V · sec can be stably obtained from the above equation, and thus, it can be seen that a relatively high electron mobility can be obtained in the process of 600 ° C. or less.
이상과 같이 본 발명은 다결정실리콘 TFT의 게이트 절연막을 ECR산소 플라즈마를 이용하여 형성하여 채널영역에서의 전자 이동도를 증가시킴으로써 LCD구동회로를 이용할 경우 구동속도의 증가로 인해 구동능력이 향상되므로 구동회로의 블럭수를 줄일 수 있어 구동회로가 간단해지고 따라서 제조 공정에 있어서의 수율을 높일 수 있게 된다.As described above, according to the present invention, the gate insulating film of the polysilicon TFT is formed by using ECR oxygen plasma to increase the electron mobility in the channel region. The number of blocks can be reduced, so that the driving circuit can be simplified, and thus the yield in the manufacturing process can be increased.
뿐만 아니라 본 발명은 저온공정에 의해서도 안정된 전자 이동도를 얻은 것이 가능하므로 저온공정 LCD용 다결정실리콘 TFT의 제조에 적용할 수 있어 저가의 유리기판의 사용이 가능하게 됨에 따라 제조원가를 절감시킬 수 있게 된다.In addition, since the present invention can obtain stable electron mobility even by low temperature process, it can be applied to the production of polycrystalline silicon TFT for low temperature process LCD, thereby making it possible to use low cost glass substrate, thereby reducing the manufacturing cost. .
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930019651A KR970011502B1 (en) | 1993-09-24 | 1993-09-24 | Thin film transistor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930019651A KR970011502B1 (en) | 1993-09-24 | 1993-09-24 | Thin film transistor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950010121A KR950010121A (en) | 1995-04-26 |
| KR970011502B1 true KR970011502B1 (en) | 1997-07-11 |
Family
ID=19364536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930019651A KR970011502B1 (en) | 1993-09-24 | 1993-09-24 | Thin film transistor manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970011502B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101218687B1 (en) * | 2011-06-30 | 2013-01-21 | 재단법인 서남권청정에너지기술연구원 | Method for forming low-temperature gate oxide film of thin film transistor using tetra-iso-propoxysilane |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100357173B1 (en) * | 1996-07-31 | 2003-01-24 | 주식회사 하이닉스반도체 | Method for manufacturing thin film transistor |
-
1993
- 1993-09-24 KR KR1019930019651A patent/KR970011502B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101218687B1 (en) * | 2011-06-30 | 2013-01-21 | 재단법인 서남권청정에너지기술연구원 | Method for forming low-temperature gate oxide film of thin film transistor using tetra-iso-propoxysilane |
Also Published As
| Publication number | Publication date |
|---|---|
| KR950010121A (en) | 1995-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4988634A (en) | Method for forming FET with a super lattice channel | |
| KR100741435B1 (en) | Controlling the properties and uniformity of a silicon nitride film by controlling the film forming precursors and tft device with the silicon nitride | |
| US6188104B1 (en) | Trench DMOS device having an amorphous silicon and polysilicon gate | |
| KR20010094962A (en) | Method of forming ohmic contacts using a self doping layer for thin-film transistors | |
| US5700699A (en) | Method for fabricating a polycrystal silicon thin film transistor | |
| KR20040021758A (en) | Method for fabricating of a poly-Si TFT | |
| KR100317641B1 (en) | Thin film transistor and the method of fabricating the same | |
| KR100473997B1 (en) | A method of fabricating the same | |
| US6514803B1 (en) | Process for making an amorphous silicon thin film semiconductor device | |
| KR970011502B1 (en) | Thin film transistor manufacturing method | |
| US6306692B1 (en) | Coplanar type polysilicon thin film transistor and method of manufacturing the same | |
| KR100317640B1 (en) | Thin film transistor and the method of fabricating the same | |
| JPH06232402A (en) | Manufacture of thin film semiconductor device | |
| US6455329B1 (en) | Method for fabricating a capacitor in a semiconductor device | |
| JPH06260644A (en) | Manufacture of semiconductor device | |
| JP3644977B2 (en) | Method for manufacturing polycrystalline silicon thin film transistor | |
| KR100272579B1 (en) | Method for fabricating thin film transistor | |
| KR100301852B1 (en) | Method for fabricating tft | |
| KR100307540B1 (en) | Fabricating method of semiconductor device | |
| KR100397876B1 (en) | Thin film transistor and the method of fabricating the same | |
| KR100323736B1 (en) | Thin film transistor and fabricating method thereof | |
| KR19980058438A (en) | Silicide Formation Method of Semiconductor Device | |
| JP2880892B2 (en) | Method for manufacturing semiconductor device | |
| KR100259068B1 (en) | Method for manufacturing mosfet of soi structure | |
| JPH06188263A (en) | Manufacture of self-alignment type thin film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20021128 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |