KR100323736B1 - Thin film transistor and fabricating method thereof - Google Patents
Thin film transistor and fabricating method thereof Download PDFInfo
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- KR100323736B1 KR100323736B1 KR1019950028152A KR19950028152A KR100323736B1 KR 100323736 B1 KR100323736 B1 KR 100323736B1 KR 1019950028152 A KR1019950028152 A KR 1019950028152A KR 19950028152 A KR19950028152 A KR 19950028152A KR 100323736 B1 KR100323736 B1 KR 100323736B1
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- 239000010409 thin film Substances 0.000 title abstract description 10
- 238000000034 method Methods 0.000 title abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 89
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 150000004767 nitrides Chemical class 0.000 claims abstract description 44
- 239000012535 impurity Substances 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 18
- 230000007547 defect Effects 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 60
- 238000004519 manufacturing process Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 238000005224 laser annealing Methods 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
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- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 238000005984 hydrogenation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
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- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229940116641 vaginal film Drugs 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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Abstract
Description
본 발명은 박막 트랜지스터(Thin Film Transistor; 이하 TFT라 칭함) 및 그 제조 방법에 관한 것으로서, 코플라나형 TFT에서 게이트 절연막으로 질화막(SiNx)을 사용함으로써 게이트 적연막과 다결정실리콘막 사이의 경계결함 밀도를 줄여 누설전류가 작고 전하의 이동도가 높은 TFT 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as a TFT) and a method of manufacturing the same, wherein a boundary defect between a gate integrator and a polysilicon film is used by using a nitride film (SiN x ) as a gate insulating film in a coplanar TFT. The present invention relates to a TFT having a low leakage current and a high charge mobility by reducing the density, and a method of manufacturing the same.
일반적으로 다결정실리콘 TFT는 액정표시장치(Liquid Crystal Display : 이하 LCD라 칭함)의 화소전극 구동소자와 주변회로의 기본소자 등에 사용된다.In general, polysilicon TFTs are used for pixel electrode driving elements of liquid crystal displays (hereinafter referred to as LCDs) and basic elements of peripheral circuits.
이러한 TFT의 구조는 크게 반도체층 패턴인 활성층과 전극의 위치에 따라 구별할 수 있다.The structure of such a TFT can be largely classified according to the positions of the active layer and the electrode, which are semiconductor layer patterns.
즉 반도체층을 사이에 두고 게이트 전극과 소오스/드레인 전극이 분리되어 있는 스테거드(Staggered)형과 반도체층의 일면에 게이트 전극과 소오스/드레인 전극이 나란히 형성되어 있는 코플라나(Coplanar)형으로 나눈다.That is, it is divided into a staggered type in which a gate electrode and a source / drain electrode are separated with a semiconductor layer interposed therein, and a coplanar type in which a gate electrode and a source / drain electrode are formed in parallel on one surface of the semiconductor layer. .
제 1A 도 내지 제 1C 도는 종래 기술의 일실시예에 따른 TFT의 제조공정도로써, 산화막을 사용한 일반적인 코플라나형 TFT의 예이다.1A to 1C are manufacturing process diagrams of a TFT according to an embodiment of the prior art, which is an example of a general coplanar TFT using an oxide film.
먼저, 절연기판(10)상에 반도체층(11) 패턴을 형성하고 레이저 아닐링(Anealing)으로 다결정화시켜 다결정실리콘(12A) 패턴을 형성한다(제 1A 참조).First, a pattern of the semiconductor layer 11 is formed on the insulating substrate 10 and polycrystalline by laser annealing to form a polycrystalline silicon 12A pattern (see 1A).
상기 제 1 및 제 2 다결정실리콘층(12A),(12B)상에 불순물 이온을 주입하고 고농도 불순물 반도체층(15)을 형성한다.Impurity ions are implanted onto the first and second polysilicon layers 12A and 12B to form a high concentration impurity semiconductor layer 15.
이때 제 1 다결정실리콘(12A) 패턴은 상측 일부만이 고농도 불순물 반도체층(15)이 되고, 제 2 다결정실리콘(12B) 패턴은 전부 고농도 불순물 반도체층(15) 패턴이 된다(제 1B 도 참조).At this time, only the upper portion of the first polycrystalline silicon 12A pattern becomes the high concentration impurity semiconductor layer 15, and the second polysilicon 12B patterns all become the high concentration impurity semiconductor layer 15 pattern (see also FIG. 1B).
그다음 상기 구조의 전표면에 산화막이나 질화막으로된 층간 절연막(18)을 형성하고, 상기 제 1 다결정실리콘층(12A) 패턴상에 형성되어 있는 고농도 불순물 반도체층(15) 상부의 층간 절연막(18)을 제거하여 콘택층을 형성한 후, 상기 콘택홀을 통하여 고농도 불순물 반도체층(15)과 접촉되는 소오스/드레인 전극(17)을 형성한다.Then, an interlayer insulating film 18 made of an oxide film or a nitride film is formed on the entire surface of the structure, and the interlayer insulating film 18 over the high concentration impurity semiconductor layer 15 formed on the first polycrystalline silicon layer 12A pattern. After removing the contact layer to form a contact layer, a source / drain electrode 17 is formed to contact the high concentration impurity semiconductor layer 15 through the contact hole.
이때 상기 산화막(13) 패턴과 상부에 형성되어 있는 고농도 불순물 반도체층 (15)이 게이트 전극이 된다(제 1C 도 참조).At this time, the pattern of the oxide film 13 and the highly doped impurity semiconductor layer 15 formed thereon become a gate electrode (see also FIG. 1C).
상기와 같은 종래 제 1 실시 기술은 상기 반도체층위에 고온(550℃ 이상)에서 도포되는 산화막(게이트 절연막)을 이용하므로 채널이 되는 반도체층과 게이트 산화막의 계면에 많은 결함이 생성되고 상기 계면의 특성이 악화되어 소자의 동작특성이 떨어지는 문제점이 있다.Since the conventional first embodiment uses an oxide film (gate insulating film) coated on the semiconductor layer at a high temperature (550 ° C. or more), many defects are generated at the interface between the semiconductor layer serving as a channel and the gate oxide film. There is a problem that the deterioration of the operation characteristics of the device is deteriorated.
고농도 불순물 반도체층(15)의 저항을 감소시키기 위한 600℃ 이상의 고온 열처리 공정이 필요하다는 단점이 있다.There is a disadvantage in that a high temperature heat treatment process of 600 ° C. or more is required to reduce the resistance of the high concentration impurity semiconductor layer 15.
그리고 층간 절연막(18)을 제작하기 때문에 게이트 전극을 노출시키는 공정이 추가된다.And since the interlayer insulation film 18 is manufactured, the process of exposing a gate electrode is added.
제 2A 도 및 제 2C 도는 종래 기술의 제 2 실시예에 따른 TFT의 제조공정도와 단면도이다.2A and 2C are manufacturing process diagrams and cross-sectional views of a TFT according to a second embodiment of the prior art.
먼저, 절연기판(10)상에 다결정실리콘(12) 패턴을 형성하고, 상기 다결정실리콘층(12) 패턴에서 채널로 예정된 부분상에 예를들어 300℃ 이하의 온도에서 CVD 방법으로 형성된 산화막(13) 패턴을 형성한 후, 상기 산화막(13) 패턴 양측의 다결정실리콘(12) 패턴상에 고농도 불순물 반도체층(15)을 형성한다.First, a polysilicon 12 pattern is formed on the insulating substrate 10, and an oxide film 13 formed by, for example, a CVD method at a temperature of 300 ° C. or less on a portion scheduled as a channel in the polysilicon layer 12 pattern. After the (I) pattern is formed, a high concentration impurity semiconductor layer 15 is formed on the polysilicon 12 patterns on both sides of the oxide film 13 pattern.
이때 고농도 불순물 반도체층(15) 형성을 위한 열처리는 예를들어 300℃ 이하에서 실시된다(제 2A 도 참조).At this time, the heat treatment for forming the high concentration impurity semiconductor layer 15 is performed at 300 ° C. or lower (see also FIG. 2A).
그후, 상기 구조의 전표면에 고온 400℃ 이상에서 층간 절연막(18)(예를들면 산화막)을 형성하고, 상기 양측 고농도 불순물 반도체층(15)상의 층간 절연막(18)을 제거하여 콘택홀을 형성한 후 상기 콘택홀을 통하여 고농도 불순물 반도체층 (15)과 접촉되는 소오스/드레인 전극(17)을 형성한다.Thereafter, an interlayer insulating film 18 (e.g., an oxide film) is formed on the entire surface of the structure at a high temperature of 400 ° C. or higher, and the interlayer insulating film 18 on the both high concentration impurity semiconductor layers 15 is removed to form contact holes. Thereafter, a source / drain electrode 17 is formed to contact the high concentration impurity semiconductor layer 15 through the contact hole.
그다음 상기 산화막(13) 패턴 상부의 층간 절연막(18)상에 도전 배선으로된 게이트 전극(16)을 형성하여 TFT를 완성한다(제 2B 도 참조).Then, a gate electrode 16 made of conductive wiring is formed on the interlayer insulating film 18 over the oxide film 13 pattern to complete the TFT (see also FIG. 2B).
상기의 종래 제 2 실시 TFT는 저온에서 고농도 불순물 반도체층의 제작이 가능하여 산화막과 다결정실리콘 패턴 계면의 결함밀도를 감소시킬수 있으나, 층간 절연막(18)을 고온에서 형성하여야 하므로 계면결함 밀도의 감소에 한계가 있다.The conventional second embodiment of the TFT is capable of fabricating a high concentration impurity semiconductor layer at a low temperature, thereby reducing the defect density between the oxide film and the polysilicon pattern interface. However, since the interlayer insulating film 18 must be formed at a high temperature, the interfacial defect density is reduced. There is a limit.
또한 고농도 이온주입시 산화막(13)내에 양이온들이 축적되기 때문에 장시간의 TFT 구동이나 외부전계 인가시에 소자의 동작특성이 저하되는 문제점이 있다.In addition, since the cations are accumulated in the oxide film 13 during the high ion concentration implantation, there is a problem in that the operation characteristics of the device are degraded when the TFT is driven for a long time or an external electric field is applied.
본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 게이트 절연막으로 질화막을 사용하여 다결정실리콘과의 경계결함 밀도를 줄이고, 고농도 불순물 이온주입시 질화막에 양이온들이 축적되지 않아 전하이동도 및 소자동작의 신뢰성을 향상시킬수 있는 TFT클 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to reduce the boundary defect density with polysilicon using a nitride film as a gate insulating film, the charge mobility is not accumulated in the nitride film when a high concentration impurity ion implantation And a TFT clasp that can improve the reliability of device operation.
본 발명의 다른 목적은 고농도 불순물 반도체층 형성에서 이온주입 공정시, 질화막을 이온주입 마스크로 사용하여 이온주입에 따른 양이온의 축적을 방지하여 소자동작의 신뢰성을 향상시킬수 있는 TFT를 제공함에 있다.Another object of the present invention is to provide a TFT that can improve the reliability of device operation by preventing the accumulation of cations due to ion implantation by using a nitride film as an ion implantation mask in the ion implantation process in the formation of a high concentration impurity semiconductor layer.
본 발명의 다른 목적은 고농도 불순물이 함유된 반도체층을 이온도핑을 이용하여 제작하여 소오스/드레인 접촉부분의 저항을 줄이고 정공의 전류에 의한 오프상태의 누설전류를 감소시킬수 있는 TFT를 제공함에 있다.Another object of the present invention is to provide a TFT which can reduce the resistance of the source / drain contact portion and reduce the leakage current in the off state due to the hole current by fabricating a semiconductor layer containing high concentration impurities using ion doping.
다른 목적을 달성하기 위한 본 발명에 따른 TFT 제조 방법의 특징은, 레이저 아닐링을 통하여 제작된 양질의 다결정실리콘위에 질화막을 도포하고 이를 이온 스토퍼로 사용하여 이온도핑을 하고 난후 별도의 불순물의 활성화 과정없이 고농도 불순물 반도체층을 형성할 수 있기 때문에 소오스/드레인층의 금속 도포시 좋은 저항성 접촉층을 형성하고, 액정디스플레이에의 적용시 균일성과 대면적화에 필요한 간단한 제조공정을 구비함에 있다.A feature of the TFT manufacturing method according to the present invention for achieving another object is to apply a nitride film on the high-quality polysilicon fabricated through laser annealing and use it as an ion stopper to ion doping, and then activate an additional impurity Since it is possible to form a high concentration impurity semiconductor layer without forming a resistive contact layer that is good for metal coating of the source / drain layer, and has a simple manufacturing process required for uniformity and large area when applied to the liquid crystal display.
특히 상기의 TFT는 매우 높은 전하이동도를 가지고 낮은 누설전류 밀도를 가지기 위해 저저항의 고농도 불순물 반도체층을 소오스/드레인 접촉층으로 확보하고 채널영역의 공기중 노출을 최소화 하고 질화막을 통한 자기수소화를 유도할 수 있다.In particular, in order to have a very high charge mobility and a low leakage current density, the TFT has a low-resistance high-concentration impurity semiconductor layer as a source / drain contact layer, minimizes exposure to air in the channel region, and performs self-hydrogenation through a nitride film. Can be induced.
이하, 첨부도면을 참조하여 본 발명에 따른 질화막을 게이트 절연막으르 사용한 다결정 실리콘 TFT 및 그 제조 방법을 상세히 설명한다.Hereinafter, a polycrystalline silicon TFT using a nitride film according to the present invention as a gate insulating film will be described in detail with reference to the accompanying drawings.
제 3 도는 본 발명에 따른 질화막을 게이트 절연막으로 사용한 다결정실리콘 TFT의 단면도이다.3 is a cross-sectional view of a polysilicon TFT using the nitride film according to the present invention as a gate insulating film.
먼저, 석영이나 유리 또는 산화막 등의 절연기판(10)상에 비정질 실리콘 반도체층을 레이저 아닐링한 다결정실리콘(12)이 형성되어 있으며, 상기 반도체층 (12)위에 이온 스토퍼인 제 1 질화막(l4A)을 플라즈마 CVD로 도포한다.First, a polysilicon 12 obtained by laser annealing an amorphous silicon semiconductor layer is formed on an insulating substrate 10 such as quartz, glass, or an oxide film, and a first nitride film l4A which is an ion stopper on the semiconductor layer 12. ) Is applied by plasma CVD.
그리고 상기 제 1 질화막(14A)에서 채널부위만 남기고 나머지 부분을 에칭하여 제 1 질화막(14A) 패턴을 형성고 이온도핑으로 고농도 불순물 반도체층(15)을 형성한다.The remaining portion of the first nitride layer 14A is etched to form a first pattern of the first nitride layer 14A, and the ion doped to form a highly impurity semiconductor layer 15 by etching the remaining portion.
또한 소오스/드레인 접촉층은 N형 불순물이 주입되어 있기 때문에 저저항의 고농도 불순물 반도체층(15)을 형성하고, 이온도핑후 수소화를 통하여 저항을 감소시킬수 있다.In addition, since the source / drain contact layer is implanted with N-type impurities, it is possible to form a low-resistance high-concentration impurity semiconductor layer 15 and reduce resistance through hydrogenation after ion doping.
상기의 소오스/드레인 전극(17)부분은 전극용 금속층을 도포하여 게이트 전극(16)과 일면으로 맞추어 형성한다(제 3 도 참조).The source / drain electrodes 17 are formed by coating an electrode metal layer with one side of the gate electrode 16 (see FIG. 3).
소오스/드레인과 게이트의 채널부는 일면상에 있게 되고 TFT의 구동시에 채널부와의 저항을 감소시킬수 있다.The channel portion of the source / drain and gate is on one surface and can reduce the resistance with the channel portion when driving the TFT.
특히 본 발명에 따른 TFT의 경우 고농도 불순물층(15)의 활성화나 이온도핑시의 이온스토퍼 내부의 양이온 축적을 제거할 수 있기 때문에 우수한 동작특성을 가지고, 제작방법이 간단하다는 특징을 갖는다.In particular, in the TFT according to the present invention, since it is possible to eliminate the activation of the high concentration impurity layer 15 and the accumulation of cations in the ion stopper during ion doping, the TFT has excellent operating characteristics and a simple manufacturing method.
여기서 상기 게이트 전극(16)은 소오스/드레인과 같은 금속을 사용하도록 되어 있고 Cr 또는 Al 등의 도전물질 패턴으로 형성하며, 직렬저항을 감소키기기 위하여 상기 고농도불순물 반도체층(15)을 형성한다.Here, the gate electrode 16 is formed of a metal such as source / drain, is formed of a conductive material pattern such as Cr or Al, and the high concentration impurity semiconductor layer 15 is formed to reduce series resistance.
상기와 같은 본 발명에 따른 TFT는 반도체층위에 질화막을 이온 스토퍼로 사용하기 때문에 이온도핑시 양이온의 축적을 방지할 수 있고, 이온주입 공정후 막간의 절연층(18)으로 플라즈마 CVD에 의한 질화막을 형성하기 때문에 제작이 용이하고 다결정실리콘(12)과의 좋은 경계특성으로 인하여 이동도가 높고 동작특성이 우수한 TFT를 제작할 수 있다.Since the TFT according to the present invention uses the nitride film as an ion stopper on the semiconductor layer, it is possible to prevent the accumulation of cations during ion doping, and to form the nitride film by plasma CVD as the insulating layer 18 between the films after the ion implantation process. Due to the formation, it is easy to manufacture and due to the good boundary characteristics with the polysilicon 12, it is possible to manufacture a TFT having high mobility and excellent operation characteristics.
제 4A 도 내지 제 4D 도는 본 발명에 따른 TFT의 제조공정도이다.4A to 4D are manufacturing process diagrams of the TFT according to the present invention.
상기 절연기판(10)상에 상압 CVD로 제작된 비정질 실리콘(11)을 레이저 아닐링하여 다결정실리콘층(12) 패턴을 형성한다(제 4A도 참조).A pattern of the polysilicon layer 12 is formed by laser annealing the amorphous silicon 11 produced by atmospheric pressure CVD on the insulating substrate 10 (see also FIG. 4A).
상압 CVD에 의한 비정질 실리콘층(11)은 박막내의 수소량이 현저히 낮기 때문에 플라즈마 CVD로 제작된 비정질 실리콘의 레이저 아닐링하여 필수적인 탄수소화 과정을 거치지 않고도 양질의 다결정실리콘(12)을 제작할 수 있는 장점을 가진다.Since the amorphous silicon layer 11 by atmospheric CVD has a significantly low amount of hydrogen in the thin film, it is possible to produce high-quality polysilicon 12 without laser annealing of the amorphous silicon produced by plasma CVD without undergoing an essential carbohydrate process. Has
레이저 아닐링으로 다결정실리콘층(12) 패턴을 형성한 뒤 플라즈마 CVD로 제 1 질화막층을 증착한 후, 패턴을 형성한다.After the polysilicon layer 12 pattern is formed by laser annealing, the first nitride film layer is deposited by plasma CVD, and then the pattern is formed.
여기서 다결정실리콘층(12)과 제 1 질화막층(14A)의 경계밀도를 줄이기 위하여 제 1 질화막층(14A)을 증착하기 이전에 다결정실리콘층(12)상에 수소와 질소 등을 이용한 플라즈마로 표면처리를 한다(제 4B 도 참조).Here, in order to reduce the boundary density between the polysilicon layer 12 and the first nitride layer 14A, the surface of the polysilicon layer 12 with plasma using hydrogen and nitrogen is deposited on the polysilicon layer 12 before the deposition of the first nitride layer 14A. Treatment is performed (see also FIG.
제 1 질확막층(14A) 패턴위에 이온도핑으로 고농도 불순물 반도체층(15)을 다결정실리콘층(12) 패턴의 양측 상부에 형성하고, 이온도핑이 끝난뒤 층간 절연막으로 제 2 질화막층(14B)을 도포한다(제 4C 도 참조).A high concentration impurity semiconductor layer 15 is formed on both sides of the polysilicon layer 12 pattern by ion doping on the first vaginal film layer 14A pattern, and after the ion doping is completed, the second nitride film layer 14B is formed as an interlayer insulating film. Apply (see Figure 4C).
이온도핑에 의하여 고농도 불순물 반도체층(15)의 형성이 끝난뒤 전표면에 제 2 질화막층(14B)을 도포하고, 소오스/드레인의 콘택층을 형성하기 위하여 제 2 질확막층(14B) 패턴을 형성하여 고농도 불순물 반도체층(15)을 노출시키고, 전극용 금속(Cr, Al)을 도포하여 게이트 전극(16)과 소오스/드레인 전극(17)을 형성한다(제 4D 도 참조).After the formation of the high concentration impurity semiconductor layer 15 by ion doping, the second nitride film layer 14B is applied to the entire surface, and the second nitride film layer 14B pattern is formed to form a source / drain contact layer. The high concentration impurity semiconductor layer 15 is exposed to form a gate electrode 16 and a source / drain electrode 17 by applying electrode metals Cr and Al (see FIG. 4D).
제 5 도는 본 발명의 실시예에 따른 TFT의 전류-전압 및 채널 트랜스 컨덕턴스-전압관계를 나타내는 것으로, 기존의 저압 CVD, 열산화 방법, 상압 CVD 등에 의한 산화막을 사용한 다결정실리콘 TFT의 특성보다 준문턱전압 기울기(드레인 전류를 10배이상 증가시키는데 필요한 게이트 전압비)가 낮다.5 shows a current-voltage and channel transconductance-voltage relationship of a TFT according to an embodiment of the present invention, which is a quasi-threshold than the characteristics of a polysilicon TFT using an oxide film by a conventional low pressure CVD, thermal oxidation method, and atmospheric pressure CVD. The voltage slope (gate voltage ratio required to increase the drain current by more than 10 times) is low.
예를들어 기존의 방법에 의한 TFT는 준문턱전압 기울기가 0.5V/dec. 보다 크지만 본 발명에 의한 경우는 0.5V/dec. 보다 작은 값을 가진다.For example, the conventional TFT has a quasi-threshold slope of 0.5 V / dec. Larger than 0.5 V / dec. Has a smaller value.
그리고 채널 트랜스 컨덕턴스-전압의 선형영역에서 구한 전자의 이동도와 문턱전압은 각가 114cm2/Vs과 4V이다.The electron mobility and threshold voltage obtained from the linear region of the channel transconductance-voltage are 114cm 2 / Vs and 4V, respectively.
이때 채널의 폭과 너비의 비는 60㎛/10㎛이고 드레인 전압은 5V이다.At this time, the width-to-width ratio of the channel is 60 μm / 10 μm and the drain voltage is 5V.
특히 채널의 오프셋 길이가 예를들어 0㎛일때 오프상태의 누설전류가 10-10A 정도로 기존의 오프셋을 가진 TFT와 비슷한 특성을 나타냄을 알수 있다.In particular, it can be seen that when the offset length of the channel is, for example, 0 μm, the leakage current in the off state is similar to that of a TFT having a conventional offset of about 10 −10 A.
또한 문턱전압 아래의 영역에서 계산된 준문턱전압 기울기값도 종래의 제 1, 제 2 실시에 따른 TFT 보다 특성이 우수함을 알수 있다.In addition, it can be seen that the quasi-threshold slope value calculated in the region below the threshold voltage is superior to the TFTs according to the first and second embodiments of the related art.
질화막을 사용하였기 때문에 플라즈마 CVD를 이용하여 대면적으로 제작할 수 있고 230℃ 정도의 온도에서 아닐링을 통하여 자기수소화를 유도하여 채널부분의 결함밀도를 감소시킬수 있는 장점이 있다.Since the nitride film is used, it can be fabricated in a large area using plasma CVD, and has an advantage of reducing defect density in the channel portion by inducing self-hydrogenation through annealing at a temperature of about 230 ° C.
특히 기존의 층간 절연막(예를들면 : 산화막)을 사용한 TFT의 경우 제작에서 제조공정 온도는 예를들어 400℃ 이상이지만 본 발명에서는 층간 절연막과 게이트 절연막을 질화막으로 사용한 TFT는 350℃ 이하의 온도에서 제조가 가능하기 때문에 우수한 동작특성을 가질수 있는 간단한 제조공정을 확보할 수 있다.In particular, in the case of a TFT using a conventional interlayer insulating film (eg, an oxide film), the manufacturing process temperature is, for example, 400 ° C or more in manufacturing, but in the present invention, a TFT using the interlayer insulating film and the gate insulating film as a nitride film is used at a temperature of 350 ° C or less Since it is possible to manufacture, it is possible to secure a simple manufacturing process that can have excellent operating characteristics.
제 6 도는 본 발명에 따른 새로운 TFT에서 오프셋 길이에 따르는 전류-전압 특성곡선으로 오프셋 길이가 0㎛ 정도일때 최적의 특성을 나타내고 있다.FIG. 6 is a current-voltage characteristic curve according to the offset length in the new TFT according to the present invention, and shows optimum characteristics when the offset length is about 0 탆.
특히 예를들어 오프상태에서의 누설전류는 10-10A 정도로 기존의 방법에 의한 TFT의 10-9A보다 작다.In particular, for example, the leakage current in the off state is about 10 -10 A, which is smaller than the 10 -9 A of the TFT by the conventional method.
이상에서 설명한 바와 같이 본 발명에 따른 TFT 및 그 제조 방법은, 다결정실리콘 패턴상에 이온 스토퍼가 되는 제 1 질화막 패턴을 형성하고, 고농도 이온주입을 실시하여 다결정실리콘 패턴의 양측부에 고농도 불순물 반도체층을 형성하며, 상기 구조의 전표면에 층간 절연막이 되는 제 2 질화막을 도포하고 소오스/드레인 콘택홀을 형성한 후 금속으로된 소오스/드레인 전극과 게이트 전극 패턴을 형성하여 TFT를 완성하였으므르, 게이트 절연막을 저온에서 형성하여 채널과의 계면에 결함생성이 방지되고 고농도 불순물 반도체층 형성을 위한 이온주입시 제 1 질화막 패턴이 이온 스토퍼로 되어 양이온의 축적을 방지하므로 게이트 절연막의 특성열화를 방지하여 소자동작의 신뢰성을 향상시킬수 있는 이점이 있다.As described above, the TFT and the method of manufacturing the same according to the present invention form a first nitride film pattern which becomes an ion stopper on the polysilicon pattern, perform high concentration ion implantation, and have a high concentration impurity semiconductor layer on both sides of the polycrystalline silicon pattern. The second nitride film serving as the interlayer insulating film was coated on the entire surface of the structure, and the source / drain contact hole was formed, and then the source / drain electrode and the gate electrode pattern made of metal were formed to complete the TFT. Formation of the insulating film at low temperature prevents defect formation at the interface with the channel, and prevents deterioration of the characteristics of the gate insulating film because the first nitride film pattern becomes an ion stopper to prevent the accumulation of cations during ion implantation to form a high concentration impurity semiconductor layer. There is an advantage that can improve the reliability of the operation.
제 1A 도 내지 제 1C 도는 종래 기술의 제 1 실시예에 따른 박막 트랜지스터의 제조공정도1A through 1C are manufacturing process diagrams of a thin film transistor according to a first embodiment of the prior art.
제 2A 도 내지 제 2C 도는 종래 기술의 제 2 실시예에 따른 박막 트랜지스터의 제조공정도2A through 2C are manufacturing process diagrams of a thin film transistor according to a second embodiment of the prior art.
제 3 도는 본 발명에 따른 새로운 박막 트랜지스터의 단면도3 is a cross-sectional view of a new thin film transistor according to the present invention.
제 4A 도 내지 제 4D 도는 본 발명에 따른 박막 트랜지스터의 제조공정도4A through 4D are manufacturing process diagrams of the thin film transistor according to the present invention.
제 5 도는 본 발명에 따른 박막 트랜지스터의 전류-전압 및 채널 트랜스 컨덕턴스-전압그래프5 is a current-voltage and channel transconductance-voltage graph of a thin film transistor according to the present invention.
제 6 도는 본 발명의 박막 트랜지스터에서 오프셋 길이에 따르는 전류-전압그래프6 is a current-voltage graph according to an offset length in the thin film transistor of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 절연기판 11 : 비정질 실리콘층10: insulating substrate 11: amorphous silicon layer
12A : 제 1 다결정실리콘층 12B : 제 2 다결정실리콘층12A: first polycrystalline silicon layer 12B: second polycrystalline silicon layer
13 : 산화막 14A : 제 1 질화막 패턴13: oxide film 14A: first nitride film pattern
14B : 제 2 질화막 패턴 15 : 고농도 불순물 반도체층14B: second nitride film pattern 15: high concentration impurity semiconductor layer
16 : 게이트 전극 17 : 소오스/드레인 전극16 gate electrode 17 source / drain electrode
18 : 층간 절연막18: interlayer insulation film
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| KR1019950028152A KR100323736B1 (en) | 1995-08-31 | 1995-08-31 | Thin film transistor and fabricating method thereof |
| US09/057,538 US6100119A (en) | 1995-08-31 | 1998-04-09 | Thin film transistor and method for fabricating the same |
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|---|---|---|---|
| KR1019950028152A KR100323736B1 (en) | 1995-08-31 | 1995-08-31 | Thin film transistor and fabricating method thereof |
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|---|---|
| KR970013428A KR970013428A (en) | 1997-03-29 |
| KR100323736B1 true KR100323736B1 (en) | 2002-08-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950028152A KR100323736B1 (en) | 1995-08-31 | 1995-08-31 | Thin film transistor and fabricating method thereof |
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| Country | Link |
|---|---|
| KR (1) | KR100323736B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101126448B1 (en) * | 2004-12-31 | 2012-03-30 | 엘지디스플레이 주식회사 | poly silicon liquid crystal display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0442577A (en) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | Thin film transistor |
| JPH0442576A (en) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | Thin film transistor |
| JPH07202214A (en) * | 1994-01-08 | 1995-08-04 | Semiconductor Energy Lab Co Ltd | Manufacture of thin-film semiconductor device |
-
1995
- 1995-08-31 KR KR1019950028152A patent/KR100323736B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0442577A (en) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | Thin film transistor |
| JPH0442576A (en) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | Thin film transistor |
| JPH07202214A (en) * | 1994-01-08 | 1995-08-04 | Semiconductor Energy Lab Co Ltd | Manufacture of thin-film semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101126448B1 (en) * | 2004-12-31 | 2012-03-30 | 엘지디스플레이 주식회사 | poly silicon liquid crystal display device |
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| Publication number | Publication date |
|---|---|
| KR970013428A (en) | 1997-03-29 |
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