JP2004040108A - Thin film transistor with ldd structure and its manufacturing method - Google Patents

Thin film transistor with ldd structure and its manufacturing method Download PDF

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JP2004040108A
JP2004040108A JP2003270766A JP2003270766A JP2004040108A JP 2004040108 A JP2004040108 A JP 2004040108A JP 2003270766 A JP2003270766 A JP 2003270766A JP 2003270766 A JP2003270766 A JP 2003270766A JP 2004040108 A JP2004040108 A JP 2004040108A
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ldd
source
drain
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film transistor
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An Shih
安 石
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TPO Displays Corp
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Toppoly Optoelectronics Corp
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor with LDD structure and its manufacturing method which can reduce hot electron effects, current leak, and punch through. <P>SOLUTION: A thin film transistor with a single LDD structure is provided. A single LDD structure 224 is positioned between a source/drain structure 2211 and 2221. The single LDD structure 224 has a first side face adjacent to a first structure of the source/drain structure and a second side face essentially separated from a second structure of the source/drain structure by a semiconductor material 223. The other thin film transistor having a first LDD structure and a second LDD structure which is adjacent to the first LDD structure is also provided. Manufacturing processes of such thin film transistors are disclosed. <P>COPYRIGHT: (C)2004,JPO

Description

　本発明は、薄膜トランジスタに関し、さらに詳しくは、そのＬＤＤ（Lightly Doped Drain）構造に関する。また、本発明は、そのような薄膜トランジスタのＬＤＤ構造を製造する方法に関する。 The present invention relates to a thin film transistor, and more particularly, to an LDD (Lightly Doped Drain) structure thereof. The invention also relates to a method for manufacturing such a thin film transistor LDD structure.

　集積回路の開発進歩にともない、電子デバイスの小型化が進められている。薄膜トランジスタ（ＴＦＴ）は、よく知られているように、ＴＦＴ液晶ディスプレイ（ＴＦＴ−ＬＣＤ）の画素制御のための基本デバイスとして広く用いられている。小型化の結果、各ＴＦＴのソースとドレイン間のチャネルが、さらに狭くなっていく。そこで、ショートチャネル現象が発生し易くなる。このようなショートチャネル現象は、ゲート電圧がゼロの場合であっても、意図しないＴＦＴのオン状態を発生させるおそれがある。従って、トランジスタのスイッチ機能が損なわれてしまう。また、チャネルにおける電界強度は、チャネルが狭いため増加する。そこで、ドレイン近傍におけるホットエレクトロンは、半導体のエネルギギャップと比べてより高いエネルギを有することになる。価電子帯の電子は、ホットエレクトロンに衝突されて伝導帯に押し上げられ、このことによって、多くの電子−ホール対が生成される。このような現象は、ホットエレクトロン効果と呼ばれている。 電子 With the development of integrated circuits, electronic devices are being miniaturized. As is well known, a thin film transistor (TFT) is widely used as a basic device for controlling pixels of a TFT liquid crystal display (TFT-LCD). As a result of the miniaturization, the channel between the source and the drain of each TFT is further narrowed. Therefore, the short channel phenomenon easily occurs. Such a short channel phenomenon may cause an unintended ON state of the TFT even when the gate voltage is zero. Therefore, the switching function of the transistor is impaired. The electric field strength in the channel increases because the channel is narrow. Therefore, the hot electrons near the drain have higher energy than the energy gap of the semiconductor. The electrons in the valence band are bombarded by hot electrons and are pushed up into the conduction band, thereby generating many electron-hole pairs. Such a phenomenon is called a hot electron effect.

　ＴＦＴ−ＬＣＤにおいて、ＴＦＴは主にガラス基板上に形成される。ガラス基板は、一般的に熱に弱く、ＬＣＤガラス板の上にＴＦＴを形成するプロセスは、低温工程によらなければならない。ホットッレクトロン効果を最小とするために、ＬＤＤ（Lightly Doped Drain）構造を有する低温ポリシリコン薄膜トランジスタ（ＬＴＰＳ−ＴＦＴ）が開発された。このようなＬＴＰＳ−ＴＦＴの中でも、ゲートとドレインがオーバラップしたＬＤＤ（gate-drain overlapped LDD； ＧＯ−ＬＤＤ）構造が広く用いられている。 ＴＦＴ In a TFT-LCD, a TFT is mainly formed on a glass substrate. Glass substrates are generally sensitive to heat, and the process of forming TFTs on LCD glass plates must rely on low temperature steps. To minimize the hot-lectron effect, a low-temperature polysilicon thin film transistor (LTPS-TFT) having an LDD (Lightly Doped Drain) structure has been developed. Among such LTPS-TFTs, a gate-drain overlapped LDD (GO-LDD) structure in which a gate and a drain overlap is widely used.

　Ｎ型ＬＴＰＳ−ＴＦＴの製造工程が、図１（ａ）〜１（ｇ）に示されている。図１（ａ）において、シリコン酸化膜緩衝層１１と真性アモルファスシリコン（intrinsic amorphous silicon；ｉ−ａ−Ｓｉ）層が、連続してガラス基板１０の上に形成される。そして、ｉ−ａ−Ｓｉ層が、レーザアニーリングによって真性ポリシリコン（intrinsic polysilicon；ｉ−ｐｏｌｙ−Ｓｉ）層１２に変えられる。そして、マイクロフォトリソグラフィとエッチング処理によって、ｉ−ｐｏｌｙ−Ｓｉ層１２が部分的にエッチングされて、図１（ｂ）に示すように、所望のポリシリコン構造１２０が形成される。図１（ｃ）に示すように、ポリシリコン構造１２０の上にフォトレジストが形成され、マスク１３が形成される。そして、イオン注入工程においてイオン注入が行われて、マスク１３に覆われていないポリシリコン構造１２の部分に２つのＮ型領域１２１，１２２が形成される。２つのＮ型領域１２１，１２２は、ＮチャネルＴＦＴのソース／ドレインとなる。フォトレジスト１３除去の後、図１（ｄ）に示すように、例えば二酸化膜シリコンによるゲート絶縁層１４が、図１（ｃ）に示す構造の上に形成される。 FIGS. 1 (a) to 1 (g) show a manufacturing process of an N-type LTPS-TFT. In FIG. 1A, a silicon oxide film buffer layer 11 and an intrinsic amorphous silicon (ia-Si) layer are continuously formed on a glass substrate 10. Then, the ia-Si layer is changed to an intrinsic polysilicon (i-poly-Si) layer 12 by laser annealing. Then, the i-poly-Si layer 12 is partially etched by microphotolithography and etching to form a desired polysilicon structure 120 as shown in FIG. 1B. As shown in FIG. 1C, a photoresist is formed on the polysilicon structure 120, and a mask 13 is formed. Then, ion implantation is performed in the ion implantation step, and two N-type regions 121 and 122 are formed in portions of the polysilicon structure 12 not covered by the mask 13. The two N-type regions 121 and 122 serve as the source / drain of the N-channel TFT. After the removal of the photoresist 13, as shown in FIG. 1D, a gate insulating layer 14 of, for example, silicon dioxide is formed on the structure shown in FIG. 1C.

　図１（ｅ）に示すように、図１（ｄ）に示す構造の上にゲート用導電層をスパッタリング成膜し、パターニングを行って、ゲート絶縁層１４の上にゲート電極１５が形成される。そして、ポリシリコン構造１２０に微量のＮ型ドーパントを供給するためのマスクとしてゲート電極１５を用いて、低濃度イオン注入を行い、２つのＬＤＤ領域１２３，１２４が、それぞれソース／ドレイン領域１２１，１２２に近接して形成される。図１（ｆ）に示すように、層間の誘電体層１７が、図１（ｅ）に示す構造の上に形成される。そして、必要な個数のコンタクトホール１８がゲート電極とソース／ドレイン領域に向けて形成される。そして、図１（ｇ）に示すように、図１（ｆ）に示す構造の上に導電体層がスパッタリング成膜され、コンタクトホールが埋められ、ゲート配線１９０とソース／ドレイン配線１９１がパターニングされて形成される。 As shown in FIG. 1E, a gate conductive layer is formed by sputtering on the structure shown in FIG. 1D and patterned to form a gate electrode 15 on the gate insulating layer 14. . Then, low-concentration ion implantation is performed using the gate electrode 15 as a mask for supplying a small amount of N-type dopant to the polysilicon structure 120, and the two LDD regions 123 and 124 are formed in the source / drain regions 121 and 122 respectively. Formed in the vicinity of As shown in FIG. 1F, an interlayer dielectric layer 17 is formed on the structure shown in FIG. 1E. Then, a required number of contact holes 18 are formed toward the gate electrode and the source / drain regions. Then, as shown in FIG. 1G, a conductor layer is formed by sputtering on the structure shown in FIG. 1F, the contact holes are filled, and the gate wiring 190 and the source / drain wiring 191 are patterned. Formed.

　ゲートとドレインがオーバラップしたＬＤＤ（ＧＯ−ＬＤＤ）構造は、ドレイン領域の近傍で電界強度を下げることになり、ホットエレクトロンの効果の影響をわずかに下げることになる。 (4) In the LDD (GO-LDD) structure in which the gate and the drain overlap, the electric field intensity is reduced in the vicinity of the drain region, and the effect of the hot electron effect is slightly reduced.

　しかしながら、高分解能ディスプレイの要求の増加によって、回路は、従来以上にさらに複雑になっている。すなわち、電子デバイスの数は、個々の電子デバイスの占める空間を減らさなければならないほど増加している。従って、トランジスタのチャネルはさらに狭くなっていく。また、ＬＤＤ領域はチャネルをさらに短くしており、ソース／ドレイン領域近傍の欠乏層領域は接近して、互いに接触しそうなほどである。そのため、上述した図１に示されるようなＬＤＤ構造を有する薄膜トランジスタにおいては、電子デバイスを劣化させる電流リークとパンチスルーの問題が発生する可能性がある。上記の現象は小型化への開発にとって重要な問題である。 However, with the increasing demand for high resolution displays, circuits have become more complex than ever. That is, the number of electronic devices is increasing so that the space occupied by individual electronic devices must be reduced. Therefore, the channel of the transistor becomes narrower. Further, the LDD region has a shorter channel, and the depletion layer regions near the source / drain regions are close to each other and almost in contact with each other. Therefore, in the thin film transistor having the LDD structure as shown in FIG. 1 described above, there is a possibility that a problem of a current leak and a punch-through that deteriorates an electronic device may occur. The above phenomena are important issues for miniaturization development.

　本発明は、上記課題を解消するものであって、ホットエレクトロン、電流リーク、及びパンチスルーを低減させた薄膜トランジスタを提供することを目的とする。また、ホットエレクトロン、電流リーク、及びパンチスルーを低減させるＬＤＤ構造を有する薄膜トランジスタの製造方法を提供することを目的とする。 The object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a thin film transistor in which hot electrons, current leak, and punch-through are reduced. Another object is to provide a method for manufacturing a thin film transistor having an LDD structure that reduces hot electrons, current leakage, and punch-through.

　上記課題を達成するために、本発明は、薄膜トランジスタであって、半導体物質で形成された半導体層と、ソース／ドレイン構造と、ＬＤＤ構造と、ゲート構造と、絶縁層とを備えている。半導体層は、多結晶シリコンのような半導体物質によって、ガラス基板上に形成されている。ソース構造とドレイン構造が互いに離れて半導体層の中にソース／ドレイン構造として形成されている。単一ＬＤＤ構造は、ソース／ドレイン構造の間に配置され、ソース／ドレイン構造の第１の構造に隣接した第１の側面と、ソース／ドレイン構造の第２の構造に対して本質的に半導体物質で隔てられた第２の側面とを有している。絶縁層は、半導体層とゲート構造の間に配置され、ゲート構造をソース／ドレイン構造とＬＤＤ構造から絶縁している。 In order to achieve the above object, the present invention is a thin film transistor, which includes a semiconductor layer formed of a semiconductor material, a source / drain structure, an LDD structure, a gate structure, and an insulating layer. The semiconductor layer is formed on a glass substrate using a semiconductor material such as polycrystalline silicon. A source structure and a drain structure are formed as a source / drain structure in a semiconductor layer apart from each other. The single LDD structure is disposed between the source / drain structure and is substantially semiconductor with respect to a first side adjacent to the first structure of the source / drain structure and to a second structure of the source / drain structure. A second side separated by a substance. The insulating layer is disposed between the semiconductor layer and the gate structure, and insulates the gate structure from the source / drain structure and the LDD structure.

　本発明の一実施形態において、単一ＬＤＤ構造は、ゲートとドレインが重なりを有するＬＤＤ（ＧＯ−ＬＤＤ）である。ソース／ドレイン構造の第１の構造がドレイン構造であり、ソース／ドレイン構造の第２の構造がソース構造である。 In one embodiment of the present invention, the single LDD structure is an LDD (GO-LDD) having a gate and a drain overlapping. The first structure of the source / drain structure is a drain structure, and the second structure of the source / drain structure is a source structure.

　本発明の他の一実施形態において、薄膜トランジスタがＮ型であり、前記ＬＤＤ構造がＰイオン、Ａｓイオン、ＰＨｘイオン、ＡｓＨｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでいる。 In another embodiment of the present invention, the thin film transistor is N-type, and the LDD structure includes a doping material selected from P ions, As ions, PH x ions, AsH x ions, and combinations thereof. I have.

　また、本発明は、薄膜トランジスタであって、半導体層と、ソース構造とドレイン構造とからなるソース／ドレイン構造と、第１のＬＤＤ構造と、第２のＬＤＤ構造と、ゲート構造と、絶縁層とを備えている。半導体層は、半導体物質で形成されている。ソース／ドレイン構造の各構造は、互いに離れて半導体層に形成されている。第１のＬＤＤ構造は、ソース／ドレイン構造の間に配置され、そのソース／ドレイン構造の第１の構造に隣接した第１の側面と、その第１の側面の反対側に第２の側面を有している。第２のＬＤＤ構造は、第１のＬＤＤ構造の第２の側面に隣接した第３の側面と、ソース／ドレイン構造の第２の構造に対して本質的に前記半導体物質で隔てられた第４の側面とを有している。ゲート構造は、半導体層の上方に形成されている。絶縁層は、半導体層とゲート構造の間に配置され、ゲート構造をソース／ドレイン構造及びＬＤＤ構造から絶縁している。 Further, the present invention is a thin film transistor, including a semiconductor layer, a source / drain structure including a source structure and a drain structure, a first LDD structure, a second LDD structure, a gate structure, and an insulating layer. It has. The semiconductor layer is formed of a semiconductor material. Each structure of the source / drain structure is formed in the semiconductor layer apart from each other. The first LDD structure is disposed between the source / drain structures and has a first side adjacent to the first structure of the source / drain structure and a second side opposite the first side. Have. The second LDD structure includes a third side adjacent to the second side of the first LDD structure and a fourth side separated by the semiconductor material with respect to the second structure of the source / drain structure. Side. The gate structure is formed above the semiconductor layer. The insulating layer is disposed between the semiconductor layer and the gate structure, and insulates the gate structure from the source / drain structure and the LDD structure.

　本発明の一実施形態において、第１及び第２の各ＬＤＤ構造は、ゲートとドレインが重なりを有するＬＤＤ（ＧＯ−ＬＤＤ）である。また、薄膜トランジスタはＮ型であり、第１のＬＤＤ構造はＰイオン、Ａｓイオン、ＰＨｘイオン、ＡｓＨｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでおり、第２のＬＤＤ構造はＢイオン、ＢＨｘイオン、Ｂ２Ｈｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでいる。 In one embodiment of the present invention, each of the first and second LDD structures is an LDD (GO-LDD) having a gate and a drain overlapping. In addition, the thin film transistor is N-type, the first LDD structure includes a doping material selected from P ions, As ions, PH x ions, AsH x ions, and a combination thereof, and the second LDD structure includes The structure includes a doping material selected from B ions, BH x ions, B 2 H x ions, and combinations thereof.

　本発明の他の一実施形態において、薄膜トランジスタは、第３のＬＤＤ構造と第４のＬＤＤ構造とをさらに備えている。第３のＬＤＤ構造は、ソース／ドレイン構造の間に配置され、そのソース／ドレイン構造の第２の構造に隣接した第５の側面と、その第５の側面の反対側に第６の側面を有している。第４のＬＤＤ構造は、第３のＬＤＤ構造の第６の側面に隣接した第７の側面と、第２のＬＤＤ構造に対して本質的に前記半導体物質で隔てられた第８の側面とを有している。第３のＬＤＤ構造はＰイオン、Ａｓイオン、ＰＨｘイオン、ＡｓＨｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでおり、第４のＬＤＤ構造はＢイオン、ＢＨｘイオン、Ｂ２Ｈｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでいる。 In another embodiment of the present invention, the thin film transistor further includes a third LDD structure and a fourth LDD structure. The third LDD structure is disposed between the source / drain structure and has a fifth side adjacent to the second structure of the source / drain structure and a sixth side opposite the fifth side. Have. The fourth LDD structure includes a seventh side adjacent to the sixth side of the third LDD structure and an eighth side essentially separated by the semiconductor material with respect to the second LDD structure. Have. The third LDD structure includes a doping material selected from P ions, As ions, PH x ions, AsH x ions, and combinations thereof, and the fourth LDD structure includes B ions, BH x ions, B 2 H x ions, and contains a doping material selected from among these combinations.

　本発明の他の一実施形態において、少なくとも第１及び第３のＬＤＤ構造の一部が、第２及び第４のＬＤＤ構造及びソース／ドレイン構造によって覆われていない。 In another embodiment of the present invention, at least a part of the first and third LDD structures is not covered by the second and fourth LDD structures and the source / drain structure.

　本発明の他の一実施形態において、第１のＬＤＤ構造が前記第２のＬＤＤ構造及びソース／ドレイン構造の第１の構造によって囲まれており、第３のＬＤＤ構造が第４のＬＤＤ構造及びソース／ドレイン構造の第２の構造によって囲まれている。 In another embodiment of the present invention, a first LDD structure is surrounded by a first of the second LDD structure and a source / drain structure, and a third LDD structure is a fourth LDD structure. It is surrounded by the second structure of the source / drain structure.

　また、本発明は、薄膜トランジスタの製造方法であって、以下の工程を備えている。ゲート絶縁層が半導体層の上に形成され、ゲート構造がゲート絶縁層の上に形成される。次に、ソース／ドレイン構造がチャネル領域で互いに隔てられて半導体層に形成される。次に、第１のＬＤＤ構造を形成するために、第１のドーピング物質が、チャネル領域の第１の端部に半導体層の表面から第１の角度の第１の方向で注入される。また、第１のＬＤＤ構造に接触している第２のＬＤＤ構造を形成するために、第２のドーピング物質が、チャネル領域の前記第１の端部に半導体層の表面から第２の角度の第２の方向で注入される。 The present invention is also a method of manufacturing a thin film transistor, and includes the following steps. A gate insulating layer is formed over the semiconductor layer, and a gate structure is formed over the gate insulating layer. Next, source / drain structures are formed in the semiconductor layer separated from each other by a channel region. Next, a first doping material is implanted into the first end of the channel region at a first angle at a first angle from the surface of the semiconductor layer to form a first LDD structure. Also, a second doping material is applied to the first end of the channel region at a second angle from the surface of the semiconductor layer to form a second LDD structure in contact with the first LDD structure. Injected in a second direction.

　本発明の一実施形態において、第１のドーピング物質は、Ｐイオン、Ａｓイオン、ＰＨｘイオン、ＡｓＨｘイオン、及びこれらの組合せの中から選択され、第２のドーピング物質は、Ｂイオン、ＢＨｘイオン、Ｂ２Ｈｘイオン、及びこれらの組合せの中から選択される。 In one embodiment of the present invention, the first doping material is selected from P ions, As ions, PH x ions, AsH x ions, and combinations thereof, and the second doping material is B ions, BH ions. x ions, B 2 H x ions, and combinations thereof.

　本発明の他の一実施形態において、第１のドーピング物質を注入する工程が、ゲート構造をマスクとして用いてチャネルに対して行われ、また、第３のＬＤＤ構造が、第１のＬＤＤ構造が形成される時、チャネル領域における第１の端部の反対側の第２の端部に同時に形成される。 In another embodiment of the present invention, the step of injecting the first doping material is performed on the channel using the gate structure as a mask, and the third LDD structure is the first LDD structure. When formed, they are formed simultaneously at a second end of the channel region opposite the first end.

　本発明の他の一実施形態において、薄膜トランジスタの製造方法は、第３のＬＤＤ構造に接触している第４のＬＤＤ構造を形成するために、半導体層の表面から第３の角度の第３の方向でチャネル領域の第２の端部に第３のドーピング物質を注入する工程をさらに備えている。 In another embodiment of the present invention, a method of fabricating a thin film transistor includes forming a third LDD structure in contact with a third LDD structure to form a third LDD structure at a third angle from a surface of the semiconductor layer. Implanting a third doping material into the second end of the channel region in the direction.

　好ましくは、第１の角度は実質的に９０゜であり、第２、及び第３の各角度は０゜より大きく３０゜より小さい。 {Preferably, the first angle is substantially 90 °, and each of the second and third angles is greater than 0 ° and less than 30 °.

　好ましくは、第３のドーピング物質は、第２のドーピング物質と同じものである。 Preferably, the third doping substance is the same as the second doping substance.

　本発明の他の一実施形態において、ゲート構造は、ゲート電極とその電極のそばのスペーサ構造を含み、第１のドーピング物質を注入する工程は、前記スペーサ構造が除去されてから行われる。 In another embodiment of the present invention, the gate structure includes a gate electrode and a spacer structure near the electrode, and the step of injecting the first doping material is performed after the spacer structure is removed.

　以下、本発明の一実施形態に係る薄膜トランジスタのＬＤＤ構造とその製造方法について、図面を参照して説明する。本発明は、ソース／ドレイン領域の近傍における欠乏層領域の接触可能性を防止する目的で、ソース／ドレイン欠乏層領域が、従来例と異なり互いに接近しないような単一ＬＤＤ構造を有するＴＦＴを提供する。このようなＴＦＴの２つの例とその製造工程を、図２（ａ）〜２（ｆ）、図図３（ａ）〜３（ｆ）に示す。 Hereinafter, an LDD structure of a thin film transistor according to an embodiment of the present invention and a manufacturing method thereof will be described with reference to the drawings. The present invention provides a TFT having a single LDD structure in which the source / drain depletion layer regions do not approach each other unlike the conventional example in order to prevent the possibility of contact between the depletion layer regions near the source / drain regions. I do. FIGS. 2 (a) to 2 (f) and FIGS. 3 (a) to 3 (f) show two examples of such a TFT and the manufacturing process thereof.

　図２（ａ）に示すように、バッファ（緩衝）層２１がガラス基板２０の上に形成される。続いて、真性アモルファスシリコン（ｉ−ａ−Ｓｉ）層がバッファ層２１の上に形成され、ｉ−ａ−Ｓｉ層がレーザアニーリングによって真性ポリシリコン（ｉ−ｐｏｌｙ−Ｓｉ）層２２に変換される。フォトレジスト層がポリシリコン層２２の上に形成され、図２（ｂ）に示すように、マイクロフォトリソグラフィとエッチングの工程によってマスク２３が形成される。また、図２（ｂ）に示すように、このマスク２３から露出したポリシリコン層２２の部位に、Ｎ型のイオン注入を行う工程によって、２つのＮ型領域２２１，２２２が形成される。２つのＮ型領域２２１，２２２は互いにチャネル領域２２３によって隔てられている。次に、図２（ｃ）に示すように、フォトレジストマスク２３が除去される。 (2) As shown in FIG. 2A, a buffer (buffer) layer 21 is formed on the glass substrate 20. Subsequently, an intrinsic amorphous silicon (ia-Si) layer is formed on the buffer layer 21, and the ia-Si layer is converted into an intrinsic polysilicon (i-poly-Si) layer 22 by laser annealing. . A photoresist layer is formed on the polysilicon layer 22, and a mask 23 is formed by microphotolithography and etching steps as shown in FIG. Further, as shown in FIG. 2B, two N-type regions 221 and 222 are formed in the portion of the polysilicon layer 22 exposed from the mask 23 by performing N-type ion implantation. The two N-type regions 221 and 222 are separated from each other by a channel region 223. Next, as shown in FIG. 2C, the photoresist mask 23 is removed.

　図２（ｄ）に示すように、図２（ｃ）に示す構造の上にゲート絶縁層２５が形成される。図２（ｅ）に示すように、チャネル２２３よりもわずかに幅の狭いゲート電極２６が、チャネル領域２２３の端部がゲート電極２６によって覆われずに露出するように、ゲート絶縁層２５の上にパターニングとエッチングの工程によって形成される。そして、ゲート電極２６をマスクとして、低濃度イオン注入が行われ、マスクから露出したポリシリコン層２２の部位に低濃度のＮ型ドーパントが供給されて、単一ＬＤＤ構造２２４がポリシリコン層２２に形成される。図２（ｆ）に示すように、Ｎ型領域２２１，２２２は、結果的に高濃度に不純物注入がなされ、ソース／ドレイン領域２２１１，２２２１が形成される。その後、層関誘電体層、コンタクトホール、ゲートとソース／ドレインの配線、及びその他の必要な構造が図２（ｆ）に示す構造の上に形成され、ＴＦＴが完成される。 (2) As shown in FIG. 2 (d), a gate insulating layer 25 is formed on the structure shown in FIG. 2 (c). As shown in FIG. 2E, the gate electrode 26 slightly narrower than the channel 223 is formed on the gate insulating layer 25 so that the end of the channel region 223 is exposed without being covered by the gate electrode 26. Is formed by a patterning and etching process. Then, low concentration ion implantation is performed using the gate electrode 26 as a mask, and a low concentration N-type dopant is supplied to the portion of the polysilicon layer 22 exposed from the mask, so that the single LDD structure 224 is added to the polysilicon layer 22. It is formed. As shown in FIG. 2F, the N-type regions 221 and 222 are consequently implanted with a high concentration of impurities, so that source / drain regions 2211 and 221 are formed. Thereafter, a layer-related dielectric layer, contact holes, gate and source / drain wiring, and other necessary structures are formed on the structure shown in FIG. 2F, and the TFT is completed.

　単一ＬＤＤ構造を有するＴＦＴの製造工程の他の例を説明する。まず、図３（ａ）に示すように、バッファ層３１がガラス基板３０の上に形成される。続いて、真性アモルファスシリコン（ｉ−ａ−Ｓｉ）層がバッファ層３１の上に形成され、ｉ−ａ−Ｓｉ層がレーザアニーリングによって真性ポリシリコン（ｉ−ｐｏｌｙ−Ｓｉ）層３２に変換される。図３（ｂ）に示すように、ゲート絶縁層３３がポリシリコン層３２の上に形成され、そのゲート絶縁層３３の上にゲート構造３４がパターニングされる。さらに、図３（ｃ）に示すように、誘電体層が図３（ｂ）に示す構造の上に形成され、スペーサ又は側壁３５がゲート構造３４の横にマイクロフォトリソグラフィとエッチングの工程によって形成される。ゲート電極３４とその横のスペーサ／側壁３５は、その後のＮ型イオン注入工程におけるドーピングのマスクとして用いられる。 Another example of the manufacturing process of the TFT having the single LDD structure will be described. First, as shown in FIG. 3A, a buffer layer 31 is formed on a glass substrate 30. Subsequently, an intrinsic amorphous silicon (ia-Si) layer is formed on the buffer layer 31, and the ia-Si layer is converted into an intrinsic polysilicon (i-poly-Si) layer 32 by laser annealing. . As shown in FIG. 3B, a gate insulating layer 33 is formed on the polysilicon layer 32, and a gate structure 34 is patterned on the gate insulating layer 33. Further, as shown in FIG. 3 (c), a dielectric layer is formed on the structure shown in FIG. 3 (b), and spacers or sidewalls 35 are formed next to the gate structure 34 by microphotolithography and etching steps. Is done. The gate electrode 34 and the spacer / sidewall 35 beside it are used as a doping mask in a subsequent N-type ion implantation step.

　図３（ｄ）に示すように、マスクから露出したポリシリコン層３２の部位に、２つのＮ型領域３２１，３２２が形成される。２つのＮ型領域３２１，３２２はチャネル領域３２３によって互いに隔てられている。図３（ｅ）に示すように、Ｎ型領域３２２に隣接する部位のスペーサ３５が取り除かれ、チャネル領域３２３の端部が露出される。図３（ｆ）に示すように、ゲート電極３４と残っているスペーサ３５をマスクとして、低濃度イオン注入が行われ、マスクから露出したポリシリコン層３２の部位に低濃度のＮ型ドーパントが供給されて、単一ＬＤＤ構造３２４がポリシリコン層３２に形成される。Ｎ型領域は同時に高濃度に不純物注入がなされ、ソース／ドレイン領域３２１１，３２２１が形成される。その後、前述の実施形態と同様の必要な工程が行われる。 よ う As shown in FIG. 3D, two N-type regions 321 and 322 are formed in the portion of the polysilicon layer 32 exposed from the mask. The two N-type regions 321 and 322 are separated from each other by a channel region 323. As shown in FIG. 3E, the spacer 35 at a portion adjacent to the N-type region 322 is removed, and the end of the channel region 323 is exposed. As shown in FIG. 3F, low concentration ion implantation is performed using the gate electrode 34 and the remaining spacer 35 as a mask, and a low concentration N-type dopant is supplied to the portion of the polysilicon layer 32 exposed from the mask. As a result, a single LDD structure 324 is formed in the polysilicon layer 32. Impurity implantation is simultaneously performed on the N-type region at a high concentration, so that source / drain regions 3211 and 3221 are formed. Thereafter, necessary steps similar to those of the above-described embodiment are performed.

　上述したそれぞれのＴＦＴは単一ＬＤＤ構造を有するので、ソース／ドレインの近傍の欠乏層領域間の距離は、２つのＬＤＤ構造を有するものと比べて、幾分増加している。そこで、従来例におけるホットエレクトロン、電流リーク、及びパンチスルーの影響がかなり低減される。上述の製造工程は、特に、ドライバ回路、及びその他の応用回路において好適である。 (4) Since each of the above-described TFTs has a single LDD structure, the distance between the depletion layer regions near the source / drain is somewhat increased as compared with that having two LDD structures. Thus, the effects of hot electrons, current leakage, and punch-through in the conventional example are significantly reduced. The above manufacturing process is particularly suitable for driver circuits and other application circuits.

　画素ユニットに関して、ＴＦＴの動作モードに対応するために、本発明はＬＤＤ構造のそばにＰ型領域を追加して問題解決を図る。このようなＴＦＴを製造する工程が、図４（ａ）〜４（ｈ）、図５（ａ）〜５（ｈ）に示されている。 Regarding the pixel unit, in order to support the operation mode of the TFT, the present invention solves the problem by adding a P-type region near the LDD structure. The steps of manufacturing such a TFT are shown in FIGS. 4 (a) to 4 (h) and FIGS. 5 (a) to 5 (h).

　図４（ａ）に示すように、バッファ層４１がガラス基板４０の上に形成される。続いて、真性アモルファスシリコン（ｉ−ａ−Ｓｉ）層がバッファ層４１の上に形成され、ｉ−ａ−Ｓｉ層がレーザアニーリングによって真性ポリシリコン（ｉ−ｐｏｌｙ−Ｓｉ）層４２に変換される。図４（ｂ）に示すように、フォトレジスト層がポリシリコン層４２の上に形成され、マイクロフォトリソグラフィとエッチングの工程によってマスク４３が形成される。このマスク４３から露出したポリシリコン層４２の部位に、Ｎ型のイオン注入を行う工程によって、図４（ｃ）に示すように、２つのＮ型領域４２１，４２２が形成される。２つのＮ型領域４２１，４２２は互いにチャネル領域４２３によって隔てられている。その後、フォトレジストマスク４３が除去される。 4) As shown in FIG. 4A, the buffer layer 41 is formed on the glass substrate 40. Subsequently, an intrinsic amorphous silicon (ia-Si) layer is formed on the buffer layer 41, and the ia-Si layer is converted into an intrinsic polysilicon (i-poly-Si) layer 42 by laser annealing. . As shown in FIG. 4B, a photoresist layer is formed on the polysilicon layer 42, and a mask 43 is formed by a microphotolithography and etching process. As shown in FIG. 4C, two N-type regions 421 and 422 are formed in the portion of the polysilicon layer 42 exposed from the mask 43 by performing N-type ion implantation. The two N-type regions 421 and 422 are separated from each other by a channel region 423. After that, the photoresist mask 43 is removed.

　図４（ｄ）に示すように、図４（ｃ）に示す構造の上に、例えば二酸化シリコンによって、ゲート絶縁層４５が形成される。図４（ｅ）に示すように、チャネル４２３よりもわずかに幅の狭いゲート電極４６が、チャネル領域４２３の両端部がゲート電極４６によって覆われずに露出するように、ゲート絶縁層４５の上にパターニングとエッチングの工程によって形成される。そして、ゲート電極４６をマスクとして、低濃度イオン注入が行われ、マスクから露出したポリシリコン層４２の部位に低濃度のＮ型ドーパントが供給されて、図４（ｆ）に示すように、２つのＬＤＤ構造４２５，４２６がポリシリコン層４２に形成される。Ｎ型領域４２１，４２２は、結果的に高濃度に不純物注入がなされ、ソース／ドレイン領域４２１１，４２２１が形成される。 4) As shown in FIG. 4D, a gate insulating layer 45 is formed on the structure shown in FIG. As shown in FIG. 4E, the gate electrode 46 slightly narrower than the channel 423 is formed on the gate insulating layer 45 so that both ends of the channel region 423 are exposed without being covered by the gate electrode 46. Is formed by a patterning and etching process. Then, low-concentration ion implantation is performed using the gate electrode 46 as a mask, and a low-concentration N-type dopant is supplied to the portion of the polysilicon layer 42 exposed from the mask, as shown in FIG. Two LDD structures 425, 426 are formed in the polysilicon layer 42. As a result, impurities are implanted into the N-type regions 421 and 422 at a high concentration, and source / drain regions 4211 and 4221 are formed.

　さらに、ゲート電極４６をマスクとして、Ｐ型ドーピング物質をポリシリコン層４２に注入する２回のイオン注入工程が行われる。一回目は、図４（ｇ）に示すように、ポリシリコン層４２の表面４２０から第１の角度だけ傾いた方向Ａから行われ、２回目は、図４（ｈ）に示すように、ポリシリコン層４２の表面４２０から第２の角度だけ傾いた方向Ｂから行われる。左右に傾いた第１及び第２の角度の大きさは、例えば、同じ角度とすることができ、０゜から３０゜の間の値をとることができる。このようにして、Ｐ型ＬＤＤ領域４２７、４２８が２つのＬＤＤ構造４２５，４２６の直近に隣接して形成される。その後、前述の実施形態と同様に必要な工程が行われる。傾けたイオン注入により、ドーパントの濃度分布が漸近的に変化するので、チャネル領域とソース／ドレイン領域を結びつける欠乏層領域の幅が減少して電流リーク及びパンチスルーが低減するようになっている。 {Circle around (2)} Using the gate electrode 46 as a mask, two ion implantation steps of implanting a P-type doping material into the polysilicon layer 42 are performed. The first time is performed from a direction A inclined by a first angle from the surface 420 of the polysilicon layer 42 as shown in FIG. 4G, and the second time is performed as shown in FIG. This is performed from the direction B inclined by the second angle from the surface 420 of the silicon layer 42. The magnitude of the first and second angles inclined left and right can be, for example, the same angle and can take a value between 0 ° and 30 °. In this way, P-type LDD regions 427 and 428 are formed immediately adjacent to the two LDD structures 425 and 426. After that, necessary steps are performed as in the above-described embodiment. Since the concentration distribution of the dopant is asymptotically changed by the inclined ion implantation, the width of the depletion layer region connecting the channel region and the source / drain region is reduced, so that current leakage and punch-through are reduced.

　次に、ＴＦＴのさらに製造工程の他の例を説明する。このＴＦＴは二重層ＬＤＤ構造を有する。図５（ａ）に示すように、バッファ層５１がガラス基板５０の上に形成される。続いて、真性アモルファスシリコン（ｉ−ａ−Ｓｉ）層がバッファ層５１の上に形成され、ｉ−ａ−Ｓｉ層がレーザアニーリングによって真性ポリシリコン（ｉ−ｐｏｌｙ−Ｓｉ）層５２に変換される。図５（ｂ）に示すように、ゲート絶縁層５３がポリシリコン層５２の上に形成され、そのゲート絶縁層５３の上にゲート電極５４がパターニングされる。さらに、図５（ｃ）に示すように、誘電体層が図５（ｂ）に示す構造の上に形成され、その誘電体層からマイクロフォトリソグラフィとエッチングの工程によってパターン形成してゲート電極５４の横にスペーサ又は側壁５５が形成される。ゲート電極５４とその横のスペーサ／側壁５５は、図５（ｃ）に示すように、Ｎ型イオン注入工程におけるドーピングのマスクとして用いられる。 Next, another example of the manufacturing process of the TFT will be described. This TFT has a double layer LDD structure. As shown in FIG. 5A, a buffer layer 51 is formed on a glass substrate 50. Subsequently, an intrinsic amorphous silicon (ia-Si) layer is formed on the buffer layer 51, and the ia-Si layer is converted into an intrinsic polysilicon (i-poly-Si) layer 52 by laser annealing. . As shown in FIG. 5B, a gate insulating layer 53 is formed on the polysilicon layer 52, and a gate electrode 54 is patterned on the gate insulating layer 53. Further, as shown in FIG. 5C, a dielectric layer is formed on the structure shown in FIG. 5B, and a pattern is formed from the dielectric layer by a microphotolithography and etching process to form the gate electrode 54. Are formed next to the spacer or side wall 55. As shown in FIG. 5C, the gate electrode 54 and the spacer / side wall 55 beside it are used as a doping mask in the N-type ion implantation step.

　図５（ｄ）に示すように、マスクから露出したポリシリコン層５２の部位に、２つのＮ型領域５２１，５２２が形成される。２つのＮ型領域５２１，５２２はチャネル領域５２３によって互いに隔てられている。次に、図５（ｅ）に示すように、Ｎ型領域３２２に隣接する部位のスペーサ／側壁３５が完全に取り除かれ、チャネル領域５２３の両方の端部が露出される。ゲート電極５４をマスクとして、低濃度イオン注入が行われ、マスクから露出したポリシリコン層５２の部位に低濃度のＮ型ドーパントが供給されて、図５（ｆ）に示すように、２つのＬＤＤ構造５２５，５２６がポリシリコン層５２に形成される。 (5) As shown in FIG. 5 (d), two N-type regions 521 and 522 are formed in the portion of the polysilicon layer 52 exposed from the mask. The two N-type regions 521 and 522 are separated from each other by a channel region 523. Next, as shown in FIG. 5E, the spacer / sidewall 35 adjacent to the N-type region 322 is completely removed, and both ends of the channel region 523 are exposed. Using the gate electrode 54 as a mask, low-concentration ion implantation is performed, and a low-concentration N-type dopant is supplied to a portion of the polysilicon layer 52 exposed from the mask, thereby forming two LDDs as shown in FIG. Structures 525 and 526 are formed in the polysilicon layer 52.

　さらに、ゲート電極５４をマスクとして、Ｐ型ドーピング物質をポリシリコン層５２に注入する２回のイオン注入工程が行われる。一回目は、図５（ｇ）に示すように、ポリシリコン層５２の表面５２０から第１の角度だけ傾いた方向Ａから行われ、２回目は、図５（ｈ）に示すように、ポリシリコン層５２の表面５２０から第２の角度だけ傾いた方向Ｂから行われる。左右に傾いた第１及び第２の角度の大きさは、例えば、同じ角度とすることができ、０゜から３０゜の間の値をとることができる。このようにして、Ｐ型ＬＤＤ領域５２７、５２８が２つのＬＤＤ構造５２５，５２６の直近に隣接して形成される。この実施形態においては、Ｐ型領域５２５，５２６がＬＤＤ構造５２５，５２６を取り囲んでいる。その後、前述の実施形態と同様の引き続きの工程が、誘電体層、ゲート及びソース／ドレインの配線などを形成するために行われる。 {Circle around (2)} Using the gate electrode 54 as a mask, two ion implantation steps of implanting a P-type doping material into the polysilicon layer 52 are performed. The first time is performed from a direction A inclined by a first angle from the surface 520 of the polysilicon layer 52 as shown in FIG. 5 (g), and the second time is performed as shown in FIG. This is performed from a direction B inclined by a second angle from the surface 520 of the silicon layer 52. The magnitude of the first and second angles inclined left and right can be, for example, the same angle and can take a value between 0 ° and 30 °. In this way, P-type LDD regions 527 and 528 are formed immediately adjacent to the two LDD structures 525 and 526. In this embodiment, P-type regions 525, 526 surround LDD structures 525, 526. Thereafter, subsequent steps similar to those of the above-described embodiment are performed to form a dielectric layer, gate and source / drain wiring, and the like.

　上述のイオン注入工程は、例えば、イオンシャワ工程に替えても良い。上述した実施形態において、ゲート導電体は、クロムＣｒ、タングステンＷ、モリブデンＭｏ、タンタルＴａ、アアルミニウムＡｌ、又は銅Ｃｕのスパッタ成膜によって形成され、その厚みは約１００ｎｍである。バッファ層は、一般に約６００ｎｍの厚みを有し、窒化シリコン、二酸化シリコン、又はこれらの組合せであり、プラズマを用いた化学蒸着（ＰＥＣＶＤ）で形成される。層間誘電体層は一般に、約６００ｎｍの厚みを有し、二酸化シリコンであり、プラズマを用いた化学蒸着（ＰＥＣＶＤ）で形成される。ゲート絶縁層は、一般に、約１００ｎｍの厚みを有し、二酸化シリコンであり、プラズマを用いた化学蒸着（ＰＥＣＶＤ）で形成される。 The above-described ion implantation step may be replaced with, for example, an ion shower step. In the above-described embodiment, the gate conductor is formed by sputtering of chromium Cr, tungsten W, molybdenum Mo, tantalum Ta, aluminum aluminum, or copper Cu, and has a thickness of about 100 nm. The buffer layer typically has a thickness of about 600 nm, is silicon nitride, silicon dioxide, or a combination thereof, and is formed by plasma enhanced chemical vapor deposition (PECVD). The interlayer dielectric layer typically has a thickness of about 600 nm, is silicon dioxide, and is formed by plasma enhanced chemical vapor deposition (PECVD). The gate insulating layer typically has a thickness of about 100 nm, is silicon dioxide, and is formed by plasma enhanced chemical vapor deposition (PECVD).

　上述した実施形態において、約１００ｎｍの厚みのアモルファスシリコン層が、レーザアニーリング／結晶化工程によってポリシリコン層を形成するために用いられている。好ましくは、レーザアニーリング／結晶化工程の前に、アモルファスシリコン層は、高温炉において４００゜、３０分の脱水素処理を行うのがよい。レーザアニーリング／結晶化工程において、レーザアニーリング／結晶化工程を行うためのエネルギは、３５０ｍＪ／ｃｍ２で少なくとも１００ショット行うように選ばれる。 In the embodiment described above, an amorphous silicon layer having a thickness of about 100 nm is used for forming a polysilicon layer by a laser annealing / crystallization process. Preferably, before the laser annealing / crystallization step, the amorphous silicon layer is subjected to a dehydrogenation treatment at 400 ° C. for 30 minutes in a high-temperature furnace. In the laser annealing / crystallization step, the energy for performing the laser annealing / crystallization step is selected to perform at least 100 shots at 350 mJ / cm 2 .

　さらに、上述のイオン注入工程においてドーパントの濃度は、Ｎ型ドーパントについては１×１０１４〜２×１０１５ｃｍ−２であり、Ｐ型ドーパントについては約１×１０１２である。Ｐ型ドーパントは、Ｂイオン、ＢＨｘイオン、Ｂ２Ｈｘイオン、及びこれらの組合せの中から選択できる。また、Ｎ型ドーパントは、Ｐイオン、Ａｓイオン、ＰＨｘイオン、ＡｓＨｘイオン、及びこれらの組合せの中から選択できる。コンタクトホールは、反応性エッチッグ工程によって形成される。 Further, in the above-described ion implantation process, the concentration of the dopant is 1 × 10 14 to 2 × 10 15 cm −2 for the N-type dopant and about 1 × 10 12 for the P-type dopant. The P-type dopant can be selected from B ions, BH x ions, B 2 H x ions, and combinations thereof. Further, N-type dopant, P ions, As ions, PH x ions, AsH x ions, and can be selected from among these combinations. The contact hole is formed by a reactive etching process.

　現状において、最も実際的で好ましい実施形態によって本発明が説明されているが、本発明は、上記に開示した実施形態に限定されるものではない。種々の変形、及び同様の構成が、そのような変形と同様の構造の全てを含むように広く解釈される。 At present, the present invention has been described by the most practical and preferred embodiments, but the present invention is not limited to the embodiments disclosed above. Various modifications and similar arrangements are to be interpreted broadly to include all such and similar structures.

従来のＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。Sectional drawing which shows notionally the manufacturing process of the TFT which has the conventional LDD structure. 従来のＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。Sectional drawing which shows notionally the manufacturing process of the TFT which has the conventional LDD structure. 従来のＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。Sectional drawing which shows notionally the manufacturing process of the TFT which has the conventional LDD structure. 従来のＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。Sectional drawing which shows notionally the manufacturing process of the TFT which has the conventional LDD structure. 従来のＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。Sectional drawing which shows notionally the manufacturing process of the TFT which has the conventional LDD structure. 従来のＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。Sectional drawing which shows notionally the manufacturing process of the TFT which has the conventional LDD structure. 従来のＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。Sectional drawing which shows notionally the manufacturing process of the TFT which has the conventional LDD structure. 本発明の一実施形態に係る、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 3 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure according to one embodiment of the present invention. 本発明の一実施形態に係る、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 3 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure according to one embodiment of the present invention. 本発明の一実施形態に係る、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 3 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure according to one embodiment of the present invention. 本発明の一実施形態に係る、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 3 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure according to one embodiment of the present invention. 本発明の一実施形態に係る、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 3 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure according to one embodiment of the present invention. 本発明の一実施形態に係る、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 3 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure according to one embodiment of the present invention. 本発明の一実施形態に係る他の例である、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 4 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure, which is another example according to one embodiment of the present invention. 本発明の一実施形態に係る他の例である、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 4 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure, which is another example according to one embodiment of the present invention. 本発明の一実施形態に係る他の例である、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 4 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure, which is another example according to one embodiment of the present invention. 本発明の一実施形態に係る他の例である、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 4 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure, which is another example according to one embodiment of the present invention. 本発明の一実施形態に係る他の例である、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 4 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure, which is another example according to one embodiment of the present invention. 本発明の一実施形態に係る他の例である、単一ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 4 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a single LDD structure, which is another example according to one embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention. 本発明の一実施形態に係るさらに他の例である、二重層ＬＤＤ構造を有するＴＦＴの製造工程を概念的に示す断面図。FIG. 9 is a cross-sectional view conceptually showing a manufacturing process of a TFT having a double-layer LDD structure, which is still another example according to an embodiment of the present invention.

符号の説明Explanation of reference numerals

　２２，３２，４２，５２　半導体層
　２５，３３，４５，５３　　絶縁層
　２６，３４，４６　　ゲート構造
　３５，５５　　スペーサ構造
　２２１，２２２，３２１，３２２，４２１，４２２，５２１，５２２　　ソース／ドレイン構造
　２２３，３２３，４２３，５２３　　チャンネル領域
　２２４，３２４　　単一ＬＤＤ構造
　４２５，４２６，４２７，４２８，５２５，５２６，５２７，５２８　　ＬＤＤ構造
22, 32, 42, 52 Semiconductor layer 25, 33, 45, 53 Insulating layer 26, 34, 46 Gate structure 35, 55 Spacer structure 221, 222, 321, 322, 421, 422, 521, 522 Source / drain structure 223 , 323, 423, 523 Channel region 224, 324 Single LDD structure 425, 426, 427, 428, 525, 526, 527, 528 LDD structure

Claims (14)

　薄膜トランジスタであって、
　半導体物質で形成された半導体層と、
　前記半導体層において互いに離れて形成されたソース構造及びドレイン構造からなるソース／ドレイン構造と、
　前記ソース／ドレイン構造の間に配置され、そのソース／ドレイン構造の第１の構造に隣接した側面と、そのソース／ドレイン構造の第２の構造に対して本質的に前記半導体物質で隔てられた側面とを有する単一ＬＤＤ構造と、
　前記半導体層の上方に形成されたゲート構造と、
　前記半導体層とゲート構造の間に配置されゲート構造を前記ソース／ドレイン構造及びＬＤＤ構造から絶縁する絶縁層と、を備えていることを特徴とする薄膜トランジスタ。 A thin film transistor,
A semiconductor layer formed of a semiconductor material;
A source / drain structure including a source structure and a drain structure formed apart from each other in the semiconductor layer;
A source / drain structure disposed between and adjacent to a first side of the source / drain structure adjacent the first structure and essentially separated by the semiconductor material from a second side of the source / drain structure; A single LDD structure having side surfaces;
A gate structure formed above the semiconductor layer;
An insulating layer disposed between the semiconductor layer and the gate structure to insulate the gate structure from the source / drain structure and the LDD structure. 　前記単一ＬＤＤ構造が、ゲートとドレインが重なりを有するＬＤＤ（ＧＯ−ＬＤＤ）である請求項１に記載の薄膜トランジスタ。 The thin film transistor according to claim 1, wherein the single LDD structure is an LDD (GO-LDD) having a gate and a drain overlapping. 　前記ソース／ドレイン構造の第１の構造がドレイン構造であり、前記ソース／ドレイン構造の第２の構造がソース構造である請求項１に記載の薄膜トランジスタ。 2. The thin film transistor according to claim 1, wherein the first structure of the source / drain structure is a drain structure, and the second structure of the source / drain structure is a source structure. 　前記薄膜トランジスタがＮ型であり、前記ＬＤＤ構造がＰイオン、Ａｓイオン、ＰＨｘイオン、ＡｓＨｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでいる請求項１に記載の薄膜トランジスタ。 The thin film transistor is an N type, the LDD structure P ions, As ions, PH x ions, AsH x ions, and a thin film transistor according to claim 1 which contains a doping material selected from among these combinations. 　薄膜トランジスタであって、
　半導体物質で形成された半導体層と、
　前記半導体層において互いに離れて形成されたソース構造及びドレイン構造からなるソース／ドレイン構造と、
　前記ソース／ドレイン構造の間に配置され、そのソース／ドレイン構造の第１の構造に隣接した第１の側面と、その第１の側面の反対側に第２の側面を有する第１のＬＤＤ構造と、
　前記第１のＬＤＤ構造の前記第２の側面に隣接した第３の側面と、前記ソース／ドレイン構造の第２の構造に対して本質的に前記半導体物質で隔てられた第４の側面とを有する第２のＬＤＤ構造と、
　前記半導体層の上方に形成されたゲート構造と、
　前記半導体層とゲート構造の間に配置されゲート構造を前記ソース／ドレイン構造及びＬＤＤ構造から絶縁する絶縁層と、を備えていることを特徴とする薄膜トランジスタ。 A thin film transistor,
A semiconductor layer formed of a semiconductor material;
A source / drain structure including a source structure and a drain structure formed apart from each other in the semiconductor layer;
A first LDD structure disposed between the source / drain structures and having a first side surface adjacent to the first structure of the source / drain structure and a second side surface opposite the first side surface; When,
A third side of the first LDD structure adjacent to the second side and a fourth side of the source / drain structure substantially separated from the second material by the semiconductor material. A second LDD structure having:
A gate structure formed above the semiconductor layer;
An insulating layer disposed between the semiconductor layer and the gate structure to insulate the gate structure from the source / drain structure and the LDD structure. 　前記第１及び第２のＬＤＤ構造が、ゲートとドレインが重なりを有するＬＤＤ（ＧＯ−ＬＤＤ）である請求項５に記載の薄膜トランジスタ。 The thin film transistor according to claim 5, wherein the first and second LDD structures are LDDs (GO-LDDs) having a gate and a drain overlapping. 　前記薄膜トランジスタがＮ型であり、前記第１のＬＤＤ構造がＰイオン、Ａｓイオン、ＰＨｘイオン、ＡｓＨｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでおり、前記第２のＬＤＤ構造がＢイオン、ＢＨｘイオン、Ｂ２Ｈｘイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでいる請求項５に記載の薄膜トランジスタ。 The thin film transistor is N-type, the first LDD structure includes a doping material selected from P ions, As ions, PH x ions, AsH x ions, and a combination thereof; LDD structure B ions, BH x ion, B 2 H x ions and a thin film transistor according to claim 5 which contains a doping material selected from among these combinations. 　前記ソース／ドレイン構造の間に配置され、そのソース／ドレイン構造の第２の構造に隣接した第５の側面と、その第５の側面の反対側に第６の側面を有する第３のＬＤＤ構造と、
　前記第３のＬＤＤ構造の前記第６の側面に隣接した第７の側面と、前記ソース／ドレイン構造の第２の構造に対して本質的に前記半導体物質で隔てられた第８の側面とを有する第４のＬＤＤ構造と、をさらに備えた請求項５に記載の薄膜トランジスタ。 A third LDD structure disposed between the source / drain structure and having a fifth side adjacent to a second structure of the source / drain structure and a sixth side opposite the fifth side; When,
A seventh side adjacent to the sixth side of the third LDD structure and an eighth side essentially separated by the semiconductor material relative to the second structure of the source / drain structure. The thin film transistor according to claim 5, further comprising: a fourth LDD structure. 　少なくとも前記第１及び第３のＬＤＤ構造の一部が、前記第２及び第４のＬＤＤ構造及び前記ソース／ドレイン構造によって覆われていない請求項８に記載の薄膜トランジスタ。 9. The thin film transistor according to claim 8, wherein at least a part of the first and third LDD structures is not covered by the second and fourth LDD structures and the source / drain structure. 　前記第１のＬＤＤ構造が前記第２のＬＤＤ構造及び前記ソース／ドレイン構造の第１の構造によって囲まれており、前記第３のＬＤＤ構造が前記第４のＬＤＤ構造及び前記ソース／ドレイン構造の第２の構造によって囲まれている請求項８に記載の薄膜トランジスタ。 The first LDD structure is surrounded by a first structure of the second LDD structure and the source / drain structure, and the third LDD structure is a structure of the fourth LDD structure and the source / drain structure. The thin film transistor according to claim 8, which is surrounded by the second structure. 　薄膜トランジスタの製造方法であって、
　半導体層を形成する工程と、
　前記半導体層の上にゲート絶縁層を形成する工程と、
　前記ゲート絶縁層の上にゲート構造を形成する工程と、
　前記半導体層にチャネル領域で互いに隔てられたソース／ドレイン構造を形成する工程と、
　第１のＬＤＤ構造を形成するために、前記半導体層の表面から第１の角度の第１の方向で前記チャネル領域の第１の端部に第１のドーピング物質を注入する工程と、
　前記第１のＬＤＤ構造に接触している第２のＬＤＤ構造を形成するために、前記半導体層の前記表面から第２の角度の第２の方向で前記チャネル領域の前記第１の端部に第２のドーピング物質を注入する工程と、を備えていることを特徴とする薄膜トランジスタの製造方法。 A method for manufacturing a thin film transistor,
Forming a semiconductor layer;
Forming a gate insulating layer on the semiconductor layer;
Forming a gate structure on the gate insulating layer;
Forming source / drain structures separated from each other by a channel region in the semiconductor layer;
Implanting a first doping material in a first direction at a first angle from a surface of the semiconductor layer to a first end of the channel region to form a first LDD structure;
Forming a second LDD structure in contact with the first LDD structure on the first end of the channel region in a second direction at a second angle from the surface of the semiconductor layer; And a step of injecting a second doping material. 　前記第１のドーピング物質を注入する前記工程が、前記ゲート構造をマスクとして用いて前記チャネル領域に対して行われ、
　第３のＬＤＤ構造が、前記第１のＬＤＤ構造が形成される時、前記チャネル領域における第１の端部の反対側の第２の端部に同時に形成される請求項１１に記載の薄膜トランジスタの製造方法。 The step of injecting the first doping material is performed on the channel region using the gate structure as a mask,
The thin film transistor of claim 11, wherein a third LDD structure is formed simultaneously at a second end of the channel region opposite the first end when the first LDD structure is formed. Production method. 　前記第３のＬＤＤ構造に接触している第４のＬＤＤ構造を形成するために、前記半導体層の前記表面から第３の角度の第３の方向で前記チャネル領域の前記第２の端部に第３のドーピング物質を注入する工程をさらに備えている請求項１２に記載の薄膜トランジスタの製造方法。 Forming a fourth LDD structure in contact with the third LDD structure at a third direction at a third angle from the surface of the semiconductor layer to the second end of the channel region; 13. The method according to claim 12, further comprising a step of injecting a third doping material. 　前記ゲート構造が、ゲート電極とその電極のそばのスペーサ構造を含み、
　前記第１のドーピング物質を注入する前記工程が、前記スペーサ構造が除去された後に行われる請求項１１に記載の薄膜トランジスタの製造方法。
The gate structure includes a gate electrode and a spacer structure near the electrode;
The method of claim 11, wherein the step of implanting the first doping material is performed after the spacer structure is removed.
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