JP2002076361A - Semiconductor device, its manufacturing method and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, its manufacturing method and an image display device which improves the reliability and forms a lightly doped region below a gate electrode at a good controllability by a simple process. SOLUTION: TFT has a gate electrode 18 provided through a gate insulation film 17 on a semiconductor film 9 laid on one surface of an insulation substrate 10, a channel region 13 on the semiconductor film 9 below the gate electrode 18, a source region 20 at one side of the channel region 13 of the semiconductor film 9, and a drain region 19 at the other side. The drain region 19 has a lightly doped region 14A underlying the end (drain side) of the gate electrode 18, and a heavily doped region 4A outside the lightly doped region 14A. This moderates the impurity concentration gradient between the channel region 13 and the drain region 19 to relax the electric field at the drain end, thereby suppressing generation of hot carriers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a thin film transistor formed on an insulating substrate such as glass, a method of manufacturing the same, and an image display device.

[0002]

2. Description of the Related Art Conventionally, there is a semiconductor device provided with an MIS field effect transistor (MISFET). In this MIS field effect transistor, a time-lapse is caused by injection of hot carriers into a gate insulating film. A GOLD (Gate Overlapped LDD) structure is known as a technique for suppressing characteristic deterioration and improving the reliability (lifetime) of an element. On the other hand, as one of the transistors, a thin film transistor (hereinafter, referred to as a TFT) in which an FET is formed on an amorphous semiconductor thin film provided on an insulating substrate is known. The TFT (Thin Film Tra) employing the above GOLD structure
nsistor) is described in JP-A-11-45999.

FIG. 10 is a cross-sectional view of a TFT having the GOLD structure. As shown in FIG. 10, the TFT having the GOLD structure is a semiconductor thin film (polycrystalline silicon thin film) provided on one surface of an insulating substrate 510. Gate insulating film 5 on 509
17, a p-type channel region 513 provided in a region of the semiconductor thin film 509 facing the gate electrode 580, and the semiconductor thin film 50.
It has an n-type source region 520 and an n-type drain region 519 provided on both sides of the nine channel regions 513, respectively. The source region 520 includes a low-concentration impurity region 515 and a high-concentration impurity region 505 provided along a direction away from the gate electrode 500.
Reference numeral 9 denotes a low-concentration impurity region 514 and a high-concentration impurity region 504 provided along a direction away from the gate electrode 500.
It is composed of The gate electrode 500 includes a first conductor 580 and source and drain-side second and third conductors (sidewalls) 550 and 550 provided on side surfaces of the first conductor 580. , Gate insulating film 517
The structure has low-concentration impurity regions 514, 515 immediately below the second and third conductors 550, 550 via the. Accordingly, in the TFT having the GOLD structure, the electric field applied to the low-concentration impurity region 514 (drain end) immediately below the end (sidewall) of the gate electrode 500 is reduced, so that the generation of hot carriers is suppressed and the gate insulating film 517 is formed. Injection of hot carriers into the carrier can be suppressed, and deterioration due to hot carriers can be suppressed.

[0004]

By the way, the above GOL
In order to form a TFT having a D structure, the following steps (1) to (3) are required to provide a low-concentration impurity region below a gate electrode.

Forming a first conductive type semiconductor thin film on the insulating substrate forming a gate insulating film on the semiconductor thin film forming a gate electrode on the gate insulating film using the gate electrode as a mask to form a semiconductor thin film; An impurity is implanted to form a source region and a drain region of the second conductivity type having a low impurity concentration.
After the Doped Drain step, a deposition step of forming a conductor layer on one surface of the insulating substrate is performed.The conductor layer is etched to form sidewalls on the source-side end surface and the drain-side end surface of the gate electrode. 2. Step of Forming Third Conductor (Sidewall) Therefore, the number of masks is increased by one, and the number of steps is increased by four steps of deposition, photo, development, and etching. Is also very complicated. In particular, since the length of the low-concentration impurity region immediately below the sidewall that determines the characteristics of the device is determined in a self-aligned manner by the width of the sidewall, control of the sidewall width becomes important. Since the sidewall width depends on two parameters, ie, the thickness of the deposited film of the second and third conductors (sidewalls) and the etch rate, it is difficult to control the sidewall width and it is a desirable method from the viewpoint of cost and yield. I can't say.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the electric field at the drain end with a simple structure, suppress deterioration due to hot carriers, improve the reliability (lifetime) of the TFT, and provide a simple and small TFT. It is an object of the present invention to provide a semiconductor device capable of forming a low-concentration impurity region under a gate electrode in a self-aligned manner with good controllability in a process, a manufacturing method thereof, and an image display device.

[0007]

In order to achieve the above object, a semiconductor device according to the present invention comprises: a gate electrode provided on a semiconductor thin film provided on one surface of an insulating substrate via a gate insulating film; A semiconductor device including a thin film transistor having a channel region provided in a region of the semiconductor thin film below an electrode, and a source region and a drain region provided on both sides of the channel region of the semiconductor thin film, At least the drain region of the source region and the drain region is provided with a low-concentration impurity region provided immediately below both ends of the gate electrode without sidewalls, and the low-concentration impurity region is opposite to the channel region with respect to the low-concentration impurity region. And a high-concentration impurity region provided on the side.

According to the semiconductor device having the above structure, at least the drain region of the source region and the drain region is formed of the low concentration impurity region and the high concentration impurity region provided along the direction away from the gate electrode. Since the low-concentration impurity region is provided directly below at least the drain-side end of the gate electrode via the gate insulating film, the impurity concentration gradient between the channel region and the drain region becomes gentle, Can be reduced. As a result, the generation of hot carriers can be suppressed, and at the same time, the penetration of hot carriers into the gate insulating film on the low-concentration impurity region can be suppressed, so that device characteristics caused by electrons trapped in the gate insulating film ( Deterioration of the threshold voltage Vth, the transfer characteristic β, etc.) is suppressed, and the reliability (lifetime) of the TFT can be improved. Also, a low concentration impurity can be formed under the gate electrode by a simpler method and fewer steps without performing many steps by a complicated method of forming sidewalls made of the second and third conductors such as a GOLD structure. The region can be formed in a self-aligned manner with good controllability.

In one embodiment, the first impurity added to the low-concentration impurity region is an impurity of an ion type different from that of the second impurity added to the high-concentration impurity region; It is characterized in that the diffusion coefficient is larger than that of the second impurity.

According to the semiconductor device of the embodiment, since the difference in diffusion coefficient can be utilized when the first and second impurities are different ionic species, a low concentration impurity region and a high impurity concentration can be used as compared with the same ionic species. The difference between the impurity region and the diffusion region is increased, the effect of relaxing the electric field in the horizontal direction of the channel is increased, and the reliability for hot carriers is improved.

In one embodiment, the first impurity added to the low-concentration impurity region is an impurity of the same ionic species as the second impurity added to the high-concentration impurity region. And

According to the semiconductor device of the above embodiment, the first impurity in the low-concentration impurity region is of the same ionic species as the second impurity in the high-concentration impurity region. It is not available, but the first,
Doping of the second impurity can be performed using the same apparatus under the same conditions, and the process can be simplified.

In one embodiment of the present invention, the semiconductor thin film is one of a single crystal silicon thin film, a polycrystalline silicon thin film, and an amorphous silicon thin film.

According to the semiconductor device of the above embodiment, when the semiconductor thin film is a single crystal silicon thin film, the mobility of electrons is very large (about 1500 cm ² / Vs), and a thin film transistor which operates at high speed can be obtained. When the semiconductor thin film is a polycrystalline silicon thin film, it can be formed by a relatively low temperature process (600 to 1000 ° C.). When the semiconductor thin film is an amorphous silicon thin film, a process at a lower temperature than polycrystalline silicon (about 3
(50 ° C.).

In the method of manufacturing a semiconductor device according to the present invention, the first impurity added to the low-concentration impurity region is an impurity of an ion type different from that of the second impurity added to the high-concentration impurity region; A method for manufacturing a semiconductor device, wherein the first impurity has a larger diffusion coefficient than the second impurity, the method comprising: forming a first conductive type semiconductor thin film on one surface of the insulating substrate; Forming a gate insulating film on the semiconductor thin film, forming a gate electrode on the gate insulating film, and using the gate electrode as a mask in a region other than a region facing the gate electrode of the semiconductor thin film. Implanting a first impurity;
A step of performing a heat treatment after injecting the first impurity to diffuse the first impurity toward a channel region below the gate electrode; and after diffusing the first impurity,
Implanting a second impurity of an ion species different from the first impurity into a region other than the region facing the gate electrode of the semiconductor thin film using the gate electrode as a mask, and performing a heat treatment after the implantation of the second impurity To form a second conductivity type low-concentration impurity region in a region immediately below both ends of the gate electrode of the semiconductor thin film, and a second conductivity type low-concentration impurity region in a region outside the low concentration impurity region of the semiconductor thin film. Forming a high-concentration impurity region.

According to the method of manufacturing a semiconductor device, a semiconductor thin film of the first conductivity type is formed on one surface of the insulating substrate, and a gate insulating film is formed on the semiconductor thin film. Next, a gate electrode is formed on the gate insulating film, and using the gate electrode as a mask, a first impurity is implanted into a region other than a region facing the gate electrode of the semiconductor thin film, and then a heat treatment is applied to the first impurity. Is diffused toward the channel region below the gate electrode. After that, using the gate electrode as a mask, a second impurity of an ion type different from the first impurity is implanted into a region other than a region facing the gate electrode of the semiconductor thin film, and then a heat treatment is performed to thereby apply both ends of the gate electrode of the semiconductor thin film. A second conductivity type low concentration impurity region is formed in a region immediately below the portion, and a second conductivity type high concentration impurity region is formed in a region outside the low concentration impurity region of the semiconductor thin film.
As described above, at least the drain region of the source region and the drain region includes the low-concentration impurity region and the high-concentration impurity region provided along the direction away from the gate electrode. Since it is provided immediately below both ends of the gate electrode with the insulating film interposed therebetween, the impurity concentration gradient between the channel region and the drain region becomes gentle, and the electric field applied to the drain end can be reduced. As a result, the generation of hot carriers can be suppressed, and at the same time, the penetration of hot carriers into the gate insulating film on the low-concentration impurity region can be suppressed, so that device characteristics caused by electrons trapped in the gate insulating film ( Deterioration of the threshold voltage Vth, the transfer characteristic β, etc.) is suppressed, and the reliability (lifetime) of the TFT can be improved. Also, a low concentration impurity can be formed under the gate electrode by a simpler method and fewer steps without performing many steps by a complicated method of forming sidewalls made of the second and third conductors such as a GOLD structure. The region can be formed in a self-aligned manner with good controllability.

Further, in the method of manufacturing a semiconductor device according to the present invention, the first impurity added to the low-concentration impurity region is an impurity of an ion type different from the second impurity added to the high-concentration impurity region; A method for manufacturing a semiconductor device, wherein the first impurity has a larger diffusion coefficient than the second impurity, the method comprising: forming a first conductive type semiconductor thin film on one surface of the insulating substrate; Forming a gate insulating film on the semiconductor thin film, forming a gate electrode on the gate insulating film, and using the gate electrode as a mask in a region other than a region facing the gate electrode of the semiconductor thin film. Implanting a first impurity;
Implanting a second impurity of an ion type different from the first impurity into a region of the semiconductor thin film other than a region facing the gate electrode, using the gate electrode as a mask, after implanting the first impurity; After injecting two impurities,
A first heat treatment is performed to diffuse the first and second impurities toward the channel region below the gate electrode, and a second conductive type low-concentration impurity region is formed in a region of the semiconductor thin film immediately below both ends of the gate electrode. Forming a second conductive type high-concentration impurity region in a region outside the low-concentration impurity region of the semiconductor thin film.

According to the method of manufacturing a semiconductor device of the above embodiment, a semiconductor thin film of the first conductivity type is formed on one surface of the insulating substrate, and a gate insulating film is formed on the semiconductor thin film. Next, a gate electrode is formed on the gate insulating film,
Using the gate electrode as a mask, the first impurity is implanted into a region other than the region facing the gate electrode of the semiconductor thin film,
Using the gate electrode as a mask, a second impurity of an ion type different from the first impurity is implanted into a region of the semiconductor thin film other than the region facing the gate electrode. Thereafter, heat treatment is performed to diffuse the first and second impurities toward the channel region below the gate electrode, thereby forming a second conductive type low-concentration impurity region in a region immediately below both ends of the gate electrode of the semiconductor thin film. And a second region in the semiconductor thin film outside the low-concentration impurity region.
A conductive type high concentration impurity region is formed. As described above, at least the drain region of the source region and the drain region includes the low-concentration impurity region and the high-concentration impurity region provided along the direction away from the gate electrode. Since it is provided immediately below both ends of the gate electrode via the insulating film, the impurity concentration gradient between the channel region and the drain region becomes gentle,
The electric field applied to the drain end can be reduced. As a result, the generation of hot carriers can be suppressed, and at the same time, the penetration of hot carriers into the gate insulating film on the low-concentration impurity region can be suppressed, so that device characteristics caused by electrons trapped in the gate insulating film can be suppressed.
(Threshold voltage Vth, transfer characteristic β, etc.) are suppressed, and the reliability (lifetime) of the TFT can be improved. Also, GOL
A low concentration impurity region can be formed under a gate electrode by a simpler method and fewer steps without performing many steps by a complicated method of forming side walls made of the second and third conductors such as a D structure. It can be formed in a self-aligned manner with good controllability. Further, the diffusion of the impurity and the activation of the impurity region can be performed simultaneously by one heat treatment, so that the steps can be simplified.

Further, according to the method of manufacturing a semiconductor device of the present invention, the first impurity added to the low-concentration impurity region is an impurity of the same ionic species as the second impurity added to the high-concentration impurity region. A method of manufacturing a semiconductor device for manufacturing, comprising: forming a semiconductor thin film of a first conductivity type on one surface of the insulating substrate; forming a gate insulating film on the semiconductor thin film; Forming a gate electrode on the insulating film; implanting a first impurity into a region of the semiconductor thin film other than the region facing the gate electrode using the gate electrode as a mask;
A step of performing a heat treatment after injecting the impurity to diffuse the first impurity toward the channel region below the gate electrode; and, after diffusing the first impurity, the semiconductor using the gate electrode as a mask. Implanting the second impurity of the same ionic species as the first impurity into a region other than the region facing the gate electrode of the thin film, and subjecting the semiconductor thin film to a heat treatment after implanting the second impurity Forming a second-conductivity-type low-concentration impurity region in a region immediately below both ends of the gate electrode, and forming a second-conductivity-type high-concentration impurity region in a region of the semiconductor thin film outside the low-concentration impurity region. It is characterized by having the step of performing.

According to the method of manufacturing a semiconductor device of the above embodiment, a semiconductor thin film of the first conductivity type is formed on one surface of the insulating substrate, and a gate insulating film is formed on the semiconductor thin film. Next, a gate electrode is formed on the gate insulating film,
Using the gate electrode as a mask, the first impurity is implanted into a region other than the region facing the gate electrode of the semiconductor thin film,
Heat treatment is performed to diffuse the first impurity toward the channel region below the gate electrode. After that, using the gate electrode as a mask, a second impurity of the same ionic species as the first impurity is implanted into a region other than the region facing the gate electrode of the semiconductor thin film, and then a heat treatment is performed to thereby apply both ends of the gate electrode of the semiconductor thin film. A second conductivity type low concentration impurity region is formed in a region immediately below the portion, and a second conductivity type high concentration impurity region is formed in a region outside the low concentration impurity region of the semiconductor thin film.
As described above, at least the drain region of the source region and the drain region includes the low-concentration impurity region and the high-concentration impurity region provided along the direction away from the gate electrode. Since it is provided immediately below both ends of the gate electrode with the insulating film interposed therebetween, the impurity concentration gradient between the channel region and the drain region becomes gentle, and the electric field applied to the drain end can be reduced. As a result, the generation of hot carriers can be suppressed, and at the same time, the penetration of hot carriers into the gate insulating film over the low-concentration impurity regions can be suppressed, so that device characteristics caused by electrons trapped in the gate insulating film ( Deterioration of the threshold voltage Vth, the transfer characteristic β, etc.) is suppressed, and the reliability (lifetime) of the TFT can be improved. Also, a low concentration impurity can be formed under the gate electrode by a simpler method and fewer steps without performing many steps by a complicated method of forming sidewalls made of the second and third conductors such as a GOLD structure. The region can be formed in a self-aligned manner with good controllability. Further, doping of the first and second impurities of the same ion species can be performed using the same apparatus under the same conditions, and the process can be simplified.

The image display device according to the present invention is an image display device in which the semiconductor device is provided on a glass substrate, wherein the semiconductor device is used in an image display section and a drive section for driving the image display section. It is characterized by having been.

According to the image display device of the above embodiment, the reliability (lifetime) can be improved, and the low-concentration impurity region can be formed in a self-aligned manner with good controllability under the gate electrode by a simple method and in a small number of steps. By using the semiconductor device for the image display unit and a driving unit for driving the image display unit, an image display device with high reliability and long life can be realized.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device, a method of manufacturing the same, and an image display device according to the present invention will be described below in detail with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 is a sectional view of an n-type TFT of a semiconductor device according to a first embodiment of the present invention.

As shown in FIG. 1, this TFT comprises a semiconductor thin film 9 provided on an insulating substrate 10 made of a quartz substrate.
A p-type channel region 13 as a first conductivity type having a predetermined length, and n ⁻ -type low-concentration impurity regions 14A, 1 as a second conductivity type provided on both sides of the channel region 13 respectively.
5A, and n ⁺ -type high-concentration impurity regions 4A and 5A as the second conductivity type provided outside the low-concentration impurity regions 14A and 15A, respectively. The low concentration impurity region 14A is a low concentration drain region, and the low concentration impurity region 15A is a low concentration source region. The high concentration impurity region 4A is a high concentration drain region, and the high concentration impurity region 5A is a high concentration source region. Then, the drain region 19 is constituted by the low-concentration drain region (14A) and the high-concentration drain region (4A).
(15A) and the high concentration source region (5A) constitute the source region 20.

The semiconductor thin film 9 is formed, for example, by low pressure CVD.
A polycrystalline silicon thin film formed by a (chemical vapor deposition) method (or a polycrystalline silicon thin film formed by depositing an amorphous silicon thin film and then performing a heat treatment). The gate insulating film 17 is formed on the low-concentration impurity regions 14A and 15A, the high-concentration impurity regions 4A and 5A, and the channel region 13 by, for example, depositing SiO ₂ by CVD.

On the other hand, the low concentration impurity regions 14A, 15
A is provided in a region of the semiconductor thin film 9 immediately below both ends of the gate electrode 18. Both ends of the gate electrode 18 extend slightly above the high concentration impurity regions 4A and 5A beyond the low concentration impurity regions 14A and 15A. This is because when the high concentration impurity regions 4A and 5A are formed, the gate electrode 18 is used as a mask for implanting impurities, and impurities are diffused below the gate electrode 18 by a subsequent heat treatment.

The insulating film 3 is formed on the gate electrode 18 and the gate insulating film 17. This insulating film 3
Is composed of, for example, a laminate of an NSG (non-doped silicate glass) film / BPSG (boron-phosphorus silicate glass) film. Further, the high-concentration impurity regions 4,
The contact holes 21 and 22 are selectively provided in the gate insulating film 17 and the insulating film 3 on the gate electrode 5, and the contact holes 21 and 22 are electrically connected to the high-concentration impurity regions 4A and the high-concentration impurity regions 5A. The drain electrode 6 and the source electrode 7 are respectively formed.

Next, a method of manufacturing the TFT having the above configuration will be described with reference to FIGS.

First, as shown in FIG. 2, a p-type semiconductor thin film 9 having a thickness of about 40 nm is formed on an insulating substrate 10 made of a quartz substrate by a low pressure CVD method. Alternatively, a semiconductor thin film 9 having a thickness of about 40 nm may be formed by forming an amorphous silicon thin film by low-pressure CVD and then performing a heat treatment at 600 ° C. for 24 hours in an N ₂ atmosphere for crystallization.

An 80 nm thick gate insulating film 17 made of SiO ₂ is formed on the semiconductor thin film 9 by a low pressure CVD method.
Further, a film thickness of 150 nm / 1 is formed on the gate insulating film 17.
A stacked gate electrode 18 of 50 nm WSi / polycrystalline silicon is formed.

Next, using the gate electrode 18 as a mask, the semiconductor thin film 9 is doped with an n-type, low-concentration first impurity A having a large diffusion coefficient in a self-aligned manner (for example, the first impurity A).
As the impurity A, phosphorus is doped at 2 × 10 ¹⁴ / cm ² ).

Subsequently, as shown in FIG. 3, a low-temperature first impurity A is diffused toward the channel region 13 by performing a heat treatment at 1000 ° C. for 30 minutes in an N ₂ atmosphere to form a gate of the semiconductor thin film 9. A low-concentration impurity region 1 is formed in a region other than the region facing the electrode 18 and immediately below both ends of the gate electrode 18.
4, 15 are formed respectively.

Again, using the gate electrode 18 as a mask, as shown in FIG. 4, a high concentration second impurity B having an n-type diffusion coefficient smaller than the low concentration first impurity A is self-aligned with the semiconductor thin film 9. (For example, arsenic is doped as the second impurity B at 3 × 10 ¹⁵ / cm ² ).
Thus, the low concentration impurity region 1 which is a low concentration drain region is formed in a region of the semiconductor thin film 9 immediately below both ends of the gate electrode 18.
4A and low concentration impurity region 1 which is a low concentration source region
5A and the low concentration impurity regions 14A,
High-concentration impurity regions 4 and 5 are formed outside 15A, respectively.

Next, as shown in FIG. 5, NSG having a thickness of about 100 nm is formed on the entire surface of the insulating substrate 10 by the CVD method.
Is deposited to form an interlayer insulating film 3a, and then heat treatment is performed at 900 ° C. for 20 minutes to activate the doped impurities. Further, the film thickness is 600 nm by a normal pressure CVD method.
After depositing about BPSG to form an interlayer insulating film 3b on the interlayer insulating film 3a, a heat treatment is performed at 950 ° C. for 30 minutes. Thus, a high-concentration impurity region 4A as a high-concentration drain region and a high-concentration impurity region 5A as a high-concentration source region are formed.

Then, the interlayer insulating films 3 (3a, 3b) on the high-concentration impurity regions 4A and 5A are selectively etched to form contact holes 21, 22 (FIG. 1).
Is formed, and the contact holes 21 and
The TFT shown in FIG. 1 is formed by filling the conductor 22 with the conductor and forming the drain electrode 6 and the source electrode 7.

As described above, since the low-concentration impurity region 14A of the drain region 19 is provided immediately below the end (drain side) of the gate electrode 18 via the gate insulating film 17, the channel region 13 and the drain region 19 , The gradient of the impurity concentration becomes gentle, and the electric field applied to the drain end can be reduced. Thereby, the generation of hot carriers can be suppressed, and at the same time, the low-concentration impurity region 14A is formed.
Since the intrusion of hot carriers into the upper gate insulating film 17 can be suppressed, device characteristics (threshold voltage Vt) caused by electrons trapped in the gate insulating film 17 can be suppressed.
h, transfer characteristics β, etc.), and the reliability of the TFT
(Lifetime) can be improved. In addition, the low-concentration impurity region can be formed under the gate electrode in a simpler and less number of steps without performing many steps by a complicated method of forming side walls made of the second and third conductors such as a GOLD structure. It can be formed in a self-aligned manner with good controllability.

(Second Embodiment) FIGS. 6A to 6C are diagrams showing a method of manufacturing a TFT according to a second embodiment of the present invention. The method of manufacturing the TFT according to the second embodiment includes the steps of:
A semiconductor thin film 10 comprising a p-type polycrystalline silicon thin film thereon
After depositing the gate insulating film 117 made of 9 and SiO ₂ ,
Until the step of forming a stacked gate electrode 118 made of WSi / polycrystalline silicon on the gate insulating film 117, the first step of forming low-concentration impurity regions on the source side and the drain side is performed.
This is the same as the TFT of the embodiment.

First, when the low concentration impurity region 114 is formed only on the drain side of the gate electrode 118, FIG.
As shown in (1), a portion from the approximate center of the gate electrode 118 to the source side is masked with the resist 101.

Next, as shown in FIG.
01 and the gate electrode 118 as a mask, a low-concentration first impurity A (for example,
(× 10 ¹⁴ / cm ² ) is doped in the semiconductor thin film 109 in a self-aligned manner, and the low concentration impurity region 114 is formed only on the drain side of the semiconductor thin film 109.

Next, as shown in FIG.
01 (shown in FIG. 6B) is peeled off.

Thereafter, as shown in FIG. 6D, a low concentration first impurity A is diffused toward a region to be a channel region by performing a heat treatment at 1000 ° C. for 30 minutes in an N ₂ atmosphere. A low-concentration impurity region 114 is formed in a region of the semiconductor thin film 109 other than the region facing the gate electrode 118 and in a region on the drain side and in a region immediately below an end (drain side) of the gate electrode 118 of the semiconductor thin film 109.

Next, using the gate electrode 118 as a mask, as shown in FIG. 6E, an n-type high impurity second impurity B smaller than the low impurity first impurity A is used.
(For example, arsenic is 3 × 10 ¹⁵ / cm ² )
Doping. By doing so, the high concentration impurity region 105 is formed on the source side of the semiconductor thin film 109, and the gate electrode 118 of the semiconductor thin film 109 is formed.
Low-concentration impurity region 11 in the region immediately below the end (drain side) of
4A, and the high concentration impurity region 104 is formed outside the low concentration impurity region 114A.

Thereafter, the interlayer insulating film 103 (NSG, BPS
G), forming a contact hole, filling a conductor, forming a drain electrode (not shown) and a source electrode (not shown), and performing a heat treatment for activation. Are performed in the same manner as in the method of manufacturing the TFT of the first embodiment.

The TFT of the second embodiment and the method of manufacturing the TFT have the same effects as those of the first embodiment.

(Third Embodiment) FIGS. 7A to 7C are diagrams showing a method of manufacturing a TFT according to a third embodiment of the present invention.

First, as shown in FIG. 7A, a p-type film having a thickness of about 40 nm is formed on an insulating substrate 210 made of a quartz substrate.
A semiconductor thin film 209 made of a polycrystalline silicon thin film is formed by a low pressure CVD method. Alternatively, a semiconductor thin film made of a polycrystalline silicon thin film having a thickness of about 40 nm may be formed by forming an amorphous silicon thin film by CVD and then performing a heat treatment at 600 ° C. for 24 hours in an N ₂ atmosphere to be crystallized. Good.

Next, a gate insulating film 217 made of SiO ₂ having a thickness of 80 nm and a laminated gate electrode 218 made of WSi / polycrystalline silicon having a thickness of 150/150 nm are formed on the semiconductor thin film 209 by the CVD method. .

Next, using the gate electrode 218 as a mask, the semiconductor thin film 209 is doped with an n-type low concentration first impurity A (for example, 2 × 10 ¹⁴ / cm ^{2 of} phosphorus) having a large diffusion coefficient in a self-aligned manner. I do. Then, low-concentration impurity regions 214 and 215 are formed in regions of the semiconductor thin film 209 other than the region facing the gate electrode 218 and in regions of the semiconductor thin film 209 just below both ends of the gate electrode 218.

Then, using the gate electrode 218 as a mask again, as shown in FIG. 7B, the second impurity B having a high concentration is smaller than the first impurity A having an n-type and a low diffusion coefficient.
(For example, arsenic is 3 × 10 ¹⁵ / cm ² )
Is self-aligned. By doing so, the high-concentration impurity utilization regions 204 and 205 are formed in regions of the semiconductor thin film 209 other than the region facing the gate electrode 218.
Are formed respectively.

Next, as shown in FIG.
After an NSG having a thickness of about 100 nm is deposited on the entire surface of the substrate 10 by a CVD method to form an interlayer insulating film 203a,
A heat treatment is performed at 000 ° C. for 30 minutes to activate the doped first and second impurities A and B, and at the same time, gate the first impurity A due to a difference in diffusion coefficient between the first and second impurities A and B. The low-concentration impurity regions 214 </ b> A and 21 </ b> A are diffused toward a region to be a channel region immediately below both ends of the electrode 218.
5A are formed, and high-concentration impurity regions 204A and 205A made of the second impurity B are formed outside thereof.

Further, as shown in FIG.
After depositing BPSG with a thickness of about 600 nm on the G film 203a by a normal pressure CVD method to form an interlayer insulating film 203b, a heat treatment is performed at 950 ° C. for 30 minutes.

Then, as shown in FIG. 7E, the interlayer insulating film 203 on the high-concentration impurity regions 204A and 205A is selectively etched to form contact holes 221 and 222.
And contact holes 221 and 22
2 is filled with a conductor, and a drain electrode 206 and a source electrode 207 are formed to form a TFT.

The low concentration impurity region 214A is a low concentration drain region, and the low concentration impurity region 215A is a low concentration source region. Also, the high-concentration impurity region 204
A is a high-concentration drain region and a high-concentration impurity region 20.
5A is a high concentration source region. Then, the drain region 219 is constituted by the low-concentration drain region (214A) and the high-concentration drain region (204A).
(215A) and the high concentration source region (205A) constitute the source region 220.

As described above, since the low-concentration impurity region 214A of the drain region 219 is provided immediately below the end (drain side) of the gate electrode 218 via the gate insulating film 217, the channel region 213 and the drain region 219 , The gradient of the impurity concentration becomes gentle, and the electric field applied to the drain end can be reduced. Thus, the generation of hot carriers can be suppressed, and at the same time, the penetration of hot carriers into the gate insulating film 217 on the low concentration impurity region 214A can be suppressed.
Device characteristics caused by electrons trapped in 17
(Threshold voltage Vth, transfer characteristic β, etc.) are suppressed, and the reliability (lifetime) of the TFT can be improved. Also, GOL
Self-aligning a low concentration impurity region under a gate electrode in a simpler and less number of steps without performing many steps by a complicated method of forming sidewalls made of second and third conductors such as a D structure. It can be formed with good controllability.
Further, the diffusion of the impurity and the activation of the impurity region can be performed simultaneously by one heat treatment, so that the process can be simplified.

(Fourth Embodiment) FIGS. 8A to 8C are diagrams showing a method of manufacturing a TFT according to a fourth embodiment of the present invention.

First, as shown in FIG. 8A, a p-type film having a thickness of about 40 nm is formed on an insulating substrate 310 made of a quartz substrate.
A semiconductor thin film 309 made of a polycrystalline silicon thin film is formed by a low pressure CVD method. Alternatively, a semiconductor thin film made of a polycrystalline silicon thin film having a thickness of about 40 nm may be formed by forming an amorphous silicon thin film by CVD and then performing a heat treatment at 600 ° C. for 24 hours in an N ₂ atmosphere to be crystallized. Good.

Next, a gate insulating film 317 made of SiO ₂ having a thickness of 80 nm is formed on the semiconductor thin film 309 by CVD, and a gate insulating film 317 having a thickness of 15 nm is formed on the gate insulating film 317.
A stacked gate electrode 318 made of WSi / polycrystalline silicon having a thickness of 0 n / 150 nm is formed.

Next, using the gate electrode 318 as a mask, an n-type low-concentration first impurity A (for example,
0 ^{13 to} 3 × 10 ¹³ / cm ² ) is doped into the semiconductor thin film 309 in a self-aligned manner.

Then, as shown in FIG. 8B, heat treatment is performed in an N ₂ atmosphere at 1000 ° C. for 30 minutes to reduce the concentration of the first impurity A to a region to be a channel region of the semiconductor thin film 309. In the semiconductor thin film 309 except for the region facing the gate electrode 318 and the semiconductor thin film 30.
The low concentration impurity regions 314 and 315 are formed in the regions immediately below both ends of the gate electrode 318 of No. 9.

Again using the gate electrode 318 as a mask, as shown in FIG. 8C, the same high concentration first impurity A (for example, 3 × 10
¹⁵ / cm ² ) is doped in the semiconductor thin film 309 in a self-aligned manner, and low concentration impurity regions 314A and 315A are formed in regions of the semiconductor thin film 309 immediately below both ends of the gate electrode 318, respectively. , 31
High-concentration impurity regions 304 and 305 are formed outside 5A, respectively.

Next, as shown in FIG.
An NSG having a thickness of about 100 nm is deposited on the entire surface of the substrate 10 by the CVD method to form an interlayer insulating film 303a.
Heat treatment for a minute. Further, a film thickness of 6
BPSG of about 00 nm is deposited, and an interlayer insulating film 303 is formed.
After forming b, heat treatment is performed at 950 ° C. for 30 minutes. Thus, the high-concentration impurity region 3 which is the high-concentration drain region
04A and a high-concentration impurity region 305A, which is a high-concentration source region, are formed.

Then, as shown in FIG. 8E, the insulating film 303 (30) on the high-concentration impurity regions 304A and 305A is formed.
3a and 303b) are selectively etched to form contact holes 321 and 322, and the contact holes 321 and 322 are filled with a conductor to form a drain electrode 306 and a source electrode 307. Form.

The low concentration impurity region 314A is a low concentration drain region, and the low concentration impurity region 315A is a low concentration source region. Further, the high-concentration impurity region 304
A is a high-concentration drain region and a high-concentration impurity region 30.
5A is a high concentration source region. A drain region 319 is formed by the low-concentration drain region (314A) and the high-concentration drain region (304A).
(315A) and the high concentration source region (305A) constitute the source region 320.

As described above, since the low-concentration impurity region 314A of the drain region 319 is provided immediately below the end (drain side) of the gate electrode 318 via the gate insulating film 317, the channel region 313 and the drain region 319 , The gradient of the impurity concentration becomes gentle, and the electric field applied to the drain end can be reduced. Thus, the generation of hot carriers can be suppressed, and at the same time, the penetration of hot carriers into the gate insulating film 317 on the low concentration impurity region 314A can be suppressed.
Device characteristics caused by electrons trapped in 17
(Threshold voltage Vth, transfer characteristic β, etc.) are suppressed, and the reliability (lifetime) of the TFT can be improved. Also, GOL
Self-aligning a low concentration impurity region under a gate electrode in a simpler and less number of steps without performing many steps by a complicated method of forming sidewalls made of second and third conductors such as a D structure. It can be formed with good controllability.
In addition, since the first and second impurities A and B are of the same ionic species, doping can be performed using the same apparatus under the same conditions, and the process can be simplified.

(Fifth Embodiment) FIG. 9A is a schematic view of an image display device according to a fifth embodiment of the present invention.

As shown in FIG. 9A, the image display device 42
Reference numeral 1 denotes an image display unit 423 incorporating a TFT of the present invention, a source driver 424 as a driving circuit, and a gate driver 425 disposed on one surface side of one quartz (glass) substrate 422.

By using the semiconductor device having the TFT of the present invention for the image display portion 423, the source driver 424, and the gate driver 425, an image display device having high reliability, a long life, and a low cost can be realized. Can be.

As shown in FIG. 9B, the image display device 421 can be applied to a transmissive liquid crystal panel.
An FT substrate) and a counter substrate 426 are bonded with a seal resin 427, and a liquid crystal 428 is injected therebetween.

In the first to fourth embodiments, the semiconductor device having an n-type TFT with the first conductivity type being p-type and the second conductivity type being n-type has been described. Second
Of course, the present invention may be applied to a semiconductor device having a p-type TFT with a p-type conductivity.

[0071]

As is clear from the above, according to the semiconductor device and the method of manufacturing the same of the present invention, the electric field at the drain end of the TFT can be reduced, so that the miniaturization,
Even in highly integrated semiconductor devices, generation of hot carriers is suppressed, and TFT device characteristics (threshold voltage Vt
h, transfer characteristics β, etc.), and a long-life semiconductor device with excellent reliability can be realized.

Further, since the semiconductor device can be manufactured with a simple configuration using the self-alignment technique with a short process, it is possible to manufacture a semiconductor device and an image display device using the semiconductor device at a high yield and at low cost. Become.

[Brief description of the drawings]

FIG. 1 is a sectional view of an n-type TFT as a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a side sectional view showing a low-concentration impurity implantation step for manufacturing the n-type TFT.

FIG. 3 is a side sectional view showing a step of thermally diffusing low-concentration impurities for manufacturing the n-type TFT.

FIG. 4 is a side sectional view showing a high-concentration impurity implantation step for manufacturing the n-type TFT.

FIG. 5 is a side sectional view showing a step of forming an interlayer insulating film for manufacturing the n-type TFT.

FIGS. 6A to 6C are diagrams showing a method for manufacturing an n-type TFT of a semiconductor device according to a second embodiment of the present invention.

FIGS. 7A to 7C are diagrams showing a method for manufacturing an n-type TFT of a semiconductor device according to a third embodiment of the present invention.

FIGS. 8A to 8C are views showing a method for manufacturing an n-type TFT of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9A shows a TFT according to a fifth embodiment of the present invention.
FIG. 9B is a schematic view of a transmissive liquid crystal panel using the image processing apparatus, as viewed from the side.

FIG. 10 is a diagram showing a conventional GOLD structure-applied T
It is sectional drawing of FT.

[Explanation of symbols]

3,203,303 ... interlayer insulating film, 4,104,204,204A, 304,304A ... high concentration impurity region, 5,105,205,205A, 305,305A ... high concentration impurity region, 6,206,306 ... Drain electrode 7, 207, 307 Source electrode 9, 109, 209, 309 Semiconductor thin film 10, 110, 210, 310 Insulating substrate 13, 213, 313 Channel region 14, 114, 114A, 214 , 214A, 314,314
A: Low concentration impurity region 15, 215, 215A, 315, 315A: Low concentration impurity region, 17, 117, 217, 317: Gate insulating film, 18, 118, 218, 318: Gate electrode, 19, 219, 319 ... Drain region, 20,220,320 ... Source region.

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toru Ueda 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term in Sharp Corporation (reference) 2H092 JA25 JA36 JA40 JA44 JB57 KA03 KA04 KA07 KA10 MA07 MA26 MA27 MA41 NA11 NA27 5F110 AA13 AA14 AA16 BB02 BB04 CC02 DD02 DD03 EE05 EE09 EE14 EE32 FF02 FF29 GG02 GG12 GG13 GG15 GG25 GG47 HJ01 HJ04 HJ23 HM12 HM15 NN03 NN04 NN22 NN35 NN11 PP10 Q13 Q

Claims (8)

[Claims] A gate electrode provided on a semiconductor thin film provided on one surface of an insulating substrate via a gate insulating film; a channel region provided in a region of the semiconductor thin film below the gate electrode; A semiconductor device comprising a thin film transistor having a source region and a drain region provided on both sides of the channel region of the semiconductor thin film, wherein at least the drain region of the source region and the drain region has no sidewall. A low-concentration impurity region provided in a region immediately below both ends of the gate electrode;
A semiconductor device comprising: a low-concentration impurity region; and a high-concentration impurity region provided on a side opposite to the channel region. 2. The semiconductor device according to claim 1, wherein the first impurity added to the low-concentration impurity region is an impurity of an ion type different from the second impurity added to the high-concentration impurity region, And a diffusion coefficient larger than that of the second impurity. 3. The semiconductor device according to claim 1, wherein the first impurity added to the low-concentration impurity region is an impurity of the same ionic species as the second impurity added to the high-concentration impurity region. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 1, wherein the semiconductor thin film is any one of a single crystal silicon thin film, a polycrystalline silicon thin film, and an amorphous silicon thin film. A semiconductor device characterized by the above-mentioned. 5. A method for manufacturing a semiconductor device according to claim 2, wherein a step of forming a first conductive type semiconductor thin film on one surface of the insulating substrate; Forming a gate insulating film on the thin film; forming a gate electrode on the gate insulating film; using the gate electrode as a mask, forming a first impurity in a region of the semiconductor thin film other than the region facing the gate electrode. Implanting the first impurity, performing a heat treatment to diffuse the first impurity toward the channel region below the gate electrode, and implanting the first impurity. A second ion species different from the first impurity in a region of the semiconductor thin film other than a region facing the gate electrode using the gate electrode as a mask;
A step of implanting an impurity; and a step of performing a heat treatment after injecting the second impurity into a region of the semiconductor thin film immediately below both ends of the gate electrode.
Forming a low-concentration impurity region of a conductivity type and forming a high-concentration impurity region of a second conductivity type in a region outside the low-concentration impurity region of the semiconductor thin film. Production method. 6. A method of manufacturing a semiconductor device for manufacturing a semiconductor device according to claim 2, wherein: a step of forming a first conductivity type semiconductor thin film on one surface of the insulating substrate; Forming a gate insulating film on the thin film; forming a gate electrode on the gate insulating film; using the gate electrode as a mask, forming a first impurity in a region of the semiconductor thin film other than the region facing the gate electrode. Implanting the first impurity, and then implanting a second impurity of an ion type different from the first impurity into a region of the semiconductor thin film other than the region facing the gate electrode, using the gate electrode as a mask. Performing a heat treatment after implanting the second impurity to diffuse the first and second impurities toward the channel region below the gate electrode, A second conductivity type low concentration impurity region is formed in a region immediately below both ends of the gate electrode, and a second conductivity type high concentration impurity region is formed in a region of the semiconductor thin film outside the low concentration impurity region. And a method of manufacturing a semiconductor device. 7. A method for manufacturing a semiconductor device according to claim 3, wherein: a step of forming a first conductive type semiconductor thin film on one surface of the insulating substrate; Forming a gate insulating film on the thin film; forming a gate electrode on the gate insulating film; using the gate electrode as a mask, forming a first impurity in a region of the semiconductor thin film other than the region facing the gate electrode. Implanting the first impurity, performing a heat treatment to diffuse the first impurity toward the channel region below the gate electrode, and implanting the first impurity. Implanting the second impurity of the same ionic species as the first impurity into a region of the semiconductor thin film other than the region facing the gate electrode, using the gate electrode as a mask; After injection of pure object is subjected to a heat treatment, the second to the region directly below both end portions of the gate electrode of the semiconductor thin film
Forming a conductive type low-concentration impurity region and forming a second conductive type high-concentration impurity region in a region of the semiconductor thin film outside the low-concentration impurity region. Method. 8. An image display device comprising the semiconductor device according to claim 1 provided on a glass substrate, wherein the image display unit and a driving unit that drives the image display unit are provided. An image display device using a semiconductor device.