CN109119427B - Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate - Google Patents
Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate Download PDFInfo
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- CN109119427B CN109119427B CN201810710165.6A CN201810710165A CN109119427B CN 109119427 B CN109119427 B CN 109119427B CN 201810710165 A CN201810710165 A CN 201810710165A CN 109119427 B CN109119427 B CN 109119427B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The invention provides a manufacturing method of a back channel etching type TFT substrate and the back channel etching type TFT substrate. The manufacturing method of the back channel etching TFT substrate adopts two silicon oxide layers to cover and protect the back channel of the active layer, firstly forms a first passivation layer of silicon oxide by low-temperature deposition, then forms a second passivation layer of silicon oxide by high-temperature deposition, then processing the surface of the second passivation layer by adopting nitrogen-containing plasma to ensure that the wetting angle of the surface of the second passivation layer is more than 60 degrees, compared with the prior technical scheme of adopting a single silicon oxide layer to cover and protect a back channel, compared with the other prior art which adopts the combination of the silicon oxide layer and the silicon nitride layer to cover and protect the back channel, the back channel etching type oxide TFT does not need to use the silicon nitride layer, the problems of switching of deposition machines of silicon oxide and silicon nitride and etching selection ratio can be avoided, and the manufacturing process is simplified.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of a back channel etching type TFT substrate and the back channel etching type TFT substrate.
Background
In the active matrix display technology, each pixel is driven by a Thin Film Transistor (TFT) integrated behind the pixel, so that a screen display effect with high speed, high brightness and high contrast can be realized. A common TFT is generally composed of three Gate/Source/Drain (Gate/Source/Drain) electrodes, an insulating layer, and a semiconductor layer. The Gate electrode controls the operating region (depletion region or accumulation region) of the semiconductor layer, thereby controlling the switching of the TFT. The semiconductor layer is provided with a Channel, for a TFT with a Back Channel Etched (BCE) structure, the Channel comprises a front conductive Channel attached to a Gate electrode and a Back Channel exposed to the outside, for an N-type doped semiconductor layer, when the Gate electrode is positively biased, the front conductive Channel attached to the Gate electrode (the front conductive Channel and a Gate electrode are separated by an insulating layer) generates accumulation of electrons, the TFT is in an open state, and when the Source/Drain electrode is additionally biased, current passes through the TFT.
In the prior art, the thin film transistor is mainly divided into an amorphous silicon (a-Si) thin film transistor, a low Temperature polysilicon (L w Temperature Poly-silicon, L TPS) thin film transistor and an Oxide semiconductor (Oxide semiconductor) thin film transistor according to the material of an active layer, the Oxide semiconductor thin film transistor (Oxide TFT) has high electron mobility, and compared with the low Temperature polysilicon thin film transistor, the Oxide semiconductor thin film transistor has a simple process and high compatibility with the amorphous silicon thin film transistor process, and is widely used.
In order to improve the stability of the TFT, a TFT having an Etch Stop layer (Etch Stop L a yer, ES L) structure is widely used, which can effectively reduce the influence of the etching damage of the source and drain electrodes on the back channel due to external environmental factors, however, the array manufacturing method of the ES L structure requires more mask times and significantly increases the size and parasitic capacitance of the TFT device.
As shown in fig. 1, the conventional BCE-type TFT substrate structure uses an inorganic insulating cover layer 200 of silicon oxide (SIOx) to cover and protect the back channel of the active layer 100, but a single layer of silicon oxide cannot isolate water and oxygen, and the TFT device characteristics are still poor, as shown in fig. 2, in the conventional BCE-type TFT substrate structure, the inorganic insulating cover layer 200 uses a double-layer film structure of a stack of silicon oxide layers and silicon nitride (SiNx) layers, which has problems of switching between silicon oxide and silicon nitride deposition machines and etching selectivity.
Disclosure of Invention
The invention aims to provide a manufacturing method of a back channel etching type TFT substrate, which uses two silicon oxide layers to cover and protect an active layer back channel, can improve the action of resistance moisture of a back channel etching type oxide TFT, improves the electrical property of the TFT, and simultaneously achieves the purpose of simplifying the process.
The invention also provides a back channel etching TFT substrate, wherein two silicon oxide layers are used for covering and protecting the back channel of an active layer, so that the effect of the back channel etching oxide TFT on resisting moisture can be improved, the electrical property of the TFT can be improved, and the purpose of simplifying the process can be achieved.
In order to achieve the above object, the present invention provides a method for manufacturing a back channel etching TFT substrate, comprising the steps of:
step S1, providing a substrate, forming a gate on the substrate, forming a gate insulating layer on the gate and the substrate, forming an active layer on the gate insulating layer corresponding to the upper side of the gate, and forming a source and a drain on the active layer and the gate insulating layer, wherein the source and the drain are respectively in contact with two sides of the active layer;
step S2, depositing a first passivation layer on the source electrode, the drain electrode, the active layer and the gate insulating layer, and depositing a second passivation layer on the first passivation layer, wherein the first passivation layer and the second passivation layer are both silicon oxide layers, the deposition temperature of the first passivation layer is lower than that of the second passivation layer, and the oxygen content of the second passivation layer is greater than that of the first passivation layer;
and step S3, processing the surface of the second passivation layer by adopting nitrogen-containing plasma.
The material of the active layer is metal oxide semiconductor.
The active layer is made of indium gallium zinc oxide.
The wetting angle of the surface of the second passivation layer is greater than 60 degrees.
The thickness of the first passivation layer is greater than the thickness of the second passivation layer.
The invention also provides a back channel etching type TFT substrate, which comprises a substrate, a grid arranged on the substrate, a grid insulating layer arranged on the grid and the substrate, an active layer arranged on the grid insulating layer and corresponding to the upper part of the grid, a source electrode and a drain electrode which are arranged on the active layer and the grid insulating layer and respectively contacted with two sides of the active layer, a first passivation layer arranged on the source electrode, the drain electrode, the active layer and the grid insulating layer, and a second passivation layer arranged on the first passivation layer;
the first passivation layer and the second passivation layer are silicon oxide layers formed by deposition, the deposition temperature of the first passivation layer is lower than that of the second passivation layer, and the oxygen content of the second passivation layer is greater than that of the first passivation layer;
and the surface of the second passivation layer is subjected to nitrogen-containing plasma treatment.
The material of the active layer is metal oxide semiconductor.
The active layer is made of indium gallium zinc oxide.
The wetting angle of the surface of the second passivation layer is greater than 60 degrees.
The thickness of the first passivation layer is greater than the thickness of the second passivation layer.
The invention has the beneficial effects that: the invention provides a method for manufacturing a back channel etching TFT substrate, which comprises the steps of respectively forming a first passivation layer and a second passivation layer by depositing silicon oxide layers twice, wherein the first passivation layer in contact with an active layer back channel selects a deposition parameter with a lower temperature, the second passivation layer far away from the back channel selects a deposition parameter with a higher temperature, the oxygen content in the second passivation layer is higher than that of the first passivation layer, and after the second passivation layer is formed by deposition, nitrogen-containing plasma is adopted to process the surface of the second passivation layer, so that the wetting angle of the surface of the second passivation layer is more than 60 degrees, compared with the prior technical scheme of adopting a single silicon oxide layer to cover and protect the back channel, the method can improve the water vapor resistance effect of the back channel etching oxide TFT and improve the electrical property of the TFT, compared with the other prior technical scheme of adopting the combination of the silicon oxide layer and the silicon nitride layer to cover and protect the back channel, the silicon nitride layer is not needed, the problems of switching of silicon oxide and silicon nitride deposition machines and etching selection ratio can be avoided, and the manufacturing process is simplified. According to the back channel etching type TFT substrate provided by the invention, the active layer back channel is covered and protected by the two silicon oxide layers, so that the action of the resistance moisture of the back channel etching type oxide TFT can be improved, the electrical property of the TFT is improved, and the purpose of simplifying the process is achieved.
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic structural diagram of a conventional back channel etching TFT substrate;
FIG. 2 is a schematic structural diagram of another conventional back channel etching TFT substrate;
FIG. 3 is a schematic flow chart of a method for fabricating a back channel etched TFT substrate according to the present invention;
FIG. 4 is a schematic view of step S1 of the method for fabricating a back channel etched TFT substrate according to the present invention;
FIG. 5 is a schematic view of step S2 of the method for fabricating a back channel etched TFT substrate according to the present invention;
FIG. 6 is a schematic view of step S3 of the method for fabricating a back channel etched TFT substrate according to the present invention;
FIG. 7 is a schematic structural view of a back channel etched TFT substrate according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 3, the present invention first provides a method for fabricating a back channel etched TFT substrate, which includes the following steps:
step S1, as shown in fig. 4, providing a substrate 10, forming a gate 11 on the substrate 10, forming a gate insulating layer 12 on the gate 11 and the substrate 10, forming an active layer 20 on the gate insulating layer 12 corresponding to the upper side of the gate 11, forming a source 31 and a drain 32 on the active layer 20 and the gate insulating layer 12, wherein the source 31 and the drain 32 are respectively in contact with two sides of the active layer 20.
Specifically, the material of the active layer 20 is a metal oxide semiconductor.
Preferably, the material of the active layer 20 is Indium Gallium Zinc Oxide (IGZO).
Specifically, the active layer 20 includes source and drain contact regions at two ends and a channel region in the middle, the source 31 and the drain 32 are respectively in contact with the source and drain contact regions of the active layer 20, and the surface of the channel region is a back channel.
Step S2, as shown in fig. 5, depositing a first passivation layer 41 on the source electrode 31, the drain electrode 32, the active layer 20 and the gate insulating layer 12, and depositing a second passivation layer 42 on the first passivation layer 41, wherein both the first passivation layer 41 and the second passivation layer 42 are silicon oxide layers, the deposition temperature of the first passivation layer 41 is lower than that of the second passivation layer 42, and the oxygen content of the second passivation layer 42 is greater than that of the first passivation layer 41.
Specifically, the thickness of the first passivation layer 41 is greater than the thickness of the second passivation layer 42.
Specifically, the thickness of the first passivation layer 41 is 100-250 nm.
Specifically, the thickness of the second passivation layer 42 is 50 to 150 nm.
Step S3, as shown in fig. 6, immediately after the second passivation layer 42 is deposited, the surface of the second passivation layer 42 is treated with a nitrogen-containing plasma.
Specifically, after the surface of the second passivation layer 42 is treated by the nitrogen-containing plasma, the wetting angle of the surface of the second passivation layer 42 is greater than 60 °.
Specifically, ammonia (NH) gas is used in step S33) And nitrogen (N)2) The surface of the second passivation layer 42 is treated by forming a nitrogen-containing Plasma in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus as a reaction gas,
according to the manufacturing method of the back channel etching type TFT substrate, the first passivation layer 41 and the second passivation layer 42 are respectively formed by depositing the silicon oxide layer twice, wherein the first passivation layer 41 in contact with the back channel of the active layer 20 selects deposition parameters with a lower temperature (L T), the second passivation layer 42 far away from the back channel selects deposition parameters with a Higher Temperature (HT), the oxygen content in the second passivation layer 42 is higher than that of the first passivation layer 41, the surface of the second passivation layer 42 is treated by adopting nitrogen-containing plasma immediately after the second passivation layer 42 is formed by deposition, so that the wetting angle of the surface of the second passivation layer 42 is more than 60 degrees.
Referring to fig. 7, based on the above method for manufacturing the back channel etching TFT substrate, the present invention further provides a back channel etching TFT substrate, which includes a substrate 10, a gate 11 disposed on the substrate 10, a gate insulating layer 12 disposed on the gate 11 and the substrate 10, an active layer 20 disposed on the gate insulating layer 12 and corresponding to the upper portion of the gate 11, a source 31 and a drain 32 disposed on the active layer 20 and the gate insulating layer 12 and respectively contacting two sides of the active layer 20, a first passivation layer 41 disposed on the source 31, the drain 32, the active layer 20 and the gate insulating layer 12, and a second passivation layer 42 disposed on the first passivation layer 41;
the first passivation layer 41 and the second passivation layer 42 are both formed by deposition, the deposition temperature of the first passivation layer 41 is lower than that of the second passivation layer 42, and the oxygen content of the second passivation layer 42 is greater than that of the first passivation layer 41;
the surface of the second passivation layer 42 is treated with nitrogen-containing plasma.
Specifically, after the surface of the second passivation layer 42 is treated by the nitrogen-containing plasma, the wetting angle of the surface of the second passivation layer 42 is greater than 60 °.
Specifically, the material of the active layer 20 is a metal oxide semiconductor.
Preferably, the material of the active layer 20 is indium gallium zinc oxide.
Specifically, the active layer 20 includes source and drain contact regions at two ends and a channel region in the middle, the source 31 and the drain 32 are respectively in contact with the source and drain contact regions of the active layer 20, and the surface of the channel region is a back channel.
Specifically, the thickness of the first passivation layer 41 is greater than the thickness of the second passivation layer 42.
Specifically, the thickness of the first passivation layer 41 is 100-250 nm.
Specifically, the thickness of the second passivation layer 42 is 50 to 150 nm.
According to the back channel etching type TFT substrate, two silicon oxide layers formed by deposition are respectively used as a first passivation layer 41 and a second passivation layer 42 to cover and protect a back channel of an active layer 20, wherein the deposition temperature of the first passivation layer 41 is lower than that of the second passivation layer 42, the oxygen content of the second passivation layer 42 is larger than that of the first passivation layer 41, and the surface of the second passivation layer 42 is subjected to nitrogen-containing plasma treatment, so that the wetting angle of the surface of the second passivation layer 42 is more than 60 degrees, the effect of resistance moisture of a back channel etching type oxide TFT can be improved, the electric property of the TFT can be improved, and the purpose of simplifying the process can be achieved.
In summary, in the method for manufacturing a back channel etching TFT substrate according to the present invention, a first passivation layer and a second passivation layer are respectively formed by depositing silicon oxide layers twice, wherein the first passivation layer contacting with the back channel of the active layer is selected to have a lower temperature deposition parameter, the second passivation layer farther from the back channel is selected to have a higher temperature deposition parameter, and the oxygen content in the second passivation layer is higher than that of the first passivation layer, and after the second passivation layer is formed by deposition, the surface of the second passivation layer is processed by using a nitrogen-containing plasma, so that the wetting angle of the surface of the second passivation layer is above 60 °. The silicon nitride layer is not needed, the problems of switching of silicon oxide and silicon nitride deposition machines and etching selection ratio can be avoided, and the manufacturing process is simplified. According to the back channel etching type TFT substrate provided by the invention, the active layer back channel is covered and protected by the two silicon oxide layers, so that the action of the resistance moisture of the back channel etching type oxide TFT can be improved, the electrical property of the TFT is improved, and the purpose of simplifying the process is achieved.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (8)
1. A method for manufacturing a back channel etching TFT substrate is characterized by comprising the following steps:
step S1, providing a substrate (10), forming a gate electrode (11) on the substrate (10), forming a gate insulating layer (12) on the gate electrode (11) and the substrate (10), forming an active layer (20) on the gate insulating layer (12) corresponding to the upper part of the gate electrode (11), forming a source electrode (31) and a drain electrode (32) on the active layer (20) and the gate insulating layer (12), wherein the source electrode (31) and the drain electrode (32) are respectively contacted with two sides of the active layer (20);
step S2, depositing a first passivation layer (41) on the source electrode (31), the drain electrode (32), the active layer (20) and the gate insulating layer (12), and depositing a second passivation layer (42) on the first passivation layer (41), wherein the first passivation layer (41) and the second passivation layer (42) are both silicon oxide layers, the deposition temperature of the first passivation layer (41) is lower than that of the second passivation layer (42), and the oxygen content of the second passivation layer (42) is greater than that of the first passivation layer (41);
step S3, processing the surface of the second passivation layer (42) by adopting nitrogen-containing plasma;
the thickness of the first passivation layer (41) is greater than the thickness of the second passivation layer (42).
2. The method of fabricating a back channel etched TFT substrate as set forth in claim 1, wherein the active layer (20) is made of a metal oxide semiconductor.
3. The method of fabricating the back channel etched TFT substrate as claimed in claim 2, wherein the active layer (20) is indium gallium zinc oxide.
4. The method of fabricating a back channel etched TFT substrate as claimed in claim 1, wherein the wetting angle of the surface of the second passivation layer (42) is greater than 60 °.
5. A back channel etching type TFT substrate is characterized by comprising a substrate (10), a grid electrode (11) arranged on the substrate (10), a grid electrode insulating layer (12) arranged on the grid electrode (11) and the substrate (10), an active layer (20) arranged on the grid electrode insulating layer (12) and corresponding to the upper part of the grid electrode (11), a source electrode (31) and a drain electrode (32) which are arranged on the active layer (20) and the grid electrode insulating layer (12) and respectively contacted with two sides of the active layer (20), a first passivation layer (41) arranged on the source electrode (31), the drain electrode (32), the active layer (20) and the grid electrode insulating layer (12), and a second passivation layer (42) arranged on the first passivation layer (41);
the first passivation layer (41) and the second passivation layer (42) are both formed by deposition, the deposition temperature of the first passivation layer (41) is lower than that of the second passivation layer (42), and the oxygen content of the second passivation layer (42) is greater than that of the first passivation layer (41);
the surface of the second passivation layer (42) is treated by nitrogen-containing plasma;
the thickness of the first passivation layer (41) is greater than the thickness of the second passivation layer (42).
6. The back-channel etched TFT substrate according to claim 5, wherein the material of the active layer (20) is a metal oxide semiconductor.
7. The back channel etched TFT substrate according to claim 6, wherein the active layer (20) is indium gallium zinc oxide.
8. The back channel etched TFT substrate according to claim 5, wherein a wetting angle of the surface of the second passivation layer (42) is greater than 60 °.
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| CN201810710165.6A CN109119427B (en) | 2018-07-02 | 2018-07-02 | Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate |
| PCT/CN2018/113263 WO2020006945A1 (en) | 2018-07-02 | 2018-11-01 | Back channel etched tft substrate manufacturing method and back channel etched tft substrate |
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| CN201810710165.6A CN109119427B (en) | 2018-07-02 | 2018-07-02 | Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate |
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| CN109920729B (en) * | 2019-03-27 | 2022-12-02 | 合肥鑫晟光电科技有限公司 | Preparation method of display substrate and display device |
| CN112458427B (en) * | 2020-11-05 | 2023-05-30 | 歌尔微电子股份有限公司 | Preparation method of chip passivation layer, chip passivation layer and chip |
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| CN1395288A (en) * | 2001-07-03 | 2003-02-05 | 联华电子股份有限公司 | Method for preventing low dielectric constant dielectric layer from deteriorating in the course of removing photoresistance |
| CN107946364A (en) * | 2017-10-24 | 2018-04-20 | 华南理工大学 | Inorganic, metal oxide thin film transistor (TFT) and its manufacture method with compound crystal form |
| CN107978607A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | The production method for carrying on the back channel etch type oxide semiconductor TFT substrate |
| CN107978560A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | Carry on the back channel etch type TFT substrate and preparation method thereof |
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| KR101844953B1 (en) * | 2011-03-02 | 2018-04-04 | 삼성디스플레이 주식회사 | Thin film transistor display panel and the method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1395288A (en) * | 2001-07-03 | 2003-02-05 | 联华电子股份有限公司 | Method for preventing low dielectric constant dielectric layer from deteriorating in the course of removing photoresistance |
| CN107946364A (en) * | 2017-10-24 | 2018-04-20 | 华南理工大学 | Inorganic, metal oxide thin film transistor (TFT) and its manufacture method with compound crystal form |
| CN107978607A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | The production method for carrying on the back channel etch type oxide semiconductor TFT substrate |
| CN107978560A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | Carry on the back channel etch type TFT substrate and preparation method thereof |
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