CN109119427A - Carry on the back the production method and back channel etch type TFT substrate of channel etch type TFT substrate - Google Patents
Carry on the back the production method and back channel etch type TFT substrate of channel etch type TFT substrate Download PDFInfo
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- CN109119427A CN109119427A CN201810710165.6A CN201810710165A CN109119427A CN 109119427 A CN109119427 A CN 109119427A CN 201810710165 A CN201810710165 A CN 201810710165A CN 109119427 A CN109119427 A CN 109119427A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The present invention provides the production method and back channel etch type TFT substrate of a kind of back channel etch type TFT substrate.The production method of back channel etch type TFT substrate of the invention, covering protection is carried out to active layer back channel using two layers of silicon oxide layer, first low temperature depositing forms the first passivation layer of silica, high temperature deposition forms the second passivation layer of silica again, then the second passivation layer surface is handled using containing nitrogen plasma, make the angle of wetting of the second passivation layer surface at 60 ° or more, compared to the prior art for carrying out covering protection to back channel using mono-layer oxidized silicon layer, the effect of back channel etch type oxide TFT impedance aqueous vapor can be promoted, it is electrical to promote TFT, another prior art of covering protection is carried out to back channel compared to the combination using silicon oxide layer and silicon nitride layer, without using silicon nitride layer, can be to avoid the deposition machine switching problem and etching selectivity of silica and silicon nitride the problem of , simplify manufacture craft.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of production methods and back for carrying on the back channel etch type TFT substrate
Channel etch type TFT substrate.
Background technique
In Active Matrix LCD At technology, each pixel is by thin film transistor (TFT) integrated behind (Thin Film
Transistor, TFT) it is driven, so as to realize the Showing Effectiveness On Screen of high speed, high brightness, high contrast.It is common
TFT be usually made of three electrode of gate/source/drain electrode (Gate/Source/Drain), insulating layer and semiconductor layer.
Gate electrode controls the working region (depletion region or accumulation area) of semiconductor layer, to control the switch of TFT.It is described partly to lead
Body layer is equipped with channel, for the TFT for carrying on the back channel etching (Back Channel Ethced, BCE) structure, the channel
Including being close to the preceding conducting channel of Gate electrode and being exposed to extraneous back channel, for n-type doping semiconductor layer, when
Gate electrode adds positive bias, and the preceding conducting channel (preceding conducting channel and gate electrode are separated by insulating layer) for being close to Gate electrode generates
The accumulation of electronics, TFT is in the open state, when Source/Drain electrode increases bias, has electric current to pass through in TFT.
Thin film transistor (TFT) is broadly divided into amorphous silicon (a-Si) thin film transistor (TFT), low according to the material of active layer in the prior art
Warm polysilicon (Low Temperature Poly-silicon, LTPS) thin film transistor (TFT) and oxide semiconductor (Oxide
Semiconductor) thin film transistor (TFT), oxide semiconductor thin-film transistor (Oxide TFT) is due to electronics with higher
Mobility, and low-temperature polysilicon film transistor is compared, oxide semiconductor thin-film transistor processing procedure is simple, thin with amorphous silicon
Film transistor process-compatible is higher, and is widely applied.Under the conditions of low resistance contact, the high migration of oxide semiconductor
Rate can be sheltered by high contact resistance, in addition, when oxide thin film transistor use BCE structure when, channel location it is active
Layer is not protected, and is easy to lose characteristic of semiconductor during processing procedure, and then lead to oxide semiconductor thin-film transistor
Switching characteristic failure.
Although for from spatial position, TFT back channel is distant with a distance from preceding conducting channel, and TFT carries on the back channel
The property at interface also has vital influence to TFT output electric property curve.For the TFT for carrying on the back channel etching structure,
Back channel can be caused to damage during channel quarter is held, also, the back channel damaged is exposed in air, it is easier to cause
Due to the absorption of water/oxygen back channel in generate defect, cause degeneration of TFT characteristic curve during stability test with
And the promotion of electric leakage, device stability reduce.In order to improve the stability of TFT, etching barrier layer (Etch Stop Layer,
ESL) TFT of structure is widely adopted, which can effectively reduce the etching injury of outside environmental elements and source-drain electrode to back
The influence of channel.However, the array manufacturing method of ESL structure needs more light shield numbers, and significantly increase TFT device
Size and parasitic capacitance.
And the TFT for carrying on the back channel etch type structure is not necessarily to etch stop layer, channel can be reduced significantly compared with ESL structure, thus be had
There are the lower production cost of opposite ESL structure and technical advantage.As shown in Figure 1, a kind of existing BCE type TFT substrate structure uses
The inorganic insulation coating 200 of silica (SIOx) gets up the back channel covering protection of active layer 100, however the oxidation of single layer
Silicon can not play the role of completely cutting off water oxygen, and TFT device property is still poor.As shown in Fig. 2, existing another kind BCE type TFT substrate knot
Structure, the double membrane structure of inorganic insulation coating 200 use silicon oxide layer and silicon nitride (SiNx) layer stack, however this kind of structure
There are problems that silica and nitride deposition board switching problem and etching selectivity.
Summary of the invention
The purpose of the present invention is to provide a kind of production methods for carrying on the back channel etch type TFT substrate, use two layers of silica
Layer covering protection active layer carries on the back channel, can promote the effect of back channel etch type oxide TFT impedance aqueous vapor, promotes TFT electrical property,
And achieve the purpose that simplified technique simultaneously.
The object of the invention is also to provide a kind of back channel etch type TFT substrates, are protected using two layers of silicon oxide layer covering
It protects active layer and carries on the back channel, the effect of back channel etch type oxide TFT impedance aqueous vapor can be promoted, it is electrical to promote TFT, and reach simultaneously
To the purpose for simplifying technique.
To achieve the above object, the present invention provides a kind of production method for carrying on the back channel etch type TFT substrate, including walks as follows
It is rapid:
Step S1, a underlay substrate is provided, forms grid on the underlay substrate, on the grid and underlay substrate
Gate insulating layer is formed, the active layer corresponded to above the grid is formed on the gate insulating layer, in the active layer
With formation source electrode on gate insulating layer and drain electrode, the source electrode is in contact with the two sides of the active layer respectively with drain electrode；
Step S2, on the source electrode, drain electrode, active layer and gate insulating layer, deposition forms the first passivation layer, described
Deposition forms the second passivation layer on first passivation layer, wherein first passivation layer and the second passivation layer are silicon oxide layer, institute
The depositing temperature for stating the first passivation layer is lower than the depositing temperature of the second passivation layer, and the oxygen content of second passivation layer is greater than described
The oxygen content of first passivation layer；
Step S3, second passivation layer surface is handled using containing nitrogen plasma.
The material of the active layer is metal-oxide semiconductor (MOS).
The material of the active layer is indium gallium zinc oxide.
The angle of wetting of second passivation layer surface is greater than 60 °.
The thickness of first passivation layer is greater than the thickness of the second passivation layer.
The present invention also provides a kind of back channel etch type TFT substrates, including underlay substrate, on the underlay substrate
Grid, is set on the gate insulating layer and corresponds to the grid gate insulating layer on the grid and underlay substrate
Active layer above pole, set on the active layer and the source that is in contact on gate insulating layer and respectively with the two sides of the active layer
Pole is blunt with drain electrode, the first passivation layer on the source electrode, drain electrode, active layer and gate insulating layer and set on described first
Change the second passivation layer on layer；
First passivation layer and the second passivation layer are the silicon oxide layer that deposition is formed, the deposition of first passivation layer
Temperature is lower than the depositing temperature of the second passivation layer, and the oxygen that the oxygen content of second passivation layer is greater than first passivation layer contains
Amount；
Second passivation layer surface, which is passed through, contains nitrogen plasma treatment.
The material of the active layer is metal-oxide semiconductor (MOS).
The material of the active layer is indium gallium zinc oxide.
The angle of wetting of second passivation layer surface is greater than 60 °.
The thickness of first passivation layer is greater than the thickness of the second passivation layer.
Beneficial effects of the present invention: a kind of production method for carrying on the back channel etch type TFT substrate provided by the invention passes through two
Secondary silicon oxide layer deposited is respectively formed the first passivation layer and the second passivation layer, wherein the first passivation contacted with active layer back channel
Deposition parameter of the layer choosing compared with low temperature selects the deposition parameter of higher temperatures with farther away second passivation layer of back channel, and second is blunt
Change the oxygen content in layer and be higher than the first passivation layer, and after deposition forms the second passivation layer using containing nitrogen plasma to described the
Two passivation layer surfaces are handled, and make the angle of wetting of second passivation layer surface at 60 ° or more, compared to using mono-layer oxidized
Silicon layer carries out the prior art of covering protection to back channel, can promote back channel etch type oxide TFT impedance aqueous vapor
Effect promotes TFT electrical property, carries out the another of covering protection to back channel compared to the combination using silicon oxide layer and silicon nitride layer
Prior art can be to avoid the deposition machine switching problem and erosion of silica and silicon nitride without using silicon nitride layer
Carve selection than the problem of, simplify manufacture craft.Back channel etch type TFT substrate provided by the invention, uses two layers of silica
Layer covering protection active layer carries on the back channel, can promote the effect of back channel etch type oxide TFT impedance aqueous vapor, promotes TFT electrical property,
And achieve the purpose that simplified technique simultaneously.
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Detailed description of the invention
With reference to the accompanying drawing, by the way that detailed description of specific embodiments of the present invention, technical solution of the present invention will be made
And other beneficial effects are apparent.
In attached drawing,
Fig. 1 is a kind of existing structural schematic diagram for carrying on the back channel etch type TFT substrate；
Fig. 2 is the structural schematic diagram of existing another back channel etch type TFT substrate；
Fig. 3 present invention carries on the back the flow diagram of the production method of channel etch type TFT substrate；
Fig. 4 is the schematic diagram of the step S1 of the production method of present invention back channel etch type TFT substrate；
Fig. 5 is the schematic diagram of the step S2 of the production method of present invention back channel etch type TFT substrate；
Fig. 6 is the schematic diagram of the step S3 of the production method of present invention back channel etch type TFT substrate；
Fig. 7 is the structural schematic diagram of present invention back channel etch type TFT substrate.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
Referring to Fig. 3, present invention firstly provides a kind of production method for carrying on the back channel etch type TFT substrate, including following step
It is rapid:
Step S1, as shown in figure 4, providing a underlay substrate 10, grid 11 is formed on the underlay substrate 10, described
Gate insulating layer 12 is formed on grid 11 and underlay substrate 10, is formed on the gate insulating layer 12 and is corresponded to the grid 11
The active layer 20 of top, the active layer 20 with form source electrode 31 and drain electrode 32 on gate insulating layer 12, the source electrode 31 with
Drain electrode 32 is in contact with the two sides of the active layer 20 respectively.
Specifically, the material of the active layer 20 is metal-oxide semiconductor (MOS).
Preferably, the material of the active layer 20 be indium gallium zinc oxide (Indium Gallium Zinc Oxide,
IGZO)。
Specifically, the active layer 20 includes being located at the source-drain electrode contact zone at both ends and being located in the middle channel region, described
Source electrode 31 is in contact with the source-drain electrode contact zone of the active layer 20 respectively with drain electrode 32, and the surface of the channel region is to carry on the back ditch
Road.
Step S2, it is formed as shown in figure 5, being deposited on the source electrode 31, drain electrode 32, active layer 20 and gate insulating layer 12
First passivation layer 41, deposition forms the second passivation layer 42 on first passivation layer 41, wherein 41 He of the first passivation layer
Second passivation layer 42 is silicon oxide layer, and the depositing temperature of first passivation layer 41 is lower than the deposition temperature of the second passivation layer 42
Degree, the oxygen content of second passivation layer 42 are greater than the oxygen content of first passivation layer 41.
Specifically, the thickness of first passivation layer 41 is greater than the thickness of the second passivation layer 42.
Specifically, first passivation layer 41 with a thickness of 100-250nm.
Specifically, second passivation layer 42 with a thickness of 50-150nm.
Step S3, it as shown in fig. 6, after deposition forms the second passivation layer 42, uses immediately containing nitrogen plasma to institute
42 surface of the second passivation layer is stated to be handled.
Specifically, 42 surface of the second passivation layer is after containing nitrogen plasma treatment, 42 surface of the second passivation layer
Angle of wetting be greater than 60 °.
Specifically, ammonia (NH is used in the step S33) and nitrogen (N2) be used as reaction gas in plasma enhancing
It is formed in vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) equipment nitrogenous
Plasma is handled to 42 surface of the second passivation layer,
The production method of back channel etch type TFT substrate of the invention is respectively formed the by silicon oxide layer deposited twice
One passivation layer 41 and the second passivation layer 42 are selected wherein carrying on the back the first passivation layer 41 that channel contacts with active layer 20 compared with low temperature (LT)
Deposition parameter, the deposition parameter of higher temperatures (HT), and the second passivation layer 42 are selected with farther away second passivation layer 42 of back channel
In oxygen content be higher than the first passivation layer 41, deposition formed the second passivation layer 42 after immediately using containing nitrogen plasma to described
Second passivation layer, 42 surface is handled, and makes the angle of wetting on 42 surface of the second passivation layer at 60 ° or more, compared to using single
Layer silicon oxide layer carries out the prior art of covering protection to back channel, can promote back channel etch type oxide TFT impedance
The effect of aqueous vapor promotes TFT electrical property, carries out covering protection to back channel compared to the combination using silicon oxide layer and silicon nitride layer
Another prior art can be to avoid the deposition machine switching problem of silica and silicon nitride without using silicon nitride layer
And the problem of etching selectivity, simplify manufacture craft.
Referring to Fig. 7, the production method based on above-mentioned back channel etch type TFT substrate, the present invention also provides a kind of back
Channel etch type TFT substrate including underlay substrate 10, the grid 11 on the underlay substrate 10, is set to the grid 11
With on underlay substrate 10 gate insulating layer 12, on the gate insulating layer 12 and correspond to the grid 11 above having
Active layer 20, set on the active layer 20 and the source electrode that is in contact on gate insulating layer 12 and respectively with the two sides of the active layer 20
31 with drain electrode 32, the first passivation layer 41 on the source electrode 31, drain electrode 32, active layer 20 and gate insulating layer 12 and set
In the second passivation layer 42 on first passivation layer 41；
First passivation layer 41 and the second passivation layer 42 are the silicon oxide layer that deposition is formed, first passivation layer 41
Depositing temperature be lower than the depositing temperature of the second passivation layer 42, the oxygen content of second passivation layer 42 is greater than first passivation
The oxygen content of layer 41；
Second passivation layer, 42 surface, which is passed through, contains nitrogen plasma treatment.
Specifically, 42 surface of the second passivation layer is after containing nitrogen plasma treatment, 42 surface of the second passivation layer
Angle of wetting be greater than 60 °.
Specifically, the material of the active layer 20 is metal-oxide semiconductor (MOS).
Preferably, the material of the active layer 20 is indium gallium zinc oxide.
Specifically, the active layer 20 includes being located at the source-drain electrode contact zone at both ends and being located in the middle channel region, described
Source electrode 31 is in contact with the source-drain electrode contact zone of the active layer 20 respectively with drain electrode 32, and the surface of the channel region is to carry on the back ditch
Road.
Specifically, the thickness of first passivation layer 41 is greater than the thickness of the second passivation layer 42.
Specifically, first passivation layer 41 with a thickness of 100-250nm.
Specifically, second passivation layer 42 with a thickness of 50-150nm.
Back channel etch type TFT substrate of the invention, two layers of the silicon oxide layer formed using deposition are blunt respectively as first
The back channel for changing layer 41 and 42 covering protection active layer 20 of the second passivation layer, wherein the depositing temperature of first passivation layer 41 is low
In the depositing temperature of the second passivation layer 42, the oxygen that the oxygen content of second passivation layer 42 is greater than first passivation layer 41 contains
Amount, 42 surface of the second passivation layer, which is passed through, contains nitrogen plasma treatment, so that the angle of wetting on 42 surface of the second passivation layer is at 60 °
More than, the effect of back channel etch type oxide TFT impedance aqueous vapor can be promoted, it is electrical to promote TFT, and reach simplified technique simultaneously
Purpose.
In conclusion a kind of production method for carrying on the back channel etch type TFT substrate provided by the invention, by depositing oxygen twice
SiClx layer is respectively formed the first passivation layer and the second passivation layer, wherein with active layer back channel contact the first passivation layer selection compared with
The deposition parameter of low temperature selects the deposition parameter of higher temperatures with farther away second passivation layer of back channel, and in the second passivation layer
Oxygen content is higher than the first passivation layer, and uses containing nitrogen plasma after deposition forms the second passivation layer to second passivation layer
Surface is handled, and makes the angle of wetting of second passivation layer surface at 60 ° or more, compared to the mono-layer oxidized silicon layer of use to back
Channel carries out the prior art of covering protection, can promote the effect of back channel etch type oxide TFT impedance aqueous vapor, is promoted
TFT is electrical, carries out another prior art of covering protection to back channel compared to the combination using silicon oxide layer and silicon nitride layer
Scheme can be to avoid the deposition machine switching problem and etching selectivity of silica and silicon nitride without using silicon nitride layer
The problem of, simplify manufacture craft.Back channel etch type TFT substrate provided by the invention is protected using two layers of silicon oxide layer covering
It protects active layer and carries on the back channel, the effect of back channel etch type oxide TFT impedance aqueous vapor can be promoted, it is electrical to promote TFT, and reach simultaneously
To the purpose for simplifying technique.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the claims in the present invention
Protection scope.
Claims (10)
1. a kind of production method for carrying on the back channel etch type TFT substrate, which comprises the following steps:
Step S1, a underlay substrate (10) are provided, grid (11) is formed on the underlay substrate (10), in the grid (11)
With gate insulating layer (12) are formed on underlay substrate (10), on the gate insulating layer (12) formed correspond to the grid
(11) active layer (20) above forms source electrode (31) and drain electrode on the active layer (20) and gate insulating layer (12)
(32), the source electrode (31) is in contact with the two sides of the active layer (20) respectively with drain electrode (32)；
Step S2, on the source electrode (31), drain electrode (32), active layer (20) and gate insulating layer (12), it is blunt to form first for deposition
Change layer (41), deposition forms the second passivation layer (42) on first passivation layer (41), wherein first passivation layer (41)
It is silicon oxide layer with the second passivation layer (42), the depositing temperature of first passivation layer (41) is lower than the second passivation layer (42)
Depositing temperature, the oxygen content of second passivation layer (42) are greater than the oxygen content of first passivation layer (41)；
Step S3, the second passivation layer (42) surface is handled using containing nitrogen plasma.
2. the production method of back channel etch type TFT substrate as described in claim 1, which is characterized in that the active layer
(20) material is metal-oxide semiconductor (MOS).
3. the production method of back channel etch type TFT substrate as claimed in claim 2, which is characterized in that the active layer
(20) material is indium gallium zinc oxide.
4. the production method of back channel etch type TFT substrate as described in claim 1, which is characterized in that second passivation
The angle of wetting on layer (42) surface is greater than 60 °.
5. the production method of back channel etch type TFT substrate as described in claim 1, which is characterized in that first passivation
The thickness of layer (41) is greater than the thickness of the second passivation layer (42).
6. a kind of back channel etch type TFT substrate, which is characterized in that including underlay substrate (10), be set to the underlay substrate
(10) grid (11) on, is set to the grid at the gate insulating layer (12) on the grid (11) and underlay substrate (10)
On pole insulating layer (12) and correspond to the grid (11) above active layer (20), be set to the active layer (20) and grid it is exhausted
The source electrode (31) being in contact in edge layer (12) and respectively with the two sides of the active layer (20) and drain electrode (32) are set to the source electrode
(31), it drains (32), active layer (20) and the first passivation layer (41) on gate insulating layer (12) and to be set to described first blunt
Change the second passivation layer (42) on layer (41)；
First passivation layer (41) and the second passivation layer (42) are the silicon oxide layer that deposition is formed, first passivation layer
(41) depositing temperature is lower than the depositing temperature of the second passivation layer (42), and the oxygen content of second passivation layer (42) is greater than described
The oxygen content of first passivation layer (41)；
Second passivation layer (42) surface, which is passed through, contains nitrogen plasma treatment.
7. back channel etch type TFT substrate as claimed in claim 6, which is characterized in that the material of the active layer (20) is
Metal-oxide semiconductor (MOS).
8. back channel etch type TFT substrate as claimed in claim 7, which is characterized in that the material of the active layer (20) is
Indium gallium zinc oxide.
9. back channel etch type TFT substrate as claimed in claim 6, which is characterized in that the second passivation layer (42) surface
Angle of wetting be greater than 60 °.
10. back channel etch type TFT substrate as claimed in claim 6, which is characterized in that the thickness of first passivation layer (41)
Degree is greater than the thickness of the second passivation layer (42).
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| CN201810710165.6A CN109119427B (en) | 2018-07-02 | 2018-07-02 | Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate |
| PCT/CN2018/113263 WO2020006945A1 (en) | 2018-07-02 | 2018-11-01 | Back channel etched tft substrate manufacturing method and back channel etched tft substrate |
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| CN201810710165.6A CN109119427B (en) | 2018-07-02 | 2018-07-02 | Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate |
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| CN109920729A (en) * | 2019-03-27 | 2019-06-21 | 合肥鑫晟光电科技有限公司 | A kind of preparation method of display base plate, display device |
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| CN112458427B (en) * | 2020-11-05 | 2023-05-30 | 歌尔微电子股份有限公司 | Preparation method of chip passivation layer, chip passivation layer and chip |
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| CN107946364A (en) * | 2017-10-24 | 2018-04-20 | 华南理工大学 | Inorganic, metal oxide thin film transistor (TFT) and its manufacture method with compound crystal form |
| CN107978607A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | The production method for carrying on the back channel etch type oxide semiconductor TFT substrate |
| CN107978560A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | Carry on the back channel etch type TFT substrate and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109920729A (en) * | 2019-03-27 | 2019-06-21 | 合肥鑫晟光电科技有限公司 | A kind of preparation method of display base plate, display device |
| CN109920729B (en) * | 2019-03-27 | 2022-12-02 | 合肥鑫晟光电科技有限公司 | Preparation method of display substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020006945A1 (en) | 2020-01-09 |
| CN109119427B (en) | 2020-07-28 |
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