JP5015471B2 - Thin film transistor and manufacturing method thereof - Google Patents

Thin film transistor and manufacturing method thereof Download PDF

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JP5015471B2
JP5015471B2 JP2006038426A JP2006038426A JP5015471B2 JP 5015471 B2 JP5015471 B2 JP 5015471B2 JP 2006038426 A JP2006038426 A JP 2006038426A JP 2006038426 A JP2006038426 A JP 2006038426A JP 5015471 B2 JP5015471 B2 JP 5015471B2
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insulating film
thin film
interlayer insulating
gate insulating
oxide semiconductor
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守 古田
寛 古田
孝 平尾
孝浩 平松
時宜 松田
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カシオ計算機株式会社
財団法人高知県産業振興センター
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  The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor (hereinafter abbreviated as TFT) having at least an oxide semiconductor thin film layer as an active layer and a manufacturing method thereof.

It has been known for a long time that oxides such as zinc oxide or magnesium zinc oxide exhibit excellent semiconductor (active layer) properties.In recent years, with the aim of application to electronic devices such as thin film transistors, light-emitting devices, transparent conductive films, etc. Research and development of semiconductor thin film layers using compounds has been activated.
TFTs using zinc oxide or magnesium zinc oxide as semiconductor thin film layers are electrons compared to amorphous silicon TFTs using amorphous silicon (a-Si: H), which is mainly used in conventional liquid crystal displays, as semiconductor thin film layers. Active development is underway, with advantages such as high mobility, excellent TFT characteristics, and the expectation of high mobility by obtaining a polycrystalline thin film even at low temperatures near room temperature.

  As TFTs (zinc oxide TFTs) using zinc oxide as an oxide semiconductor thin film layer, bottom-gate and top-gate structures have been reported.

  An example of a bottom-gate structure is a structure in which a gate electrode and a gate insulating film are formed in order from the substrate, and an oxide semiconductor thin film layer mainly composed of zinc oxide is formed covering the upper surface. ing. This structure is similar in manufacturing process to the bottom gate type amorphous silicon TFT currently commercialized as a driving element of a liquid crystal display. Therefore, the structure can be created relatively easily with the production equipment of the amorphous silicon TFT, and is often used as a zinc oxide TFT.

  However, since the bottom gate type thin film transistor has a structure in which an oxide semiconductor thin film layer is stacked on a gate insulating film, an area of initial film formation with insufficient crystallinity must be used as an active layer, There is a problem that sufficient mobility cannot be obtained. On the other hand, a top-gate thin film transistor has a structure in which a gate insulating film is provided over an oxide semiconductor thin film layer, so that a region with good crystallinity above the oxide semiconductor thin film layer can be used as an active layer. This is more effective than a bottom gate type thin film transistor.

As an example of the top gate structure, a structure in which a source / drain electrode, an oxide semiconductor thin film layer, a gate insulating film, and a gate electrode are stacked in this order from the substrate can be exemplified.
However, there is a problem in that the oxide semiconductor thin film layer from the source / drain electrodes to the channel becomes a resistance, and current limiting occurs.
A problem similar to that of a zinc oxide TFT already exists in an amorphous silicon TFT, and the structure shown in FIG. 4 is disclosed as a solution in Patent Document 1 below. In this structure, a pair of source / drain electrodes 102, a semiconductor thin film layer 103, a gate insulating film 104, and a gate electrode 105 are sequentially formed on a substrate 101. Further, the gate insulating film 104 and the gate electrode 105 have the same shape in a self-aligning manner. In addition, impurities are introduced into a region other than the region directly below the gate electrode in the entire thickness direction of the semiconductor thin film layer 103 to form a source / drain region having a lower resistance than the region immediately below the gate electrode. Therefore, the current rate limiting can be suppressed. As a method for forming source / drain regions in an amorphous silicon TFT, ion implantation is performed in which an element that serves as a donor, for example, phosphorus (P), is implanted from the outside in the form of ions into amorphous silicon that is a main component of a semiconductor thin film layer. The law is shown.

However, although a source / drain region with reduced resistance can be formed by such a method, it cannot be said that the resistance of the source / drain region has been sufficiently reduced. Therefore, a parasitic resistance from the source / drain electrodes to the channel cannot be sufficiently suppressed, and a method for further reducing the resistance is desired.
Even if the solution in the above amorphous silicon TFT is applied to a zinc oxide TFT, a source / drain region with a sufficiently low resistance cannot be formed as in the case of an amorphous silicon TFT, and from the source / drain electrode to the channel. There arises a problem that the parasitic resistance of is not sufficiently suppressed.

Japanese Patent Laid-Open No. 8-51209

The present invention has been made in view of the above problems, and the problems to be solved are as follows. First, a processing method for reducing resistance different from the conventional one is established. In addition, by using the low resistance method in combination with other low resistance methods, a sufficiently low source / drain region is formed. Thus, the parasitic capacitance between the gate electrode and the source / drain regions is reduced, and a high-speed thin film transistor is provided. In addition, the parasitic resistance from the source / drain region to the channel is reduced, and the occurrence of current rate control is suppressed.
In addition, the resistance of the source / drain region is selectively reduced, and an increase in leakage current due to a decrease in resistance of the channel region is prevented.

The invention according to claim 1 is an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on an insulating substrate, a gate insulating film formed on the oxide semiconductor thin film layer, and the gate insulation A gate electrode stacked on the film; and an interlayer insulating film covering at least a region of the oxide semiconductor thin film layer not covered with the gate insulating film, wherein the gate insulating film and the gate electrode are self-aligned. In particular, the present invention relates to a thin film transistor characterized in that the interlayer insulating film contains hydrogen, and the hydrogen concentration in the interlayer insulating film is higher than the hydrogen concentration in the gate insulating film .

The invention according to claim 2 includes a step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on a substrate, and a step of covering the oxide semiconductor thin film layer to form a gate insulating film. In a method of manufacturing a thin film transistor including a step of loading a gate electrode on the gate insulating film, the gate insulating film is etched using the gate electrode as a mask, and hydrogen is contained on a region exposed by the etching process The present invention relates to a method of manufacturing a thin film transistor , wherein the resistance is reduced by forming an interlayer insulating film to form a source / drain region, and the hydrogen concentration in the interlayer insulating film is higher than the hydrogen concentration in the gate insulating film .

According to a third aspect of the present invention, a plasma CVD method is used for forming the interlayer insulating film, and the substrate is exposed to plasma by hydrogen or a gas containing hydrogen as a constituent element before forming the interlayer insulating film. 3. The method of manufacturing a thin film transistor according to claim 2 , wherein the thin film transistor is a thin film transistor.

Invention, the interlayer by plasma CVD to deposit the insulating film, according to claim 2 or 3, wherein the forming the interlayer insulating film while applying high frequency power to the substrate side according to claim 4 The present invention relates to a method for manufacturing a thin film transistor.
The invention according to claim 5 is a step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on a substrate, and a step of covering the oxide semiconductor thin film layer to form a gate insulating film. In a method of manufacturing a thin film transistor including a step of loading a gate electrode on the gate insulating film, the gate insulating film is etched using the gate electrode as a mask, and hydrogen is contained on a region exposed by the etching process Lowering the resistance by forming an interlayer insulating film to form source / drain regions, using the plasma CVD method for forming the interlayer insulating film, and containing hydrogen or hydrogen as a constituent element before forming the interlayer insulating film The present invention relates to a method for manufacturing a thin film transistor, characterized in that the substrate is exposed to a plasma by a gas.

According to the first aspect of the present invention, the gate insulating film and the gate electrode are formed in the same shape in a self-aligned manner. It exists in the position aligned in the direction, and the parasitic capacitance between the source / drain region and the gate electrode is reduced, and the operation speed can be improved.
Further, by containing hydrogen in the interlayer insulating film, the hydrogen concentration of the oxide semiconductor thin film layer covered with the interlayer insulating film can be increased. Accordingly, the resistance of the oxide semiconductor thin film layer covered with the interlayer insulating film can be reduced, and the source / drain regions with reduced resistance can be formed. Therefore, resistance from the source / drain electrodes to the channel can be suppressed, and current rate control can be suppressed. Further, the resistance of the source / drain region can be further reduced by separately performing other resistance reduction processing such as ion implantation. Therefore, the resistance from the source / drain electrodes to the channel can be further suppressed, and the current rate can be sufficiently suppressed.

According to the first aspect of the present invention, by making the hydrogen concentration in the interlayer insulating film larger than the hydrogen concentration in the gate insulating film, the resistance of the source / drain region can be selectively lowered, and the resistance of the channel region is reduced. An increase in leakage current can be prevented.

According to the second aspect of the present invention, the gate insulating film is etched using the gate electrode as a mask to form the source / drain electrodes, so that the inner ends of the source / drain regions and both ends of the gate electrodes are in the film thickness direction. As a result, the parasitic capacitance between the source / drain regions and the gate electrode is reduced, and the operation speed can be improved.
By forming an interlayer insulating film containing hydrogen over the area exposed by the etching process, the resistance from the source / drain electrodes to the channel is reduced by reducing the resistance and forming the source / drain regions, thereby limiting the current rate. Can be suppressed. Further, the resistance of the source / drain region can be further reduced by separately performing other resistance reduction processing such as ion implantation.
Therefore, the resistance from the source / drain electrodes to the channel can be further suppressed, and the current rate can be sufficiently suppressed.

According to the second aspect of the present invention, since the hydrogen concentration in the interlayer insulating film is larger than the hydrogen concentration in the gate insulating film, the range exposed by the etching process is selectively reduced to reduce the source / drain region. It can be formed, and an increase in leakage current accompanying a decrease in resistance of the channel region can be prevented.

  According to the invention of claim 5, the interlayer insulating film is coated by exposing the substrate to plasma of hydrogen or a gas containing hydrogen as a constituent element, and then forming the interlayer insulating film using a plasma CVD method. Hydrogen can be efficiently introduced by the oxide semiconductor thin film layer, a source / drain region with reduced resistance can be efficiently formed, and an increase in leakage current can be prevented.

According to the fourth aspect of the present invention, the plasma CVD method is used for forming the interlayer insulating film, and the ion energy in the plasma can be increased by forming the interlayer insulating film while applying high frequency power to the substrate side. In addition, hydrogen can be introduced into a deeper region in the oxide semiconductor thin film layer, and an increase in leakage current can be prevented.

Hereinafter, embodiments of the TFT of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a first embodiment of a TFT according to the present invention.

  A thin film transistor 100 according to the first embodiment of the present invention includes a substrate 1, a pair of source / drain electrodes 2, an oxide semiconductor thin film layer 3, a gate insulating film 4, a gate electrode 6, an interlayer insulating film 7, a contact portion 8a, It has a pair of source / drain external electrodes 2a and a display electrode 9, and is formed by laminating these components as shown in FIG. 1, and is usually called a stagger type.

As shown in FIG. 1, the thin film transistor 100 is formed on a substrate 1 made of glass (non-alkali glass containing SiO 2 and Al 2 O 3 as main components).
The material of the substrate 1 is not limited to glass, and any material can be used as long as it is an insulator such as a plastic or metal foil coated with an insulator.

A pair of source / drain electrodes 2 are stacked on the substrate 1. The pair of source / drain electrodes 2 are disposed on the upper surface of the substrate 1 with a gap.
The pair of source / drain electrodes 2 are formed of, for example, a conductive oxide such as indium tin oxide (ITO) or n + ZnO, a metal, or a metal at least partially covered with the conductive oxide.

The oxide semiconductor thin film layer 3 is disposed so as to form a channel between the pair of source / drain electrodes 2, and is formed of an oxide semiconductor containing zinc oxide as a main component. Here, the oxide semiconductor containing zinc oxide as a main component is doped with intrinsic zinc oxide, p-type dopants such as Li, Na, N, and C, and n-type dopants such as B, Al, Ga, and In. And zinc oxide doped with Mg, Be and the like.
The oxide semiconductor thin film layer 3 includes a channel region 31 and a pair of source / drain regions 32. The channel region 31 is a range used as a channel of the oxide semiconductor thin film layer 3. The source / drain region 32 is a region formed in a region other than the channel region 31 in a self-aligned manner and having a lower resistance than the channel region 31. In the case of the present invention, the resistance reduction is performed by coating the interlayer insulating film 7.
By providing the source / drain regions 32, the resistance from the source / drain electrodes to the channel can be suppressed, and the current rate can be suppressed.
Although the thickness of this oxide semiconductor thin film layer 3 is not specifically limited, For example, it forms in about 25-200 nm, Preferably, it forms in about 50-100 nm. In FIG. 1, the source / drain region 32 is illustrated such that the thickness of the portion formed on each source / drain electrode 2 is thinner than the portion formed between the pair of source / drain electrodes 2. However, this is merely for the convenience of illustration, and in fact, the thicknesses of both are almost the same.

The gate insulating film 4 is formed so as to cover only the upper surface of the channel region 31 of the oxide semiconductor thin film layer 3.
The gate insulating film 4 is a silicon oxide (SiOx) film, silicon oxynitride (SiON) film, silicon nitride (SiNx) film, or silicon nitride (SiNx) doped with oxygen using oxygen or a compound containing oxygen as a constituent element. It is formed by a film. The gate insulating film 4 has a dielectric constant larger than that of a silicon oxide compound (SiOx) or silicon oxynitride (SiON), and a compound containing oxygen or oxygen as a constituent element in silicon nitride (SiNx), for example, nitrogen oxide (N 2 A film doped with oxygen using O) is preferably used. Accordingly, the thin film transistor has a high dielectric constant and is excellent from the viewpoint of protecting the oxide semiconductor thin film layer.

The gate electrode 6 is formed on the gate insulating film 4. The gate electrode 6 serves to control the electron density in the oxide semiconductor thin film layer 3 by a gate voltage applied to the thin film transistor.
The gate electrode 6 is made of a metal film exemplified by Cr and Ti.
Further, both ends of the gate electrode 6 exist at positions aligned with the inner ends of the source / drain regions in the film thickness direction. Thereby, parasitic capacitance is not generated between the source / drain regions and the gate electrode, and the operation speed can be improved.
In addition, it is preferable that both end portions of the gate electrode 6 are located inside the inner end portions of the source / drain electrodes. Thereby, the parasitic capacitance between the gate electrode 6 and the source / drain electrode 2 is not generated, and the operation speed can be improved.

The interlayer insulating film 7 is laminated so as to cover the entire surface of the pair of source / drain electrodes 2 and the gate electrode 6.
The interlayer insulating film 7 contains hydrogen. Accordingly, the resistance of the oxide semiconductor thin film layer covered with the interlayer insulating film 7 can be reduced.
It is preferable that the hydrogen concentration of the interlayer insulating film 7 is higher than the hydrogen concentration of the gate insulating film 4. As a result, the resistance of the pair of source / drain regions 32 that are the oxide semiconductor thin film layer immediately below the interlayer insulating film 7 is lower than the resistance of the channel region 31 that is the oxide semiconductor thin film layer immediately below the gate insulating film 4. can do.
When a film containing hydrogen is formed on the oxide semiconductor thin film layer 3, hydrogen diffuses from the film into the oxide semiconductor thin film layer 3. Hydrogen forms an electrically shallow impurity level and causes a reduction in resistance of the oxide semiconductor thin film layer. By making the hydrogen concentrations of the gate insulating film 4 and the interlayer insulating film 7 different, the amount of diffusion of hydrogen into the oxide semiconductor thin film layer 3 is also different, and the resistance is also different. That is, by making the hydrogen concentration of the interlayer insulating film 7 higher than the hydrogen concentration of the gate insulating film 4, the hydrogen concentration of the oxide semiconductor thin film layer immediately below the interlayer insulating film 7 is reduced to the oxidation immediately below the gate insulating film 4. A pair of source / drain regions 32 having a higher resistance than the hydrogen concentration of the thin film semiconductor layer and having a low resistance can be formed.
Specifically, by using silicon nitride (SiNx) for the interlayer insulating film 7 and silicon oxide (SiO 2 ) for the gate insulating film 4, the hydrogen concentration of the interlayer insulating film is made higher than the hydrogen concentration of the gate insulating film. I can. In addition, the hydrogen concentration can be controlled by the film forming conditions.

  The pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via the contact portions 8a.

  The display electrode 9 is formed to apply a voltage to the liquid crystal used in the liquid crystal display via a thin film transistor. Since this electrode requires high transmittance for visible light, it is formed of indium tin oxide (ITO), which is an oxide conductive thin film.

  The TFT according to the present invention is not limited to the first embodiment, and a second embodiment as shown in FIG. 3 is also conceivable. The second embodiment is generally called a coplanar type, and has a structure in which corresponding source / drain electrodes are connected to a pair of source / drain regions, respectively. A part of the TFT 200 of the second embodiment has the same structure as that of the TFT of the first embodiment, and therefore shows the same reference numerals. In the case of the TFT 200 of the second embodiment, it is sufficient that the resistance of the source / drain region 32 is reduced only at the upper surface.

  A method of manufacturing the thin film transistor (TFT) according to the first embodiment of the present invention will be described below with reference to FIG.

First, as shown in FIG. 2A, a semiconductor thin film mainly composed of zinc oxide as an oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and the pair of source / drain electrodes 2, preferably intrinsic zinc oxide ( ZnO) is formed by a magnetron sputtering method with a film thickness of, for example, about 50 to 100 nm and patterned. A gate insulating film 4 is formed thereon by a technique and conditions that do not reduce the resistance of the zinc oxide surface.
An example of a method for forming the gate insulating film 4 is a method of forming SiN with a thickness of 20 to 50 nm by plasma enhanced chemical vapor deposition (PCVD). Examples of conditions include conditions performed by adjusting the mixed gas of NH 3 and SiH 4 at a substrate temperature of 250 ° C. so that NH 3 has a flow rate four times that of SiH 4 .

As shown in FIG. 2B, a gate electrode 6 is loaded on the gate insulating film 4, and the gate insulating film 4 is dry-etched using a gas such as SF 6 using the gate electrode 6 as a mask.

  FIG. 2 (3) shows a cross-sectional view after the gate insulating film 4 is dry-etched. The gate insulating film 4 and the gate electrode 6 are formed in the same shape in a self-aligning manner. In addition, since the oxide semiconductor thin film layer 3 is not etched by the treatment, both end portions are not covered with the gate insulating film 4 and are exposed.

After pattern formation of the gate insulating film 4, an interlayer insulating film 7 is formed on the entire surface of the substrate 1, the pair of source / drain electrodes 2, the oxide semiconductor thin film layer 3, and the gate electrode 6 as shown in FIG.
At this time, when the interlayer insulating film 7 contains hydrogen, the resistance of the oxide semiconductor thin film layer covered with the interlayer insulating film 7 can be reduced.
Further, it is preferable to use a film in which the hydrogen concentration of the interlayer insulating film 7 is higher than the hydrogen concentration of the gate insulating film 4. Hydrogen diffuses from the interlayer insulating film 7 to the underlying oxide semiconductor thin film layer 3, but this diffusion amount is larger than the diffusion amount from the gate insulating film. Therefore, the hydrogen concentration of the oxide semiconductor thin film layer immediately below the interlayer insulating film 7 is higher than the hydrogen concentration immediately below the gate insulating film 4. Since hydrogen forms an electrically shallow impurity level, the region immediately below the interlayer insulating film 7 has a lower resistance than the region immediately below the gate insulating film 4, and becomes a pair of source / drain regions 32.
Thereby, the resistance from the source / drain electrodes to the channel can be suppressed, and the current rate can be suppressed.
In addition, the resistance of the source / drain region 32 can be further reduced by further reducing the resistance by ion implantation or the like before forming the interlayer insulating film, thereby further suppressing the current rate limiting. it can.
Further, as an example of a method for forming the interlayer insulating film 7, there is a method of forming a SiN film with a thickness of 100 to 500 nm by plasma enhanced chemical vapor deposition (PCVD). The conditions example, conditions for a mixed gas of SiH 4 and NH 3 at a substrate temperature of 250 ° C. and adjust the flow rate such that the SiH 4 / NH 3 from 4 to 20 is illustrated.
In addition, hydrogen is efficiently introduced into the oxide semiconductor thin film layer covered with the interlayer insulating film by exposing the substrate to plasma with hydrogen or a gas containing hydrogen as a constituent element before forming the interlayer insulating film by the PCVD method. Therefore, the source / drain regions with reduced resistance can be formed efficiently.
In addition, by forming an interlayer insulating film by PCVD while applying high-frequency power to the substrate side, the ion energy in the plasma can be increased, and hydrogen is introduced deeper into the oxide semiconductor thin film layer. It becomes possible to do.
After the interlayer insulating film is formed, heat treatment is preferably performed at a temperature higher than the film forming temperature of the interlayer insulating film, for example, 300 ° C. Accordingly, hydrogen in the interlayer insulating film can be diffused into the oxide semiconductor thin film, and the effects of the present invention can be more effectively achieved.

  Thereafter, as shown in FIG. 2 (5), contact holes are opened on the source / drain electrodes 2 using photolithography, and a pair of source / drain external electrodes 2a are connected to the corresponding sources via the contact portions 8a. Connect to drain electrode 2 Finally, the display electrode 9 made of indium tin oxide (ITO) or the like is formed to complete the TFT array.

A method for manufacturing a thin film transistor (TFT) according to the second embodiment of the present invention will be described below (not shown).
First, the oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and patterned. Thereafter, the gate insulating film 4 is coated on the oxide semiconductor thin film layer 3 and the gate electrode 7 is loaded thereon. The gate insulating film 4 is etched using the gate electrode 7 as a mask.
Thereafter, an interlayer insulating film 7 is formed. At this time, since the interlayer insulating film 7 contains hydrogen, the resistance of the oxide semiconductor thin film layer covered with the interlayer insulating film 7 can be reduced.
At this time, the hydrogen concentration of the interlayer insulating film is higher than the hydrogen concentration of the gate insulating film 4. Due to the difference in the amount of hydrogen diffusion, in the oxide semiconductor thin film layer 3, the region immediately below the interlayer insulating film 7 has a lower resistance than the region immediately below the gate insulating film 4, and a pair of source / drain regions 32 are formed. .
Then, contact holes are opened to connect the pair of source / drain electrodes 2 to the corresponding source / drain regions 32. Finally, the display electrode 9 is formed, and the TFT array according to the second embodiment is completed.

  As described above, the thin film transistor using the zinc oxide according to the present invention for the semiconductor thin film layer has excellent performance and can be suitably used as a driving element for a liquid crystal display device or the like.

It is sectional drawing which shows 1st embodiment of the thin-film transistor (TFT) in this invention. It is sectional drawing which shows the manufacturing method of 1st embodiment of the thin-film transistor (TFT) in this invention with time, and consists of following (1) to (5). (1) Cross-sectional view of a structure in which source / drain electrodes and oxide semiconductor thin film layers are formed on a substrate and a gate insulating film is coated (2) Cross-sectional view of a stacked gate electrode (3) Structure in which a gate insulating film is patterned (4) Cross-sectional view coated with an interlayer insulating film (5) Cross-sectional view of a structure in which contact portions, source / drain external electrodes, and display electrodes are formed It is sectional drawing which shows 2nd embodiment of the thin-film transistor (TFT) in this invention. It is sectional drawing which shows the thin-film transistor (TFT) using an amorphous silicon as a semiconductor thin film layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Source / drain electrode 3 Oxide semiconductor thin film layer 31 Channel region 32 Source / drain region 4 Gate insulating film 6 Gate electrode 7 Interlayer insulating film 100, 200 Thin film transistor





Claims (5)

  1. An oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on an insulating substrate, a gate insulating film formed on the oxide semiconductor thin film layer, and a gate stacked on the gate insulating film An electrode and an interlayer insulating film covering at least a range of the oxide semiconductor thin film layer not covered with the gate insulating film, and the gate insulating film and the gate electrode are formed in the same shape in a self-aligning manner, A thin film transistor comprising hydrogen in the interlayer insulating film, wherein a hydrogen concentration in the interlayer insulating film is higher than a hydrogen concentration in the gate insulating film .
  2. A step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on the substrate; a step of covering the oxide semiconductor thin film layer to form a gate insulating film; and on the gate insulating film In a method of manufacturing a thin film transistor including a step of loading a gate electrode, the gate insulating film is etched using the gate electrode as a mask, and an interlayer insulating film containing hydrogen is formed on a region exposed by the etching process. A method of manufacturing a thin film transistor , wherein the resistance is reduced to form source / drain regions, and the hydrogen concentration in the interlayer insulating film is higher than the hydrogen concentration in the gate insulating film .
  3. Using a plasma CVD method in the film forming of the interlayer insulating film, according to claim 2, wherein the exposing the substrate to plasma generated by a gas containing as a constituent element of hydrogen or hydrogen before forming the interlayer insulating film Thin film transistor manufacturing method.
  4. 4. The method of manufacturing a thin film transistor according to claim 2 , wherein a plasma CVD method is used for forming the interlayer insulating film, and the interlayer insulating film is formed while applying high frequency power to the substrate side.
  5. A step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on the substrate; a step of covering the oxide semiconductor thin film layer to form a gate insulating film; and on the gate insulating film In a method of manufacturing a thin film transistor including a step of loading a gate electrode, the gate insulating film is etched using the gate electrode as a mask, and an interlayer insulating film containing hydrogen is formed on a region exposed by the etching process. The resistance is reduced to form source / drain regions , plasma CVD is used to form the interlayer insulating film, and the substrate is applied to plasma with hydrogen or a gas containing hydrogen as a constituent element before forming the interlayer insulating film. A method of manufacturing a thin film transistor, characterized by being exposed .
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