JP2007220818A - Thin-film transistor and manufacturing method thereof - Google Patents

Thin-film transistor and manufacturing method thereof Download PDF

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JP2007220818A
JP2007220818A JP2006038427A JP2006038427A JP2007220818A JP 2007220818 A JP2007220818 A JP 2007220818A JP 2006038427 A JP2006038427 A JP 2006038427A JP 2006038427 A JP2006038427 A JP 2006038427A JP 2007220818 A JP2007220818 A JP 2007220818A
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gate insulating
insulating film
thin film
oxide semiconductor
semiconductor thin
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Hiroshi Furuta
Mamoru Furuta
Takahiro Hiramatsu
Takashi Hirao
Tokiyoshi Matsuda
守 古田
寛 古田
孝 平尾
孝浩 平松
時宜 松田
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Casio Comput Co Ltd
Kochi Prefecture Sangyo Shinko Center
カシオ計算機株式会社
財団法人高知県産業振興センター
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Priority to JP2006038427A priority Critical patent/JP2007220818A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor in which occurrence of current rate limiting is suppressed by reducing parasitic resistance from source-drain electrodes to a channel, and to provide a manufacturing method thereof. <P>SOLUTION: The thin-film transistor has an oxide semiconductor thin-film layer principally containing a zinc oxide and formed as a channel on a substrate; a gate insulating film for covering at least a predetermined range of the oxide semiconductor thin-film layer; and a gate electrode stacked on the gate insulating film. The oxide semiconductor thin-film layer includes a source-drain region where a range other than a portion immediately below the gate electrode has resistance less than that of a range of the portion immediately below the gate electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor (hereinafter abbreviated as TFT) having at least an oxide semiconductor thin film layer as an active layer and a manufacturing method thereof.

It has been known for a long time that oxides such as zinc oxide or magnesium zinc oxide exhibit excellent semiconductor (active layer) properties.In recent years, with the aim of application to electronic devices such as thin film transistors, light-emitting devices, transparent conductive films, etc. Research and development of semiconductor thin film layers using compounds has been activated.
TFTs using zinc oxide or magnesium zinc oxide as semiconductor thin film layers are electrons compared to amorphous silicon TFTs using amorphous silicon (a-Si: H), which is mainly used in conventional liquid crystal displays, as semiconductor thin film layers. Active development is underway, with advantages such as high mobility, excellent TFT characteristics, and the expectation of high mobility by obtaining a polycrystalline thin film even at low temperatures near room temperature.

  As TFTs (zinc oxide TFTs) using zinc oxide as an oxide semiconductor thin film layer, bottom-gate and top-gate structures have been reported.

  An example of a bottom-gate structure is a structure in which a gate electrode and a gate insulating film are formed in order from the substrate, and an oxide semiconductor thin film layer mainly composed of zinc oxide is formed covering the upper surface. (For example, refer to Patent Document 1 below). This structure is similar in manufacturing process to the bottom gate type amorphous silicon TFT currently commercialized as a driving element of a liquid crystal display. Therefore, the structure can be created relatively easily with the production equipment of the amorphous silicon TFT, and is often used as a zinc oxide TFT.

  However, since the bottom gate type thin film transistor has a structure in which an oxide semiconductor thin film layer is stacked on a gate insulating film, an area of initial film formation with insufficient crystallinity must be used as an active layer, There is a problem that sufficient mobility cannot be obtained. On the other hand, a top-gate thin film transistor has a structure in which a gate insulating film is provided over an oxide semiconductor thin film layer, so that a region with good crystallinity above the oxide semiconductor thin film layer can be used as an active layer. This is more effective than a bottom gate type thin film transistor.

As an example of the top gate structure, as shown in FIG. 7, a pair of source / drain electrodes 12, an oxide semiconductor thin film layer 13, a gate insulating film 14, and a gate electrode 15 are stacked in this order from the substrate 11. The structure can be exemplified.
However, this structure has a problem that the oxide semiconductor thin film layer 13 extending from the source / drain electrode 12 to the channel becomes a parasitic resistance, and current limiting occurs.

Japanese Patent Laid-Open No. 2004-349583

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a thin film transistor in which parasitic resistance from a source / drain electrode to a channel is reduced and current rate is suppressed, and a method for manufacturing the same.

  The invention according to claim 1 includes an oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on a substrate, a gate insulating film covering at least a certain range of the oxide semiconductor thin film layer, and the gate A thin film transistor having a gate electrode stacked on an insulating film, wherein a range of the oxide semiconductor thin film layer other than directly below the gate electrode is lower than a range directly below the gate electrode. The present invention relates to a thin film transistor including a source / drain region.

The invention according to claim 2 is characterized in that the source / drain region is formed of a region whose resistance is reduced by doping ions serving as donors with respect to zinc oxide by an ion implantation method. The present invention relates to a thin film transistor.
A third aspect of the present invention relates to the thin film transistor according to the second aspect, wherein the ions are ions of group III.

  The invention according to claim 4 relates to the thin film transistor according to any one of claims 1 to 3, wherein the gate insulating film and the gate electrode have the same shape in a self-aligning manner.

According to a fifth aspect of the present invention, the gate insulating film is formed on the first gate insulating film, the first gate insulating film covering at least the entire upper surface of the oxide semiconductor thin film layer, and the gate electrode 4. The thin film transistor according to claim 1, comprising a second gate insulating film formed in the same shape in a self-aligned manner.
The invention according to claim 6 relates to the thin film transistor according to claim 5, wherein the first gate insulating film covers only the entire upper surface of the oxide semiconductor thin film layer.

  The invention according to claim 7 is a step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on a substrate, and a step of covering the oxide semiconductor thin film layer to form a gate insulating film. The present invention relates to a method of manufacturing a thin film transistor having a process of stacking a gate electrode on the gate insulating film, wherein the resistance is reduced using the gate electrode as a mask to form a source / drain region.

The invention according to claim 8 is characterized in that the source / drain regions are formed by reducing the resistance by doping ions serving as donors with respect to zinc oxide by an ion implantation method. Relates to the manufacturing method.
The invention according to claim 9 relates to a method of manufacturing a thin film transistor according to claim 8, characterized in that a group III ion is used as the ion.

  The invention according to claim 10 relates to the thin film transistor according to any one of claims 7 to 9, wherein the gate insulating film is etched using the gate electrode as a mask.

According to an eleventh aspect of the present invention, the gate insulating film includes a first gate insulating film and a second gate insulating film, and covers the entire upper surface of the oxide semiconductor thin film layer to form the first gate insulating film. A second gate insulating film is formed on the first gate insulating film, the gate electrode is stacked on the second gate insulating film, and the second gate insulating film is formed using the gate electrode as a mask. 10. The method of manufacturing a thin film transistor according to claim 7, wherein an etching process is performed.
The invention according to claim 12 relates to the method of manufacturing a thin film transistor according to claim 11, wherein the oxide semiconductor thin film layer and the first gate insulating film are etched together.

  According to the first aspect of the present invention, in the oxide semiconductor thin film layer, the region other than the region directly below the gate electrode includes the source / drain region having a lower resistance than the region directly below the gate electrode. -Parasitic resistance from the drain electrode to the channel can be suppressed, and current rate limiting can be suppressed. In addition, since the source / drain regions are located in a range other than directly below the gate electrode, the parasitic capacitance between the source / drain regions and the gate electrode is reduced, and the operation speed can be improved.

According to the second aspect of the present invention, the source / drain region is made of a region whose resistance is reduced by doping ions serving as donors with respect to zinc oxide by an ion implantation method. After film formation, ions can be doped afterwards. Therefore, the resistance of the source / drain regions can be reduced by self-alignment and selectively.
According to the invention of claim 3, by doping ions made of group III elements by ion implantation, these ions become donors to zinc oxide, and the resistance can be effectively reduced.

  According to the invention of claim 4, since the gate insulating film and the gate electrode are formed in the same shape in a self-aligning manner, the source / drain region is not covered with the gate insulating film, and the resistance is reduced. Can be performed without a gate insulating film. Therefore, it is possible to reduce a pressurizing voltage or the like when doping ions, and to reduce damage caused by doping ions into zinc oxide.

According to the invention of claim 5, since the second gate insulating film and the gate electrode are formed in the same shape in a self-aligning manner, the first gate is formed as a gate insulating film on the region to be the source / drain region. Only the insulating film exists and the first gate insulating film is thinned, whereby the applied voltage or the like when doping ions can be reduced.
Further, the gate insulating film is composed of the first gate insulating film and the second gate insulating film, and the first gate insulating film covers the entire upper surface of the oxide semiconductor thin film layer, so that the first gate insulating film becomes the source / drain region. Also plays a role to protect. Therefore, the resistance of the source / drain regions can be further reduced.
According to the invention of claim 6, since the first gate insulating film covers only the entire upper surface of the oxide semiconductor thin film layer, the interface characteristics between the oxide semiconductor thin film layer and the first gate insulating film are excellent. Maintained.

  According to the seventh aspect of the present invention, the parasitic resistance from the source / drain electrode to the channel can be suppressed by reducing the resistance by using the gate electrode as a mask to form the source / drain region, and the current rate can be suppressed. Can do. In addition, since the source / drain regions are located in a range other than directly below the gate electrode, the parasitic capacitance between the source / drain regions and the gate electrode is reduced, and the operation speed can be improved.

In the invention according to claim 8, the source / drain regions are formed by reducing the resistance by doping ions serving as donors with respect to zinc oxide by an ion implantation method. After that, ions can be doped, and the source / drain regions can be self-aligned and selectively reduced in resistance.
In the invention according to claim 9, by using ions made of group III as ions to be doped in the source / drain regions, these ions become donors to zinc oxide and can effectively reduce the resistance. .

  In the invention according to claim 10, by etching the gate insulating film using the gate electrode as a mask, the source / drain regions are not covered with the gate insulating film, and the resistance is reduced without using the gate insulating film. be able to. Therefore, it is possible to reduce a pressurizing voltage or the like when doping ions, and to reduce damage caused by doping ions into zinc oxide.

The invention according to claim 11 comprises the step of etching the second gate insulating film using the gate electrode as a mask, so that only the first gate insulating film is provided as a gate insulating film on the region to be the source / drain region. It will only exist. Therefore, by reducing the thickness of the first gate insulating film, it is possible to reduce the applied voltage when doping ions.
Furthermore, since the first gate insulating film covers the entire upper surface of the oxide semiconductor thin film layer, the source / drain regions can be protected in a manufacturing process such as etching the second gate insulating film. Therefore, the resistance of the source / drain regions can be further reduced.
According to a twelfth aspect of the present invention, the first gate insulating film protects the oxide semiconductor thin film layer from various solvents such as a resist stripping solution by etching the oxide semiconductor thin film layer and the first gate insulating film together. Therefore, the interface characteristics between the oxide semiconductor thin film layer and the gate insulating film are maintained well.

Hereinafter, embodiments of the thin film transistor of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a first embodiment of a thin film transistor according to the present invention.

  A thin film transistor 100 according to the first embodiment of the present invention includes a substrate 1, a pair of source / drain electrodes 2, an oxide semiconductor thin film layer 3, a gate insulating film 4, a gate electrode 6, an interlayer insulating film 7, a contact portion 8a, It has a pair of source / drain external electrodes 2a and a display electrode 9, and is formed by laminating these components as shown in FIG. 1, and is usually called a stagger type.

As shown in FIG. 1, the thin film transistor 100 is formed on a substrate 1 made of glass (non-alkali glass containing SiO 2 and Al 2 O 3 as main components).
The material of the substrate 1 is not limited to glass, and any material can be used as long as it is an insulator such as a plastic or metal foil coated with an insulator.

A pair of source / drain electrodes 2 are stacked on the substrate 1. The pair of source / drain electrodes 2 are disposed on the upper surface of the substrate 1 with a gap.
The source / drain electrode 2 is formed of, for example, a conductive oxide such as indium tin oxide (ITO) or n + ZnO, a metal, or a metal at least partially covered with the conductive oxide.

The oxide semiconductor thin film layer 3 is disposed so as to form a channel between the pair of source / drain electrodes 2, and is formed of an oxide semiconductor containing zinc oxide as a main component. Here, the oxide semiconductor containing zinc oxide as a main component is doped with intrinsic zinc oxide, p-type dopants such as Li, Na, N, and C, and n-type dopants such as B, Al, Ga, and In. And zinc oxide doped with Mg, Be and the like.
The oxide semiconductor thin film layer includes a channel region 31 and a pair of source / drain regions 32. The channel region 31 is a range used as a channel of the oxide semiconductor thin film layer 3.
The pair of source / drain regions 32 is formed in a self-aligned manner in a region not covered with the gate electrode of the oxide semiconductor thin film layer 3. At this time, it is preferable that ions serving as donors with respect to zinc oxide are formed afterwards by ion implantation. This is because ions can be selectively doped in a self-aligned manner by using the ion implantation method. Since the source / drain region 32 is doped with ions, the resistance becomes lower than that of the channel region 31 not doped with ions afterwards.
Examples of the ion include a group III element such as indium ion, gallium ion, and aluminum ion.
By providing the source / drain regions 32, the parasitic resistance from the source / drain electrodes to the channel can be suppressed, and the current rate can be suppressed.
Although the thickness of this oxide semiconductor thin film layer 3 is not specifically limited, For example, it forms in about 25-200 nm, Preferably, it forms in about 50-100 nm. In FIG. 1, the source / drain region 32 is illustrated such that the thickness of the portion formed on each source / drain electrode 2 is thinner than the portion formed between the pair of source / drain electrodes 2. However, this is merely for the convenience of illustration, and in fact, the thicknesses of both are almost the same.

The gate insulating film 4 is formed so as to cover only the upper surface of the channel region 31 of the oxide semiconductor thin film layer 3.
The gate insulating film 4 is a silicon oxide (SiOx) film, silicon oxynitride (SiON) film, silicon nitride (SiNx) film, or silicon nitride (SiNx) doped with oxygen using oxygen or a compound containing oxygen as a constituent element. It is formed by a film. The gate insulating film 4 has a dielectric constant larger than that of a silicon oxide compound (SiOx) or silicon oxynitride (SiON), and a compound containing oxygen or oxygen as a constituent element in silicon nitride (SiNx), for example, nitrogen oxide (N 2 A film doped with oxygen using O) is preferably used. Accordingly, the thin film transistor has a high dielectric constant and is excellent from the viewpoint of protecting the oxide semiconductor thin film layer.

The gate electrode 6 is formed on the gate insulating film 4. The gate electrode 6 serves to control the electron density in the oxide semiconductor thin film layer 3 by a gate voltage applied to the thin film transistor.
The gate electrode 6 is made of a metal film exemplified by Cr and Ti.
Further, both ends of the gate electrode 6 are present at positions aligned with the inner ends of the pair of source / drain regions 32 in the film thickness direction. Thereby, parasitic capacitance is reduced between the source / drain regions and the gate electrode, and the operation speed can be improved.
Moreover, it is preferable that both ends of the gate electrode 6 are located at positions inside the inner ends of the source / drain electrodes. As a result, the parasitic capacitance between the gate electrode 6 and the source / drain electrode 2 is reduced, and a decrease in the operation speed is suppressed.

  The interlayer insulating film 7 is laminated so as to cover the entire surface of the pair of source / drain electrodes 2, the oxide semiconductor thin film layer 3, and the gate electrode 6.

  The pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via the contact portions 8a.

  The display electrode 9 is formed to apply a voltage to the liquid crystal used in the liquid crystal display via a thin film transistor. Since this electrode requires high transmittance for visible light, it is formed of indium tin oxide (ITO), which is an oxide conductive thin film.

  A second embodiment as shown in FIG. 3 is also conceivable. The second embodiment is usually called a coplanar type, and has a structure in which corresponding source / drain electrodes 2 are connected to a pair of source / drain regions 32, respectively. A part of the TFT 200 of the second embodiment has a structure similar to that of the TFT of the first embodiment, and therefore has the same reference number. In the case of the TFT 200 of the second embodiment, it is sufficient that at least the upper surface of the pair of source / drain regions 32 has a low resistance.

  A third embodiment as shown in FIG. 4 is also conceivable. A part of the TFT 300 according to the third embodiment has the same structure as the TFT 100 and the TFT 200, and is given the same reference number. However, the gate insulating film 4 includes a first gate insulating film and a second gate insulating film. For convenience, the first gate insulating film 41 and the second gate insulating film 5 are used.

  The first gate insulating film 41 is formed so as to cover the entire upper surface and side surfaces of the oxide semiconductor thin film layer 3. Since the first gate insulating film 41 covers the pair of source / drain regions 32, the pair of source / drain regions 32 is protected from an etching process in a manufacturing process such as etching the second gate insulating film. be able to. Therefore, the resistance of the source / drain regions can be further reduced.

  The second gate insulating film 5 is formed in the same shape as the gate electrode 6 in a self-aligning manner so as to cover a part of the upper part of the first gate insulating film 41.

  The first gate insulating film 41 and the second gate insulating film 5 are formed of different compounds. Thereby, only the second gate insulating film can be etched without etching the first gate insulating film 41. Specifically, a configuration in which the first gate insulating film 41 is a silicon oxide (SiOx) film and the second gate insulating film 5 is a silicon nitride (SiNx) film is exemplified.

A fourth embodiment as shown in FIG. 6 is also conceivable. The TFT 400 according to the fourth embodiment has a structure in which the first gate insulating film 41 of the TFT 300 covers only the upper surface of the oxide semiconductor thin film layer 3. Therefore, the same reference numbers as those of the TFT 300 are given.
The TFT 400 has a structure in which the first gate insulating film covers only the entire upper surface of the oxide semiconductor thin film layer. In order to adopt such a structure, the oxide semiconductor thin film layer 3 and the first gate insulating film 41 are collectively etched, and the first gate insulating film 41 forms the oxide semiconductor thin film layer 3 as a resist stripping solution. Plays a role in protecting against various chemicals. Therefore, surface roughness of the oxide semiconductor thin film layer can be prevented. Preferably, the oxide semiconductor thin film layer 3 and the first gate insulating film 41 are continuously formed in vacuum, and then taken out into the atmosphere and etched. Thereby, a good interface between the oxide semiconductor thin film layer 3 formed in vacuum and the first gate insulating film 41 is maintained, and an improvement in TFT characteristics can be expected.

  The present invention naturally includes a structure (coplanar type) in which the gate insulating film is formed of two layers and the source / drain electrodes are connected on the source / drain regions. Further, a structure in which the gate insulating film is composed of three or more layers is naturally included.

  A method of manufacturing the thin film transistor (TFT) according to the first embodiment of the present invention will be described below with reference to FIG.

First, as shown in FIG. 2A, a semiconductor thin film mainly composed of zinc oxide as an oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and the pair of source / drain electrodes 2, preferably intrinsic zinc oxide ( ZnO) is formed by magnetron sputtering with a film thickness of, for example, about 50 to 100 nm and patterned. A gate insulating film 4 is formed thereon by a technique and conditions that do not reduce the resistance of the zinc oxide surface.
An example of a method for forming the gate insulating film 4 is a method of forming SiNx with a thickness of 50 to 500 nm by plasma enhanced chemical vapor deposition (PCVD). Examples of conditions include conditions performed by adjusting the mixed gas of NH 3 and SiH 4 at a substrate temperature of 250 ° C. so that NH 3 has a flow rate four times that of SiH 4 .

As shown in FIG. 2B, a gate electrode 6 is loaded on the gate insulating film 4, and the gate insulating film 4 is dry-etched using a gas such as SF 6 using the gate electrode 6 as a mask.

  FIG. 2 (3) shows a cross-sectional view after the gate insulating film 4 is dry-etched. The gate insulating film 4 and the gate electrode 6 are formed in the same shape in a self-aligning manner. In addition, since the oxide semiconductor thin film layer 3 is not etched by the treatment, both end portions are not covered with the gate insulating film 4 and are exposed.

After the pattern formation of the gate insulating film 4, as shown in FIG. 2 (4), zinc oxide is formed on the pair of source / drain regions 32 exposed using the gate electrode 6 as a mask in the entire film thickness direction of the oxide semiconductor thin film layer 3. On the other hand, it is preferable to reduce the resistance by doping ions serving as donors by an ion implantation method. This is because by using the ion implantation method, ions can be doped after the oxide semiconductor thin film layer is formed, and self-alignment can be selectively performed.
Examples of ions serving as donors include Group III elements such as indium ions, gallium ions, and aluminum ions.
Further, since these ions are doped without going through the gate insulating film, the applied voltage during doping can be reduced, and damage caused by ion implantation into zinc oxide can be reduced.

  As shown in FIG. 2 (5), an interlayer insulating film 7 is formed on the entire surface of the substrate 1, the pair of source / drain electrodes 2, the oxide semiconductor thin film layer 3, and the gate electrode 6.

  Thereafter, as shown in FIG. 2 (6), by using a photolithography method, contact holes are opened on the pair of source / drain electrodes 2, and the pair of source / drain external electrodes 2a are respectively connected via the contact portions 8a. To the corresponding source / drain electrodes 2. Finally, the display electrode 9 made of indium tin oxide (ITO) or the like is formed to complete the TFT array.

A method for manufacturing a thin film transistor (TFT) according to the second embodiment of the present invention will be described below (not shown).
First, the oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and patterned. Thereafter, the gate insulating film 4 is coated on the oxide semiconductor thin film layer 3 and the gate electrode 7 is loaded thereon. Using the gate electrode 7 as a mask, the gate insulating film 4 is etched, and the resistance of the exposed portion of the oxide semiconductor thin film layer 3 is reduced to form the source / drain regions 32.
As a method for reducing the resistance, it is preferable to perform doping by ion implantation with ions serving as donors to zinc oxide as in the first embodiment. In the second embodiment, it is sufficient that at least the upper surface of the source / drain region has a low resistance. Examples of the ion include a group III element ion such as an aluminum ion, an indium ion, and a gallium ion.
Thereafter, an interlayer insulating film 7 is formed, contact holes are opened, and the pair of source / drain electrodes 2 are connected to the corresponding source / drain regions 32. Finally, the display electrode 9 is formed, and the TFT array according to the second embodiment is completed.

Next, a method for manufacturing a TFT according to the third embodiment will be described.
First, as shown in FIG. 5A, the entire surface of the substrate 1 and the pair of source / drain electrodes 2 is covered with an oxide semiconductor thin film layer 3 and patterned. Then, as shown in FIG. 5 (2), the first gate insulating film 41 is formed by a technique and conditions that do not reduce the resistance of zinc oxide.

As shown in FIG. 5 (3), the second gate insulating film 5 is formed so as to cover the first gate insulating film 41. The gate electrode 6 is loaded on the second gate insulating film 5, and the second gate insulating film 5 is dry-etched using a gas such as SF 6 using the gate electrode 6 as a mask. By making the first gate insulating film 41 and the second gate insulating film 5 different compounds, only the second gate insulating film 5 can be etched without etching the first gate insulating film 41. Therefore, the first gate insulating film 41 exists on the source / drain region 32, and the source / drain region can be protected in a manufacturing process such as etching the second gate insulating film 5, so that the source / drain region is protected. The resistance of the region can be further reduced.
Specifically, the SiO 2 film formed by the plasma CVD method using SiH 4 and N 2 O gas as the first gate insulating film 41, and the SiN formed by the plasma CVD method as the second gate insulating film. By using a film, etching selectivity can be secured and the structure can be formed. In this case, the thickness of each layer is not particularly limited, but it is possible to prevent the acceleration voltage such as ion implantation from increasing by setting the first gate insulating film to a level equivalent to the zinc oxide film thickness of 50 to 100 nm. Become.

  FIG. 5 (4) shows a cross-sectional view after the second gate insulating film 5 is dry-etched. The second gate insulating film 5 and the gate electrode 6 are formed in the same shape in a self-aligning manner.

As shown in FIG. 5 (5), ions serving as donors for zinc oxide are ion-implanted in the source / drain regions 32 using the gate electrode 6 as a mask in the entire thickness direction of the oxide semiconductor thin film layer 3. Preferably, the resistance is lowered by doping. In this case, examples of the ions include ions composed of group III elements, such as indium ions, gallium ions, and aluminum ions.
At this time, by setting the first gate insulating film to 50 to 100 nm, which is equivalent to the thickness of the oxide semiconductor thin film, the applied voltage used in the ion implantation method can be reduced.
Further, since the first gate insulating film 41 covers the pair of source / drain regions 32, damage to the source / drain regions when the second gate insulating film 5 is etched can be prevented. Therefore, the resistance of the source / drain regions can be further reduced.

  Thereafter, an interlayer insulating film 7 is formed on the entire surface of the substrate 1, the pair of source / drain electrodes 2, the oxide semiconductor thin film layer 3, and the gate electrode 6. Then, contact holes are opened on the source / drain electrodes 2 using a photolithography method, and the pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via the contact portions 8a. Finally, a display electrode 9 made of indium tin oxide (ITO) or the like is formed to complete the TFT array (see FIG. 4).

Finally, a manufacturing method of the TFT 400 according to the fourth embodiment of the present invention will be described (not shown).
The manufacturing method of the TFT 400 is performed together with the first gate insulating film 41 when the oxide semiconductor thin film layer 3 is etched in the manufacturing method of the TFT 300. Specifically, the oxide semiconductor thin film layer 3 is formed on the entire surface of the substrate 1 and the pair of source / drain electrodes 2, and the first gate insulating film 41 is formed without patterning. At this time, it is desirable to form the oxide semiconductor thin film layer in a vacuum using a sputtering method, and continuously form a gate insulating film using a plasma CVD method or a sputtering method without opening to the atmosphere. Thereby, a favorable interface is formed and maintained between the oxide semiconductor thin film layer 3 and the first gate insulating film 41. Thereafter, the substrate is taken out into the atmosphere, a photoresist is coated on the first gate insulating film 41, a patterned photoresist is formed, and the first gate insulating film 41 and the oxide are formed using the photoresist as a mask. The semiconductor thin film layer 3 is dry etched at once.

As a result, a TFT active layer region having the first gate insulating film 41 having the same shape as the oxide semiconductor thin film layer 3 is formed. In addition to forming an interface with the oxide semiconductor thin film layer 3, the first gate insulating film 41 also plays a role of protecting the oxide semiconductor thin film layer when patterning the active region. That is, if the resist stripping solution used for stripping the photoresist 4a after patterning the active layer contacts the surface of the oxide semiconductor thin film layer 3, the surface of the thin film and the crystal grain boundary are roughened by etching, but the first gate insulation The presence of the film 41 on the surface of the oxide semiconductor thin film layer 3 serves as a protective film against various chemicals such as a resist stripping solution in a photolithography process, and the surface roughness of the oxide semiconductor thin film layer 3 can be prevented.
In addition, the first gate insulating film 41 exists on the pair of source / drain regions 32, and the source / drain regions can be protected in a manufacturing process such as etching the second gate insulating film 5. Therefore, the resistance of the source / drain regions can be further reduced.
As mentioned above, although embodiment of this invention was described, this invention is not limited at all by above-described embodiment, The thin-film transistor which has an oxide semiconductor thin film layer which has zinc oxide as a main component besides above-described embodiment Of course, those having source / drain regions with reduced resistance are included.

  As described above, the thin film transistor using the zinc oxide according to the present invention for the semiconductor thin film layer has excellent performance and can be suitably used as a driving element for a liquid crystal display device or the like.

It is sectional drawing which shows 1st embodiment of the thin-film transistor (TFT) in this invention. It is sectional drawing which shows the manufacturing method of 1st embodiment of the thin-film transistor (TFT) in this invention over time, and consists of following (1) to (6). (1) Cross-sectional view of a structure in which source / drain electrodes and oxide semiconductor thin film layers are formed on a substrate and a gate insulating film is coated (2) Cross-sectional view of a stacked gate electrode (3) Structure in which a gate insulating film is patterned (4) Cross-sectional view after resistance reduction (5) Cross-sectional view coated with interlayer insulating film (6) Cross-sectional view of structure in which contact portion, source / drain external electrode and display electrode are formed It is sectional drawing which shows 2nd embodiment of the thin-film transistor (TFT) in this invention. It is sectional drawing which shows 3rd embodiment of the thin-film transistor (TFT) in this invention. It is sectional drawing which shows temporally the manufacturing method of 3rd embodiment of the thin-film transistor (TFT) in this invention, and consists of following (1)-(5). (1) Cross-sectional view of a structure in which a source / drain electrode and an oxide semiconductor thin film layer are formed on a substrate (2) A cross-sectional view in which a first gate insulating film is formed (3) A second gate insulating film and a gate electrode are laminated Sectional view (4) Sectional view after patterning the second gate insulating film (5) Sectional view after lowering the resistance It is sectional drawing which shows 4th embodiment of the thin-film transistor (TFT) in this invention. It is sectional drawing which shows the thin-film transistor (TFT) using an amorphous silicon as a semiconductor thin film layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Source / drain electrode 3 Oxide semiconductor thin film layer 31 Channel region 32 Source / drain region 4 Gate insulating film 41 First gate insulating film 5 Second gate insulating film 6 Gate electrode 100, 200, 300, 400 Thin film transistor

Claims (12)

  1. An oxide semiconductor thin film layer mainly composed of zinc oxide formed as a channel on the substrate, a gate insulating film covering at least a certain range of the oxide semiconductor thin film layer, and the gate insulating film stacked on the gate insulating film A thin film transistor having a gate electrode, wherein the oxide semiconductor thin film layer includes a source / drain region in which a range other than immediately below the gate electrode has a lower resistance than a range immediately below the gate electrode A thin film transistor characterized by the above.
  2. 2. The thin film transistor according to claim 1, wherein the source / drain region comprises a region whose resistance is reduced by doping ions serving as donors with respect to zinc oxide by an ion implantation method.
  3. 3. The thin film transistor according to claim 2, wherein the ion is a group III ion.
  4. 4. The thin film transistor according to claim 1, wherein the gate insulating film and the gate electrode have the same shape in a self-aligning manner.
  5. The gate insulating film is formed on the first gate insulating film so as to cover at least the entire upper surface of the oxide semiconductor thin film layer, and has the same shape as the gate electrode in a self-aligning manner. 4. The thin film transistor according to claim 1, comprising a second gate insulating film to be formed.
  6. 6. The thin film transistor according to claim 5, wherein the first gate insulating film covers only the entire upper surface of the oxide semiconductor thin film layer.
  7. A step of forming an oxide semiconductor thin film layer mainly composed of zinc oxide serving as a channel on the substrate; a step of covering the oxide semiconductor thin film layer to form a gate insulating film; and on the gate insulating film A method of manufacturing a thin film transistor having a process of stacking a gate electrode, wherein the resistance is reduced to a source / drain region using the gate electrode as a mask.
  8. 8. The method of manufacturing a thin film transistor according to claim 7, wherein the source / drain regions are formed with low resistance by doping ions serving as donors with respect to zinc oxide by an ion implantation method.
  9. 9. The method for producing a thin film transistor according to claim 8, wherein an ion comprising a group III is used as the ion.
  10. 10. The thin film transistor according to claim 7, wherein the gate insulating film is etched using the gate electrode as a mask.
  11. The gate insulating film is composed of a first gate insulating film and a second gate insulating film, and covers the entire upper surface of the oxide semiconductor thin film layer to form the first gate insulating film. A second gate insulating film is formed thereon, the gate electrode is stacked on the second gate insulating film, and the second gate insulating film is etched using the gate electrode as a mask. A method for producing a thin film transistor according to claim 7.
  12. 12. The method of manufacturing a thin film transistor according to claim 11, wherein the oxide semiconductor thin film layer and the first gate insulating film are etched together.
JP2006038427A 2006-02-15 2006-02-15 Thin-film transistor and manufacturing method thereof Pending JP2007220818A (en)

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