CN109920845A - Array substrate and its manufacturing method, display panel, display device - Google Patents
Array substrate and its manufacturing method, display panel, display device Download PDFInfo
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- CN109920845A CN109920845A CN201910212844.5A CN201910212844A CN109920845A CN 109920845 A CN109920845 A CN 109920845A CN 201910212844 A CN201910212844 A CN 201910212844A CN 109920845 A CN109920845 A CN 109920845A
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Abstract
This application discloses a kind of array substrate and its manufacturing method, display panel, display devices, belong to field of display technology.Array substrate (0) includes: substrate (01) and metal structure (02), and active layer of metal oxide (03), the first insulating layer (04) and the source-drain electrode layer (05) successively arranged along the direction far from substrate (01), metal structure (02) is located between substrate (01) and the first insulating layer (04), and is electrically connected with active layer of metal oxide (03)；Array substrate (0) has through the first insulating layer (04) and is connected to first via hole (11) of metal structure (02)；Source-drain electrode layer (05) is electrically connected by the first via hole (11) with metal structure (02).The problem of being easier to be etched present application addresses the higher active layer of metal oxide of activity and being damaged, can be avoided active layer of metal oxide is etched and damages, and the application is used for array substrate.
Description
Technical field
This application involves field of display technology, in particular to a kind of array substrate and its manufacturing method, display panel, display
Device.
Background technique
Organic LED display panel is widely answered due to having many advantages, such as that contrast is high, thickness is thin, visual angle is wide
In the electronic products such as TV, mobile phone.Array substrate in organic LED display panel generally includes: substrate, with
And pixel circuit layer and Organic Light Emitting Diode layer on substrate.
In the related technology, pixel circuit layer includes metal oxide thin-film transistor.When manufacturing array substrate, elder generation is needed
Active layer of metal oxide and the first insulating layer are sequentially formed on substrate, which is that metal oxide is thin
The active layer of film transistor.Then, form through the first insulating layer and be connected to the first via hole of active layer of metal oxide.Most
Afterwards, the first source-drain electrode of metal oxide thin-film transistor is formed, and the first source-drain electrode is made to be electrically connected metal by the first via hole
Oxide active layer.
Since the material of active layer of metal oxide is metal oxide, and metal oxide was easy to by the quarter of insulating layer
Object etching is lost, therefore, when etching the first via hole, the higher active layer of metal oxide of activity is easier to be etched and damaged
It is bad.
Summary of the invention
This application provides a kind of array substrate and its manufacturing method, display panel, display device, can solve activity compared with
High active layer of metal oxide is easier to the problem of being etched and being damaged, and the technical solution is as follows:
On the one hand, a kind of array substrate is provided, the array substrate includes: substrate and metal structure, and along separate
Active layer of metal oxide, the first insulating layer and the source-drain electrode layer that the direction of the substrate is successively arranged,
The metal structure between the substrate and first insulating layer, and with the active layer of metal oxide
Electrical connection；
The array substrate has the first via hole through first insulating layer and the connection metal structure；
The source-drain electrode layer is electrically connected by first via hole with the metal structure.
Optionally, the array substrate includes: two groups of metal structures being spaced apart from each other,
The first via hole in the array substrate is connected to one by one with metal structure；
The source-drain electrode layer includes: the first source electrode and the first drain electrode, and first source electrode and one group of metal structure pass through institute
The first via hole electrical connection of one group of metal structure connection is stated, first drain electrode passes through described another group with another group of metal structure
The first via hole electrical connection of metal structure connection.
Optionally, two groups of metal structures are respectively positioned on the active layer of metal oxide close to or far from the substrate
Side.
Optionally, the array substrate further include: the low temperature polycrystalline silicon successively arranged along the direction far from the substrate has
Active layer, second insulating layer, first grid and third insulating layer, the source-drain electrode layer further include: the second source electrode and the second drain electrode,
The metal structure and the active layer of metal oxide are respectively positioned on the third insulating layer and first insulation
Between layer, the orthographic projection region of the low-temperature polysilicon silicon active layer and the active layer of metal oxide over the substrate exists
Interval；
The array substrate has two group of second via hole, and second via hole runs through first insulating layer, described second
Insulating layer and the third insulating layer, and it is connected to the low-temperature polysilicon silicon active layer；
Second source electrode is electrically connected by the second via hole described in one group with the low-temperature polysilicon silicon active layer；Described second
Drain electrode is electrically connected by the second via hole described in another group with the low-temperature polysilicon silicon active layer.
Optionally, the array substrate further include: the electricity between first insulating layer and the third insulating layer
Hold structure.
Optionally, the capacitance structure include: along far from the substrate direction successively arrange first electrode, collets
And second electrode, the first electrode and the metal structure are same layer structure.
Optionally, the array substrate further include: be located at the active layer of metal oxide and first insulating layer it
Between, and the 4th insulating layer and second grid successively arranged along the direction far from the substrate；
The second electrode and the second grid are same layer structure, and/or, the collets and the 4th insulating layer
For same layer structure.
On the other hand, a kind of manufacturing method of array substrate is provided, which comprises
Be formed on the substrate metal structure, and the active layer of metal oxide that is sequentially overlapped along the direction far from substrate and
First insulating layer, wherein the material of the active layer of metal oxide includes metal oxide, and the metal structure is located at described
Between substrate and first insulating layer, and it is electrically connected with the active layer of metal oxide；
Patterned process is carried out to the structure formed on the substrate, to be formed through first insulating layer and connection institute
State the first via hole of metal structure；
Source-drain electrode layer is formed on the first insulating layer, wherein the source-drain electrode layer passes through first via hole and institute
State metal structure electrical connection.
Another aspect, provides a kind of display panel, and the display panel includes above-mentioned array substrate.
In another aspect, providing a kind of display device, the display device includes above-mentioned display panel.
Technical solution bring beneficial effect provided by the present application includes at least:
Since active layer of metal oxide is electrically connected by metal structure with source-drain electrode layer in array substrate, and in connection gold
Belong to structure and be connected to the metal structure with the first via hole etched when source-drain electrode layer, and is not connected to active layer of metal oxide.Cause
This, during etching the first via hole, active layer of metal oxide will not be etched.Also, since the activity of metal is lower than gold
Belong to the activity of oxide, therefore, during etching the first via hole, metal structure is also not easy to be etched.So in array substrate
Source-drain electrode layer can be effectively electrically connected by metal structure with active layer of metal oxide, and can be avoided metal oxide and have
Active layer is etched and damages.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the structural schematic diagram of array substrate in provided in an embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram for array substrate that the relevant technologies provide；
Fig. 4 is a kind of manufacturing method flow chart of array substrate provided in an embodiment of the present invention；
Fig. 5 is the manufacturing method flow chart of another array substrate provided in an embodiment of the present invention；
Fig. 6 is a kind of manufacturing process schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 7 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 8 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 9 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Figure 10 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Figure 11 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Figure 12 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Figure 13 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Figure 14 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention；
Figure 15 is the manufacturing process schematic diagram of another array substrate provided in an embodiment of the present invention.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with attached drawing to the application embodiment party
Formula is described in further detail.
Since array substrate in the related technology is during manufacture, the active layer of metal oxide thin-film transistor compared with
It is easy to be damaged by overetch, therefore, the embodiment of the invention provides a kind of new array substrates, are manufacturing the array substrate
When, the active layer of metal oxide thin-film transistor will not be etched and damage.
Fig. 1 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention, as shown in Figure 1, array substrate 0 is wrapped
It includes: substrate 01 and metal structure 02, and the active layer of metal oxide 03, first successively arranged along the direction far from substrate 01
Insulating layer 04 and source-drain electrode layer 05,
Metal structure 02 is located between substrate 01 and the first insulating layer 04, and is electrically connected with active layer of metal oxide 03；
Array substrate 0 has through the first insulating layer 04 and is connected to the first via hole 11 of metal structure 02；Source-drain electrode layer 05
It is electrically connected by the first via hole 11 with metal structure 02.
In conclusion due in array substrate provided in an embodiment of the present invention, active layer of metal oxide and source-drain electrode layer
It is electrically connected by metal structure, and is connected to the metal structure with the first via hole etched when source-drain electrode layer in connection metal structure,
And it is not connected to active layer of metal oxide.Therefore, during etching the first via hole, active layer of metal oxide will not be carved
Erosion.Also, since the activity of metal is lower than the activity of metal oxide, during etching the first via hole, metal structure
Also it is not easy to be etched.So source-drain electrode layer can be effectively electric with active layer of metal oxide by metal structure in array substrate
Connection, and can be avoided active layer of metal oxide and be etched and damage.
Optionally, the material of active layer of metal oxide 03 may include: IGZO (English: indium gallium zinc
oxide；Chinese: indium gallium zinc oxide), zinc oxide, tin oxide etc..
It should be noted that the both ends of active layer of metal oxide 03 are required to be electrically connected with source-drain electrode layer 05.Assuming that battle array
The metal structure 02 of every one end in column substrate 0 for being electrically connected source-drain electrode layer 05 and active layer of metal oxide 03 is one group of gold
Belong to structure 02, then array substrate 0 provided in an embodiment of the present invention may include one group of metal structure 02 or two groups of metal structures 02
(in Fig. 1 by taking two groups of metal structures 02 as an example), the embodiment of the present invention is not construed as limiting this.Also, every group of metal structure 02 can be with
Structure 02 is included one or more metals, in Fig. 1 by taking every group of metal structure 02 is included a metal structure 02 as an example.
On the one hand, when array substrate 0 includes one group of metal structure 02, one end of active layer of metal oxide 03 can lead to
It crosses this group of metal structure 02 to be electrically connected with source-drain electrode layer 05, the other end of active layer of metal oxide 03 can directly and source-drain electrode
Layer 05 is electrically connected.
On the other hand, when array substrate 0 includes: two groups of metal structures 02 being spaced apart from each other, in the first insulating layer 04
First via hole 11 is connected to one by one with the metal structure 02 in metal structure 02；Source-drain electrode layer 05 includes: the first source electrode 051 and first
Drain electrode 052, the first source electrode 051 are electrically connected with one group of metal structure 02 by the first via hole 11 that one group of metal structure 02 is connected to,
First drain electrode 052 is electrically connected with another group of metal structure 02 by the first via hole 11 that another group of metal structure 02 is connected to.It needs
Illustrate, when array substrate 0 includes two groups of metal structures 02, the both ends of active layer of metal oxide 03 can pass through gold
Belong to structure 02 to be electrically connected with source-drain electrode layer 05, at this point, the both ends of active layer of metal oxide 03 will not be etched.
Optionally, which can be respectively positioned on active layer of metal oxide 03 close to or far from substrate 01
Side is respectively positioned on active layer of metal oxide 03 close to the side of substrate 01 with this two groups of metal structures 02 in Fig. 1.Optionally,
This two groups of metal structures 02 can also be respectively positioned on side of the active layer of metal oxide 03 far from substrate 01；Alternatively, one group of metal
Structure 02 is located at active layer of metal oxide 03 close to the side of substrate 01, and another group of metal structure 02 has positioned at metal oxide
Side of the active layer 03 far from substrate 01.
Further, array substrate 0 can also include: positioned at active layer of metal oxide 03 and the first insulating layer 04 it
Between, and the 4th insulating layer 011 and second grid 012 successively arranged along the direction far from substrate 01.Second grid in Fig. 1
012, the 4th insulating layer 011, the first source electrode 051, first drain electrode 052, active layer of metal oxide 03, metal structure 02 can groups
At metal oxide thin-film transistor.The orthographic projection region of 4th insulating layer on substrate is located at active layer of metal oxide and exists
In orthographic projection region on substrate.It the orthographic projection region of second grid on substrate can be with the positive throwing of the 4th insulating layer on substrate
In the domain of shadow zone.
Optionally, Fig. 2 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention, as shown in Fig. 2,
On the basis of Fig. 1, which can also include: active along the low temperature polycrystalline silicon successively arranged of direction far from substrate 01
Layer 06, second insulating layer 07, first grid 08 and third insulating layer 09, source-drain electrode layer 05 further include: the second source electrode 053 and second
Drain electrode 054.
Wherein, metal structure 02 and active layer of metal oxide 03 be respectively positioned on third insulating layer 09 and the first insulating layer 04 it
Between, the orthographic projection region of low-temperature polysilicon silicon active layer 06 and active layer of metal oxide 03 on substrate 01, which exists, to be spaced；Array
Substrate 0 has two group of second via hole 12, and the second via hole 12 runs through the first insulating layer 04, second insulating layer 07 and third insulating layer
09, and it is connected to low-temperature polysilicon silicon active layer 06；Second source electrode 053 passes through one group of second via hole 12 and low-temperature polysilicon silicon active layer 06
Electrical connection；Second drain electrode 054 is electrically connected by another group of the second via hole 12 with low-temperature polysilicon silicon active layer 06.The third insulating layer
09 may include: the insulating layer ontology 091 and upper buffer layer 092 successively arranged along the direction far from substrate.
Figure it is seen that one end of the second via hole 12 is concordant with one end of the first via hole 11, it is respectively positioned on the first insulating layer
04 surface far from substrate 01.But the other end arrival low-temperature polysilicon silicon active layer 06 of the second via hole 12, and the first via hole 11
The other end only arrives at active layer of metal oxide 03, and low-temperature polysilicon silicon active layer 06 is lower than active layer of metal oxide 03,
Therefore, the depth of the second via hole 12 is greater than the depth of the first via hole 11.
Above-mentioned second grid 012, the 4th insulating layer 011, the first source electrode 051, first drain electrode 052, metal oxide are active
Layer 03, metal structure 02 can form metal oxide thin-film transistor.Above-mentioned low-temperature polysilicon silicon active layer 06, second insulating layer
07, first grid 08, third insulating layer 09, the second source electrode 053 and the second drain electrode 054 can form low-temperature polysilicon film crystal
Pipe.It should be noted that array substrate provided in an embodiment of the present invention may include that one or more metal-oxide films are brilliant
Body pipe, and one or more polycrystalline SiTFTs, can also include other kinds of thin film transistor (TFT), and the present invention is implemented
Example is not construed as limiting this.
Optionally, array substrate 0 further include: the capacitance structure between the first insulating layer 04 and third insulating layer 09
010.Illustratively, the capacitance structure 010 may include: along far from substrate 01 direction successively arrange first electrode 01001, absolutely
Edge block 01002 and second electrode 01003.It orthographic projection region of the first electrode 01001 on substrate 01 can be with first grid 08
Orthographic projection area coincidence on substrate 01, orthographic projection region of the first electrode 01001 on substrate 01 can also and the first grid
There is no overlapping, the embodiment of the present invention to be not construed as limiting to this in orthographic projection region of the pole 08 on substrate 01.01002 He of collets
Second electrode 01003 can be located at orthographic projection of the first electrode 01001 on substrate 01 in the orthographic projection region on substrate 01
In region
The first electrode 01001 can be same layer structure with metal structure 02.It should be noted that if two structures are same
Layer structure, then the two structures are that can manufacture simultaneously obtained structure by one-time process.For example, the first electrode 01001
It is same layer structure with metal structure 02, then explanation is made to the first electrode while manufacturing metal structure 02
01001, so as to reduce manufacturing process.
Again optionally, second electrode 01003 and second grid 012 are same layer structure, and/or, collets 01002 and the 4th
Insulating layer 011 is same layer structure.The embodiment of the present invention, for same layer structure, and is insulated with second electrode 01003 and second grid 012
Block 01002 and the 4th insulating layer 011 is for same layer structures.Alternatively it is also possible to be second electrode 01003 and second grid
012 is same layer structure or collets 01002 and the 4th insulating layer 011 is same layer structure.As it can be seen that provided in an embodiment of the present invention
Same layer structure in array substrate is more, therefore the manufacturing process of array substrate provided in an embodiment of the present invention is simpler, accordingly
Manufacture efficiency it is also higher.
Optionally, with continued reference to FIG. 2, the array substrate 0 can also include: positioned at source-drain electrode layer 05 far from one side of substrate
Passivation layer 014, the first PLN (English: Planarization；Chinese: flat) layer 015, connection electrode layer 016, the 2nd PLN
Layer 017, OLED (English: Organic Light-Emitting Diode；Chinese: Organic Light Emitting Diode) anode 018, as
Element defines layer 019 and PS (English: Photo spacer；Also referred to as: supporter) 020.Wherein, it is illustrated only in OLED in Fig. 2
Anode 018, which can also include the electroluminescence layer formed after forming pixel defining layer 019 and cathode (in Fig. 2
It is not shown)；Connection electrode 016 may include: source connection electrode 0161 and leakage connection electrode 0162.Source connection electrode 0161 is logical
Via hole in transpassivation layer 014 and the first PLN layer 015 is electrically connected with the second source electrode 053, and leakage connection electrode 0162 passes through passivation layer
014 and the first via hole in PLN layer 015 be electrically connected with the second drain electrode 054.Anode 018 in OLED can be by the 2nd PLN layers
Via hole in 017 is electrically connected with leakage connection electrode 0162.
Substrate 01 may include: substrate bulk 0101, and be located at active positioned at substrate bulk 0101 and low temperature polycrystalline silicon
Bottom breaker 0102 between layer 06.Optionally, the structure in above structure in addition to substrate bulk 0101 can be located at lining
Effective display area domain (the English: Active Area of copy for the record or for reproduction body 0101；In (not marked in Fig. 2) referred to as: AA), also, lower buffering
Layer 0102, second insulating layer 07, third insulating layer 09, the first insulating layer 04, passivation layer 014 are also extend to substrate bulk
0101 noneffective display area domain (not marked in Fig. 2).Optionally, array substrate provided in an embodiment of the present invention can be flexibility
Substrate can not also be flexible base board, and when the array substrate is flexible base board, the material of substrate bulk 0101 can be flexibility
Material, such as polyimides (English: Polyimide；Referred to as: PI).When array substrate is flexible base board, substrate bulk 0101
On noneffective display area can also form fluted X, can be exhausted through second insulating layer 07, third with groove X in Fig. 2
Edge layer 09, the first insulating layer 04 and passivation layer 014, and only for through part bottom breaker 0102.Alternatively, groove X can also
To run through bottom breaker 0102, second insulating layer 07, third insulating layer 09, the first insulating layer 04 and passivation layer 014, this hair simultaneously
Bright embodiment is not construed as limiting this.
It should be noted that the noneffective display area of substrate bulk 0101 may include: bending (English: bending) area,
And other regions (being not shown in Fig. 2), region of the groove X where go substrate bulk 0101 can be substrate bulk 0101
In bent area.So, when the bent area of substrate bulk 0101 is bent, due to having groove X on the bent area,
Film layer on bent area is less, so, the case where being broken off there is no the film layer on bent area.
Fig. 3 is a kind of array substrate that the relevant technologies provide, as shown in figure 3, the array substrate 2 may include: substrate 21,
And low-temperature polysilicon film transistor and metal oxide thin-film transistor on substrate 21.
When manufacturing array substrate 2, need first to sequentially form low-temperature polysilicon silicon active layer 221, first on substrate 21 exhausted
Edge layer 222, first grid 223, second insulating layer 224, active layer of metal oxide 231, third insulating layer 232, second grid
233, third grid 242 and the 4th insulating layer 234.And the 5th insulating layer is also formed while forming third insulating layer 232
243.Then, it is formed and runs through the first insulating layer 222, second insulating layer 224 and the 4th insulating layer 234, and be connected to low temperature polycrystalline silicon
Two the first via holes 24 of active layer 221, and formed through the 4th insulating layer 234 and connection active layer of metal oxide 231
Two the second via holes 25.Finally, forming source-drain electrode layer 26, which includes: low-temperature polysilicon film transistor 22
The first source-drain electrode 261 and metal oxide thin-film transistor 23 the second source-drain electrode 262.
Substrate 21 may include substrate bulk 2101, and be located at substrate bulk 2101 and low-temperature polysilicon silicon active layer 221
Between bottom breaker 2102.Second insulating layer 224 may include: insulating layer ontology 2241 and upper buffer layer 2242.The array
Substrate 2 can also include: passivation layer 244, the first PLN layer 245, connection electrode layer positioned at source-drain electrode layer 26 far from one side of substrate
246, the 2nd PLN layer 247, the anode 248 of OLED, pixel defining layer 249 and PS 250.
Wherein, the first source-drain electrode 261 is electrically connected low-temperature polysilicon silicon active layer 221, the second source by two the first via holes 24
Drain electrode 262 is electrically connected active layer of metal oxide 03 by two the second via holes 24.It needs to etch due to forming the first via hole 24
Three insulating layers, and forming the second via hole 25 only needs one insulating layer of etching, therefore, duration needed for forming the second via hole 25 is small
The duration needed for forming the first via hole 24.Also, the material of active layer of metal oxide is metal oxide, metal oxide
It is easy to be etched by the engraving of insulating layer.If desired the first via hole 24 and the second via hole 25 are formed in an etching technics,
Then after etching forms the second via hole 25, the higher active layer of metal oxide 231 of activity is easier to be etched and be damaged.
If in the related technology etching the first via hole 24 and the second via hole 25 respectively, for example the first via hole is etched by an etching technics
24, the second via hole 25 is etched further through another secondary etching technics, then the manufacturing step that will lead to array substrate is cumbersome, manufacture effect
Rate is lower.
And in array substrate provided in an embodiment of the present invention, since active layer of metal oxide and source-drain electrode layer pass through metal
Structure electrical connection, and it is connected to the metal structure with the first via hole etched when source-drain electrode layer in connection metal structure, and do not connect
Logical active layer of metal oxide.If desired the first via hole and the second via hole are etched using an etching technics, then in the first via hole
After etching, if etching technics is also not finished, active layer of metal oxide due to not being connected to the first via hole, so
Active layer of metal oxide will not be etched and be destroyed.Also, since the activity of metal structure is lower, although golden
Belong to structure to be connected to the first via hole, metal structure is also not easy to be etched.Also, it can be etched simultaneously by an etching technics
The first via hole and the second via hole are obtained, therefore, the manufacture efficiency of array substrate is higher.
In addition, the insulating layer in Fig. 3 between first grid 223 and third grid 242 and the two grids can form
Capacitance structure.From figure 3, it can be seen that the insulating layer between the two grids is more (having three-layer insulated layer), lead to the two grid
The spacing of pole is larger, and therefore, the capacitor of the capacitance structure formed in the related technology is smaller.And array provided in an embodiment of the present invention
In substrate, between two electrodes (first electrode 01001 and second electrode 01003) in capacitance structure 010 only between be separated with one
Collets 01002, therefore the spacing of the two electrodes is smaller, the capacitor of capacitance structure is larger.
In conclusion due in array substrate provided in an embodiment of the present invention, active layer of metal oxide and source-drain electrode layer
It is electrically connected by metal structure, and is connected to the metal structure with the first via hole etched when source-drain electrode layer in connection metal structure,
And it is not connected to active layer of metal oxide.Therefore, during etching the first via hole, active layer of metal oxide will not be carved
Erosion.Also, since the activity of metal is lower than the activity of metal oxide, during etching the first via hole, metal structure
Also it is not easy to be etched.So source-drain electrode layer can be effectively electric with active layer of metal oxide by metal structure in array substrate
Connection, and can be avoided active layer of metal oxide and be etched and damage.
Fig. 4 is a kind of manufacturing method of array substrate provided in an embodiment of the present invention, and this method is shown in FIG. 1 for manufacturing
Array substrate, as shown in figure 4, the manufacturing method of the array substrate may include:
Metal structure, and the metal oxide being sequentially overlapped along the direction far from substrate is formed on the substrate in step 401
Active layer and the first insulating layer, wherein the material of active layer of metal oxide includes metal oxide, and metal structure is located at substrate
And first between insulating layer, and is electrically connected with active layer of metal oxide.
Step 402 carries out patterned process to the structure formed on substrate, to be formed through the first insulating layer and connection gold
Belong to the first via hole of structure.
Step 403 forms source-drain electrode layer on the first insulating layer, wherein source-drain electrode layer passes through the first via hole and metal knot
Structure electrical connection.
In conclusion metal oxide is active in the array substrate as prepared by method provided in an embodiment of the present invention
Layer is electrically connected with source-drain electrode layer by metal structure, and is connected in connection metal structure with the first via hole etched when source-drain electrode layer
The metal structure, and it is not connected to active layer of metal oxide.Therefore, during etching the first via hole, metal oxide has
Active layer will not be etched.Also, since the activity of metal is lower than the activity of metal oxide, etch the mistake of the first via hole
Cheng Zhong, metal structure are also not easy to be etched.So source-drain electrode layer can pass through metal structure and metal oxide in array substrate
Active layer is effectively electrically connected, and be can be avoided active layer of metal oxide and be etched and damage.
Fig. 5 is the manufacturing method of another array substrate provided in an embodiment of the present invention, and this method can be used for manufacturing such as
Array substrate shown in Fig. 2, as shown in figure 5, the manufacturing method of the array substrate may include:
Step 501, to sequentially form low-temperature polysilicon silicon active layer, second insulating layer, first grid and third on substrate exhausted
Edge layer.
It should be noted that the substrate in the embodiment of the present invention can be the substrate of any one type, such as flexible liner
Bottom or rigid substrate, in the embodiment of the present invention by taking substrate is flexible substrate as an example.Illustratively, substrate may include the substrate of superposition
Ontology and bottom breaker, the material of the substrate bulk can be flexible material.It is active that low temperature polycrystalline silicon is sequentially formed on substrate
Layer, second insulating layer, first grid and third insulating layer can be with are as follows: sequentially form in bottom breaker far from the surface of substrate bulk
Low-temperature polysilicon silicon active layer, second insulating layer, first grid and third insulating layer.
It, can be first on substrate using coating, physical vapour deposition (PVD) when low-temperature polysilicon silicon active layer is formed on the substrate
(English: Physical Vapor Deposition；Referred to as: PVD) or chemical vapor deposition is (English: Chemical Vapor
Deposition；The methods of referred to as: CVD) form low temperature polycrystalline silicon material layers.Later, which is carried out
Patterned process, to obtain low-temperature polysilicon silicon active layer.The patterned process may include: photoresist coating processes, exposure work
Skill, developing process, etching technics and photoresist stripping process.
After forming low-temperature polysilicon silicon active layer 06 on substrate 01 (including substrate bulk 0101 and bottom breaker 0102), such as
Shown in Fig. 6, second insulating layer 07, first grid 08 and third insulating layer 09 can be sequentially formed again.Wherein, third insulating layer 09
It may include the insulating layer ontology 091 and upper buffer layer 092 successively arranged along the direction far from substrate；Form second insulating layer
07, the process of insulating layer ontology 091 and upper buffer layer 092 can refer to the process of above-mentioned formation low temperature polycrystalline silicon material layers, shape
The process of above-mentioned formation low-temperature polysilicon silicon active layer can be referred at the process of first grid 08, the embodiment of the present invention is not done herein
It repeats.
Step 502 forms metal pattern on the substrate for being formed with third insulating layer, which includes: mutual
Every two groups of metal structures and first electrode.
After forming third insulating layer, metal material layer can be formed far from the surface of substrate in third insulating layer first
(process can be with reference to the process for forming low temperature polycrystalline silicon material layers in step 501).Later, figure is carried out to the metal material layer
To obtain metal pattern, (the patterned process process can be referred in step 501 to low temperature polycrystalline silicon material layers figure for caseization processing
The process of caseization processing).
Metal pattern includes two groups of metal structures and first electrode, wherein the metal structure number in two groups of metal structures
Can be identical or different, every group of metal structure may include at least one (such as one or two lamp) metal structure.Illustratively,
The metal structure 02 and first electrode 01001 being prepared in step 502 can be as shown in Figure 7, wherein every group of metal structure 02
It only include a metal structure 02.Optionally, orthographic projection region of the first electrode 01001 on substrate 01 can and first grid
There is overlapping in 08 orthographic projection region on substrate 01, orthographic projection region of the first electrode 01001 on substrate 01 can also be with
There is no overlapping, the embodiment of the present invention to be not construed as limiting to this in orthographic projection region of the first grid 08 on substrate 01.
It should be noted that two groups of metal structures are for being electrically connected with the active layer of metal oxide being subsequently formed
It connects, which is an electrode of the capacitance structure that the embodiment of the present invention needs to form.In the embodiment of the present invention, by two groups
Metal structure is formed simultaneously with first electrode, can obtain two groups of metal structures and first simultaneously using a patterned process
Electrode, so that the manufacturing step of array substrate greatly simplifies, and improves the manufacture efficiency of array substrate.
Step 503 forms active layer of metal oxide on the substrate for being formed with two groups of metal structures, the metal oxide
Active layer is electrically connected with two groups of metal structures.
After forming two groups of metal structures, it can continue that metal oxide material layers are formed on the substrate, and to the gold
Belong to oxide material layer and carry out patterned process, to obtain active layer of metal oxide.Wherein, metal oxide material layers are formed
Process pattern can be carried out to metal oxide material layers with reference to the process for forming low temperature polycrystalline silicon material layers in step 501
The process for changing processing can be with reference to the process that in step 501 low temperature polycrystalline silicon material layers are carried out with patterned process, and the present invention is real
Applying example, this will not be repeated here.
Optionally, active layer of metal oxide can cover the partial region in two metal structures, so that two
Metal structure is electrically connected with active layer of metal oxide.Illustratively, the active layer of metal oxide 03 that is formed in step 503 with
The positional relationship of two metal structures 02 can be as shown in Figure 8.
Step 504 forms insulating pattern on the substrate for be formed with active layer of metal oxide, which includes:
4th insulating layer and collets.
After forming active layer of metal oxide, isolation material layer can be continuously formed on substrate, and to the insulation
Material layers carry out patterned process, to obtain insulating pattern.Wherein, the process for forming isolation material layer can refer to step 501
The middle process for forming low temperature polycrystalline silicon material layers, the process for carrying out patterned process to isolation material layer can refer to step 501
In to low temperature polycrystalline silicon material layers carry out patterned process process, this will not be repeated here for the embodiment of the present invention.
Insulating pattern may include: the 4th insulating layer and collets.It that is to say, in the embodiment of the present invention, by the 4th insulation
Layer and collets are formed simultaneously, and can obtain the 4th insulating layer and collets simultaneously using a patterned process.Such energy
Enough so that the manufacturing step of array substrate greatly simplifies, the manufacture efficiency of array substrate is improved.
Illustratively, the 4th insulating layer 011 and collets 01002 can be as shown in Figure 9.4th insulating layer is on substrate
Orthographic projection region is located in the orthographic projection region of active layer of metal oxide on substrate, and the 4th insulating layer is for the gold that insulate
Belong to oxide active layer and subsequent second grid to be formed.The orthographic projection region of the collets on substrate can be located at first
In the orthographic projection region of electrode on substrate, collets are the insulation division in the capacitance structure that the embodiment of the present invention needs to form
Point.
Step 505 forms electrode pattern on the substrate for be formed with insulating pattern, which includes: second grid
And second electrode.
After forming insulating pattern, it can continue that conductive material layer is formed on the substrate, and carry out the conductive material layer
Patterned process is to obtain electrode pattern.Wherein, the process for forming conductive material layer can be more with reference to low temperature is formed in step 501
The process of crystal silicon material layers, the process for carrying out patterned process to conductive material layer can refer in step 501 to low-temperature polysilicon
Silicon material layer carries out the process of patterned process, and this will not be repeated here for the embodiment of the present invention.
Illustratively, electrode pattern may include: second grid and second electrode.It that is to say, in the embodiment of the present invention, by
Two grids and second electrode are formed simultaneously, and can obtain second grid and second electrode simultaneously using a patterned process.
It enables to the manufacturing step of array substrate to greatly simplify in this way, improves the manufacture efficiency of array substrate.
The second grid 012 can be as shown in Figure 10, and the orthographic projection region of second grid on substrate can be with the 4th insulation
In the orthographic projection region of layer on substrate.The second electrode can be another electrode of capacitance structure in array substrate, second
Electrode 01003 can be as shown in Figure 10, and the orthographic projection region of second electrode on substrate can be located at first electrode on substrate
Orthographic projection region in.First electrode 01001, collets 01002 and second electrode 01003 collectively constitute capacitance structure 010.
Step 506 forms the first insulating layer on the substrate for be formed with electrode pattern.
It after forming electrode pattern, can continue that the first insulating layer is formed on the substrate.Wherein, the first insulating layer is formed
Process can be with reference to the process for forming low temperature polycrystalline silicon material layers in step 501.The first insulating layer 04 formed in step 506 can
With as shown in figure 11.
Step 507 carries out patterned process to the structure that is formed on substrate, to form the first via hole, the second via hole and the
Three via holes.
In a first aspect, the first via hole formed in step 507 is one by one connected to through the first insulating layer and with metal structure.Than
When as formed two metal structures in step 502, it will form two the first via holes, and the two first via holes in step 507
It is connected to one by one with the two metal structures.Second aspect forms two group of second via hole in step 507, and each second via hole is equal
Through the first insulating layer, second insulating layer and third insulating layer, and it is connected to low-temperature polysilicon silicon active layer.The third aspect, step 507
The first via hole and the second via hole of middle formation can be located in the effective display area domain of substrate bulk, but above-mentioned third via hole can
To be located in the noneffective display area domain of substrate bulk, and can be through the first insulating layer, second insulating layer and third insulation
Layer.Illustratively, the position of the first via hole 11, the second via hole 12 and third via hole 13 that are obtained in step 507 by patterned process
It sets and is shown in Fig.12.
Optionally, first via hole, the second via hole and third via hole can etch to obtain using an etching technics.Its
In, since the first via hole and third via hole cross hole depth than second, etching technics is not also after the first via etch
Terminate, but active layer of metal oxide is with the first via hole due to not being connected to, so active layer of metal oxide will not be etched
And it is destroyed.Also, since the activity of metal structure is lower, although metal structure is connected to the first via hole, metal knot
Structure is also not easy to be etched.Also, it can etch to obtain the first via hole, the second via hole and third simultaneously by an etching technics
Via hole, therefore, the manufacture efficiency of array substrate are higher.
Step 508, on the substrate for being formed with the first insulating layer formed source-drain electrode layer, source-drain electrode layer include: the first source electrode,
First drain electrode, the second source electrode and the second drain electrode.
The first insulating layer is being formed, and after forming above-mentioned via hole, conductive material layer can continuously formed on substrate, and right
The conductive material layer carries out patterned process to obtain source-drain electrode layer.Wherein, the process for forming conductive material layer can be with reference to step
The process that low temperature polycrystalline silicon material layers are formed in rapid 501, the process for carrying out patterned process to conductive material layer can be with reference to step
In rapid 501 low temperature polycrystalline silicon material layers are carried out with the process of patterned process, this will not be repeated here for the embodiment of the present invention.
First source electrode is electrically connected by one group of first via hole with active layer of metal oxide, and the first drain electrode passes through another group
First via hole is electrically connected with active layer of metal oxide.Second source electrode passes through one group of second via hole and low-temperature polysilicon silicon active layer electricity
Connection, the second drain electrode are electrically connected by another group of the second via hole with low-temperature polysilicon silicon active layer.Illustratively, it is formed in step 508
Source-drain electrode layer 05 in the first source electrode 051, first drain the position of the 052, second source electrode 053 and the second drain electrode 054 can be such as figure
Shown in 13.
Step 509, sequentially formed on the substrate for being formed with source-drain electrode layer passivation layer, the first PLN layers, connection electrode layer,
The anode of OLED, the 2nd PLN layers, pixel defining layer and PS.
After forming passivation layer, the via hole of the second source electrode of connection and the second drain electrode can also be formed in the passivation layer (as schemed
The via hole 14 of the second source electrode, and the via hole 15 of the second drain electrode of connection are connected in 14), and the 4th via hole of connection third via hole
(the 4th via hole 16 in such as Figure 14).Optionally, the connectivity slot of connection third via hole can also be formed in bottom breaker later
(connectivity slot 17 in such as Figure 15).Third via hole 13, the 4th via hole 16 are connected to connectivity slot 17, collectively constitute the non-of substrate bulk
Groove X on display area.
Later, it can continue to sequentially form the first PLN layers, connection electrode layer, the 2nd PLN layers, the sun of OLED on substrate
Pole, pixel defining layer and PS, to obtain array substrate shown in Fig. 2.Wherein, as shown in Fig. 2, forming the first PLN layer
Afterwards, two groups of via holes in the first PLN layer 015 can also be formed.Connection electrode 016 may include: source connection electrode 0161
With leakage connection electrode 0162.Source connection electrode 0161 passes through the via hole and the second source electrode in passivation layer 014 and the first PLN layer 015
053 electrical connection, leakage connection electrode 0162 are electrically connected by the via hole in passivation layer 014 and the first PLN layer 015 with the second drain electrode 054
It connects.The 2nd is being formed after PLN layer, via hole can also formed in PLN layer the 2nd, so that the anode of the OLED of formation passes through the
Via hole in two PLN layers 017 is electrically connected with leakage connection electrode 0162.
In conclusion metal oxide is active in the array substrate as prepared by method provided in an embodiment of the present invention
Layer is electrically connected with source-drain electrode layer by metal structure, and is connected in connection metal structure with the first via hole etched when source-drain electrode layer
The metal structure, and it is not connected to active layer of metal oxide.Therefore, during etching the first via hole, metal oxide has
Active layer will not be etched.Also, since the activity of metal is lower than the activity of metal oxide, etch the mistake of the first via hole
Cheng Zhong, metal structure are also not easy to be etched.So source-drain electrode layer can pass through metal structure and metal oxide in array substrate
Active layer is effectively electrically connected, and be can be avoided active layer of metal oxide and be etched and damage.
The embodiment of the invention provides a kind of display panel, which may include provided in an embodiment of the present invention
Array basal plate (such as array substrate shown in fig. 1 or fig. 2).
The embodiment of the invention provides a kind of display device, which may include above-mentioned display panel.
The display device can be with are as follows: Electronic Paper, mobile phone, tablet computer, television set, display, laptop, digital phase
Any products or components having a display function such as frame, navigator.
It should be noted that embodiment of the method provided in an embodiment of the present invention can mutually join with corresponding Installation practice
It examines, it is not limited in the embodiment of the present invention.The sequencing of embodiment of the method step provided in an embodiment of the present invention can be into
Row appropriate adjustment, step also according to circumstances can accordingly be increased and decreased, and anyone skilled in the art is in this hair
In the technical scope of bright exposure, the method that can readily occur in variation be should be covered by the protection scope of the present invention, therefore not
It repeats again.
Term "and/or" in the present invention, only a kind of incidence relation for describing affiliated partner, indicates may exist three kinds
Relationship, for example, A and/or B, can indicate: individualism A exists simultaneously A and B, these three situations of individualism B.In addition, this
Character "/" in text typicallys represent the relationship that forward-backward correlation object is a kind of "or".
The foregoing is merely the alternative embodiments of the application, not to limit the application, it is all in spirit herein and
Within principle, any modification, equivalent replacement, improvement and so on be should be included within the scope of protection of this application.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate (0) includes: substrate (01) and metal structure (02), and
Active layer of metal oxide (03), the first insulating layer (04) and the source-drain electrode successively arranged along the direction far from the substrate (01)
Layer (05),
The metal structure (02) aoxidizes between the substrate (01) and first insulating layer (04), and with the metal
Object active layer (03) electrical connection；
The array substrate (0) has the first via hole through first insulating layer (04) and the connection metal structure (02)
(11)；
The source-drain electrode layer (05) is electrically connected by first via hole (11) with the metal structure (02).
2. array substrate according to claim 1, which is characterized in that the array substrate (0) includes: two be spaced apart from each other
Group metal structure (02),
The first via hole (11) in the array substrate (0) is connected to one by one with metal structure (02)；
The source-drain electrode layer (05) include: the first source electrode (051) and first drain electrode (052), first source electrode (051) with one group
Metal structure (02) is electrically connected by the first via hole (11) that one group of metal structure (02) is connected to, first drain electrode
(052) it is electrically connected with another group of metal structure (02) by the first via hole (11) that another group of metal structure (02) is connected to.
3. array substrate according to claim 2, which is characterized in that two groups of metal structures (02) are respectively positioned on the gold
Belong to oxide active layer (03) close to or far from the side of the substrate (01).
4. array substrate according to any one of claims 1 to 3, which is characterized in that the array substrate (0) further include: edge
Far from the substrate (01) direction successively arrange low-temperature polysilicon silicon active layer (06), second insulating layer (07), first grid
(08) and third insulating layer (09), the source-drain electrode layer (05) further include: the second source electrode (053) and the second drain electrode (054),
The metal structure (02) and the active layer of metal oxide (03) are respectively positioned on the third insulating layer (09) and described
Between first insulating layer (04), the low-temperature polysilicon silicon active layer (06) and the active layer of metal oxide (03) are in the lining
There is interval in the orthographic projection region on bottom (01)；
The array substrate (0) has two group of second via hole (12), and second via hole (12) runs through first insulating layer
(04), the second insulating layer (07) and the third insulating layer (09), and it is connected to the low-temperature polysilicon silicon active layer (06)；
Second source electrode (053) is electrically connected by the second via hole (12) described in one group with the low-temperature polysilicon silicon active layer (06)
It connects；Second drain electrode (054) is electrically connected by the second via hole (12) described in another group and the low-temperature polysilicon silicon active layer (06)
It connects.
5. array substrate according to claim 4, which is characterized in that the array substrate (0) further include: be located at described the
Capacitance structure (010) between one insulating layer (04) and the third insulating layer (09).
6. array substrate according to claim 5, which is characterized in that the capacitance structure (010) includes: along far from described
First electrode (0101), collets (0102) and the second electrode (0103) that the direction of substrate (01) is successively arranged, described first
Electrode (0101) and the metal structure (02) are same layer structure.
7. array substrate according to claim 6, which is characterized in that
The array substrate (0) further include: be located at the active layer of metal oxide (03) and first insulating layer (04) it
Between, and the 4th insulating layer (011) and second grid (012) successively arranged along the direction far from the substrate (01)；
The second electrode (0103) and the second grid (012) are same layer structure, and/or, the collets (0102) with
4th insulating layer (011) is same layer structure.
8. a kind of manufacturing method of array substrate, which is characterized in that the described method includes:
Metal structure, and the active layer of metal oxide and first being sequentially overlapped along the direction far from substrate is formed on the substrate
Insulating layer, wherein the material of the active layer of metal oxide includes metal oxide, and the metal structure is located at the substrate
It is electrically connected between first insulating layer, and with the active layer of metal oxide；
Patterned process is carried out to the structure formed on the substrate, to be formed through first insulating layer and the connection gold
Belong to the first via hole of structure；
Source-drain electrode layer is formed on the first insulating layer, wherein the source-drain electrode layer passes through first via hole and the gold
Belong to structure electrical connection.
9. a kind of display panel, which is characterized in that the display panel includes any array substrate of claim 1 to 7.
10. a kind of display device, which is characterized in that the display device includes display panel as claimed in claim 9.
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