CN110164873A - Production method, array substrate, display panel and the display device of array substrate - Google Patents
Production method, array substrate, display panel and the display device of array substrate Download PDFInfo
- Publication number
- CN110164873A CN110164873A CN201910464234.4A CN201910464234A CN110164873A CN 110164873 A CN110164873 A CN 110164873A CN 201910464234 A CN201910464234 A CN 201910464234A CN 110164873 A CN110164873 A CN 110164873A
- Authority
- CN
- China
- Prior art keywords
- layer
- region
- dry etching
- array substrate
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
Abstract
The invention discloses a kind of production method of array substrate, array substrate, display panel and display devices, patterned process is carried out to the photoresist layer that is formed on planarization layer, makes the other parts reserve part in the part first through hole of thin film transistor (TFT) drain electrode top without photoresist layer, first through hole that photoresist layer, the photoresist layer above color blocking layer be divided to be fully retained；In the subsequent progress dry etching processing to passivation layer, since only photoresist layer is divided in reserve part for the other parts of first through hole, the photoresist layer that the other parts of middle first through hole are fully retained compared with the prior art is relatively thin, and the present invention is conducive to form preferable dry etching angle in dry etching passivation layer；In addition the photoresist layer thickness above color blocking layer of the present invention compared with the prior art in photoresist layer thickness above color blocking layer it is thicker, when carrying out dry etching to passivation layer, it can prevent from generating the planarization layer above color blocking dry etching damage, avoid so that the possibility that subsequent organic luminous layer vapor deposition exception and organic film transmitance reduce.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of production method of array substrate, array substrate, display surface
Plate and display device.
Background technique
Currently, thin film transistor (TFT) (Thin Film Transistor, TFT) is liquid crystal display and the organic hair of active matrix
The main driving element of optical diode (Active Matrix Organic Light Emitting Diode, AMOLED).
Recent large scale OLED because of its high contrast, self-luminous and gradually at TV new hot-spot for growth due to become development and lead
Stream, wherein the TFT of top gate structure has high on-state current, more high aperture compared to the TFT of bottom grating structure in large scale OLED
It attracts attention with better TFT stability.Large scale OLED uses WRGB coloured silk membrane technology at present, i.e., is BGR blunt in array
Change on layer (Array PVX), and since the high colour gamut requirement of product and color membrane material are limited, the thickness of BGR is thicker by (one at present
As >=3.0 μm), since the thickness of BGR is thicker, to guarantee flattening effect, corresponding organic planarization layer (Resin) is also thick
(general >=3.3 μm).To guarantee passivation layer via hole, one can be formed in TFT zone when carrying out planarization layer process and led to without Resin
Hole, at subsequent passivation layer via hole exposure mask (source-drain electrode metal connect via hole with ITO) since photoresist mobility itself can make
Photoresist is compared with pixel region thickness in Resin through-hole, and pixel region photoresist is thin, and the thicker dry etching Profile of photoresist thickness is by shadow in Resin
It ringing, etch rate is slack-off, and since pixel region photoresist is relatively thin when passivation layer via hole dry etching, it may be to pixel region
Planarization layer generate dry etching damage (DE Damage) so that subsequent organic luminous layer (EL) vapor deposition exception and organic film it is saturating
Cross rate reduction.
Summary of the invention
The embodiment of the present invention provides production method, array substrate, display panel and the display device of a kind of array substrate, uses
To solve problems of the prior art.
Therefore, the embodiment of the invention provides a kind of production methods of array substrate, comprising:
Thin film transistor (TFT), passivation layer, color blocking layer and planarization layer are sequentially formed on underlay substrate；Wherein, the film
The orthographic projection of transistor and the color blocking layer on the underlay substrate is not overlapped, and the planarization layer is in the thin film transistor (TFT)
Top have first through hole；
Photoresist layer is formed on the planarization layer with the first through hole；
Patterned process is carried out to the photoresist layer, forms photoetching agent pattern；The photoetching agent pattern includes going completely
Except region, first part retain region and region is fully retained；Wherein, the region that completely removes is in the first through hole range
Interior and be located above the drain electrode, the first part retains region and is covered by the first through hole, and the photoresist is protected completely
Stay color blocking layer region described in region overlay；
Using the photoetching agent pattern as blocking, dry etching processing, the passivation are carried out to the passivation layer of exposing
Layer forms the second through-hole in the corresponding position in region that completely removes；
Remove the photoetching agent pattern；
Anode is formed on the planarization layer, the anode is electrically connected by second through-hole with the drain electrode.
Optionally, in the specific implementation, described in the production method of above-mentioned array substrate provided in an embodiment of the present invention
Photoetching agent pattern further includes that second part retains region, and the second part retains region and the thin film transistor (TFT) and described
Orthographic projection of the color blocking layer on the underlay substrate is not overlapped, and the photoresist thickness in second part reservation region is greater than
The first part retains the photoresist thickness in region.
Optionally, in the specific implementation, in the production method of above-mentioned array substrate provided in an embodiment of the present invention, to institute
It states photoresist layer and carries out patterned process, specifically include: the photoresist layer being carried out at patterning using intermediate tone mask plate
Reason；The intermediate tone mask plate includes: to completely remove the corresponding complete transmission region in region with described, is protected with the first part
The corresponding first part's transmission region in region is stayed, second part transmission region corresponding with second part reservation region, with
It is described that the corresponding light tight region in region is fully retained；The light transmission capacity of first part's transmission region is the complete transparent area
The 50% of the light transmission capacity in domain, the light transmission capacity of the second part transmission region are the 10% of the light transmission capacity of the complete transmission region
~20%.
Optionally, in the specific implementation, described in the production method of above-mentioned array substrate provided in an embodiment of the present invention
First part retain region photoetching agent pattern with a thickness of 1.5 μm -1.8 μm, the photoetching agent pattern that region is fully retained
With a thickness of 2.1 μm, the second part retain the photoetching agent pattern in region with a thickness of 1.7 μm -1.9 μm.
Optionally, in the specific implementation, in the production method of above-mentioned array substrate provided in an embodiment of the present invention, to dew
The passivation layer out carries out dry etching processing, specifically includes:
Using O2And CF4Combination gas to the passivation layer carry out dry etching processing, the O2With the CF4Ratio
Example is variation.
Optionally, in the specific implementation, it in the production method of above-mentioned array substrate provided in an embodiment of the present invention, uses
Dry etching carries out dry etching processing to the passivation layer at least twice, wherein the O in dry etching each time2And CF4Ratio
Example is fixed, the O in adjacent dry etching twice2And CF4Ratio be variation.
Optionally, in the specific implementation, it in the production method of above-mentioned array substrate provided in an embodiment of the present invention, uses
Dry etching carries out dry etching processing to the passivation layer twice, wherein O in first time dry etching2Ratio be greater than second
O in secondary dry etching2Ratio.
Optionally, in the specific implementation, described in the production method of above-mentioned array substrate provided in an embodiment of the present invention
O in first time dry etching2Content be 55%~65%, CF4 content be 35%~45%；Second of dry etching
Middle O2Content be 15%~35%, CF4 content be 65%~85%.
Optionally, in the specific implementation, it in the production method of above-mentioned array substrate provided in an embodiment of the present invention, uses
Dry etching carries out dry etching processing, during the treatment, the O to the passivation layer2Ratio gradually decrease.
Correspondingly, the embodiment of the invention also provides a kind of array substrates, using above-mentioned provided in an embodiment of the present invention
Production method described in one is made.
Optionally, in the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, second through-hole
There are at least two angles of gradient between section and the underlay substrate, be directed toward along the underlay substrate far from the underlay substrate
The degree in direction, the angle of gradient gradually decreases.
Correspondingly, the embodiment of the invention also provides a kind of display panels, including above-mentioned battle array provided in an embodiment of the present invention
Column substrate.
Correspondingly, the embodiment of the invention also provides a kind of display device, including it is provided in an embodiment of the present invention above-mentioned aobvious
Show panel.
The embodiment of the present invention the utility model has the advantages that
Production method, display panel and the display device of array substrate provided in an embodiment of the present invention, by being formed in
Photoresist layer on planarization layer carries out patterned process, makes not having in the part first through hole above the drain electrode of thin film transistor (TFT)
Photoresist layer, first through hole other parts reserve part divide that photoresist layer, corresponding photoresist layer is fully retained above color blocking layer；
In this way it is subsequent to passivation layer carry out dry etching processing when, due to first through hole other parts only reserve part be divided photoresist
Layer, the photoresist layer that the other parts of middle first through hole are fully retained compared with the prior art is relatively thin, and the present invention is conducive in dry etching
Preferable dry etching Profile is formed when passivation layer；In addition the relatively existing skill of photoresist layer thickness in the present invention above color blocking layer
Photoresist layer thickness in art above color blocking layer is thicker, and when carrying out dry etching to passivation layer, the present invention can be prevented in color blocking
The planarization layer of side generates dry etching damage, avoids so that subsequent organic luminous layer vapor deposition exception and organic film transmitance reduced
It may.
Detailed description of the invention
Fig. 1 is the flow chart of the production method of array substrate provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 3 A to Fig. 3 E be array substrate provided in an embodiment of the present invention production method in execute cuing open after each step
Face structural schematic diagram.
Specific embodiment
In order to make the purpose of the present invention, the technical scheme and advantages are more clear, with reference to the accompanying drawing, to the embodiment of the present invention
The production method of the array substrate of offer, array substrate, the specific embodiment of display panel and display device carry out in detail
Explanation.
Each layer film thickness and shape do not reflect the actual proportions of array substrate in attached drawing, and purpose is schematically illustrate hair
Bright content.
The embodiment of the invention provides a kind of production methods of array substrate, as shown in Figure 1, comprising:
S101, thin film transistor (TFT), passivation layer, color blocking layer and planarization layer are sequentially formed on underlay substrate；Wherein, film
The orthographic projection of transistor and color blocking layer on underlay substrate is not overlapped, and planarization layer has first to lead in the top of thin film transistor (TFT)
Hole；
S102, photoresist layer is formed on the planarization layer with first through hole；
S103, patterned process is carried out to photoresist layer, forms photoetching agent pattern；Photoetching agent pattern includes completely removing area
Domain, first part retain region and region are fully retained；Wherein, region is completely removed within the scope of first through hole and is located at drain electrode
Top, first part retain region and are covered by first through hole, and region overlay color blocking layer region is fully retained in photoresist；
S104, using photoetching agent pattern as blocking, dry etching processing is carried out to the passivation layer of exposing, passivation layer is complete
It removes the corresponding position in region and forms the second through-hole；
S105, stripping photoresist pattern；
S106, anode is formed on planarization layer, anode is electrically connected by the second through-hole with drain electrode.
The production method of above-mentioned array substrate provided in an embodiment of the present invention, passes through the photoetching to being formed on planarization layer
Glue-line carries out patterned process, makes to lead in the part first through hole above the drain electrode of thin film transistor (TFT) without photoresist layer, first
The other parts reserve part in hole divides photoresist layer, the corresponding photoresist layer in color blocking layer top to be fully retained；In this way subsequent to blunt
When changing layer and carrying out dry etching processing, since only photoresist layer is divided in reserve part for the other parts of first through hole, compared with the prior art
The photoresist layer that the other parts of middle first through hole are fully retained is relatively thin, and the present invention is conducive to be formed in dry etching passivation layer preferably
Dry etching Profile；In addition the photoresist layer thickness in the present invention above color blocking layer compared with the prior art in above color blocking layer
Photoresist layer thickness is thicker, and when carrying out dry etching to passivation layer, the present invention can prevent from generating the planarization layer above color blocking
Dry etching damage avoids so that the possibility that subsequent organic luminous layer vapor deposition exception and organic film transmitance reduce.
Further, in the specific implementation, in order to be easily peeled off photoresist layer, in above-mentioned battle array provided in an embodiment of the present invention
In the production method of column substrate, photoetching agent pattern further includes that second part retains region, and second part retains region and film is brilliant
The orthographic projection of body pipe and color blocking layer on underlay substrate is not overlapped, and the photoresist thickness in second part reservation region is greater than
The photoresist thickness in first part's reservation region.
Further, in the specific implementation, right in the production method of above-mentioned array substrate provided in an embodiment of the present invention
Photoresist layer carries out patterned process, can specifically include: carrying out patterned process to photoresist layer using intermediate tone mask plate；
Intermediate tone mask plate includes: complete transmission region corresponding with region is completely removed, and retains region corresponding the with first part
A part of transmission region, second part transmission region corresponding with second part reservation region are corresponding with region is fully retained
Light tight region；The light transmission capacity of first part's transmission region is the 50% of the light transmission capacity of complete transmission region, second part light transmission
The light transmission capacity in region is the 10%~20% of the light transmission capacity of complete transmission region.
Further, in the specific implementation, existing in the production method of above-mentioned array substrate provided in an embodiment of the present invention
Have the photoresist generally coated in technology with a thickness of 1.8 μm, the present invention in coat photoresist layer with a thickness of 2.1 μm, by
In the mobility of photoresist, the photoresist in the first through hole of planarization layer can be made with a thickness of 3 μm -3.6 μm, therefore first part
Retain region photoetching agent pattern with a thickness of 1.5 μm -1.8 μm, be fully retained the photoetching agent pattern in region with a thickness of 2.1 μ
M, second part retain region photoetching agent pattern with a thickness of 1.7 μm -1.9 μm.The intermediate tone mask used through the invention
Plate makes the photoresist in the first through hole of planarization layer meet etching requirement, and thickness will not be due to the mobility of photoresist
It is thicker, and corresponding photoresist thickness is thicker above color blocking layer, is resistant to subsequent passivation layer etching, will not generate to planarization layer dry
Damage is carved, the reliability of panel is improved；And the thickness that second part retains the photoetching agent pattern in region is reduced to former light
The 10%~20% of photoresist is easily peeled off in subsequent stripping photoresist in this way.
When carrying out dry etching to passivation layer, work as O2It is very fast to the etch rate of photoresist when content is high；Work as CF4Content
Gao Shi etches passivation layer very fast；It is in the prior art usually only with primary etching, and O2Content be greater than CF4Ratio,
It is very fast to the etch rate of photoresist in this way, so can etch away most photoresist after the completion of passivation layer etching, make color
Photoresist above resistance layer retains relatively thin, is easy to generate planarization layer dry etching damage, influences the steaming of subsequent organic function layer
Plating.Therefore, in the specific implementation, in the production method of above-mentioned array substrate provided in an embodiment of the present invention, to the blunt of exposing
Change layer and carry out dry etching processing, can specifically include:
Using O2And CF4Combination gas to passivation layer carry out dry etching processing, O2And CF4Ratio be variation.It is logical
Cross O in change etching process2And CF4Ratio, it is possible to reduce to the etching of photoresist, retain the photoresist above color blocking layer
It is thicker, will not to planarization layer generate dry etching damage, to not influence the vapor deposition of subsequent organic function layer.
It further, in the specific implementation, can in the production method of above-mentioned array substrate provided in an embodiment of the present invention
To carry out dry etching processing to passivation layer using dry etching at least twice, wherein the O in dry etching each time2And CF4's
Ratio is fixed, the O in adjacent dry etching twice2And CF4Ratio be variation.
Further, in the specific implementation, it in the production method of above-mentioned array substrate provided in an embodiment of the present invention, adopts
Dry etching processing is carried out to passivation layer with dry etching twice, wherein O in first time dry etching2Ratio be greater than second
O in dry etching2Ratio.Specifically, O in first time dry etching2Content be 55%~65%, CF4 content be 35%
~45%；O in second of dry etching2Content be 15%~35%, CF4 content be 65%~85%.Specifically, first
Secondary dry etching uses CF4(content is 35%~45%)+O2(content is 55%~65%) carries out, and uses high source power
It is carried out with high bias power, the passivation layer of about 50% thickness is etched, due to O2Content is higher and the first through hole of planarization layer in
Photoresist thickness it is not thick, meet etching require, make passivation layer that can etch preferable dry etching angle, at the same time, due to O2
Content is high, very fast to the etch rate of photoresist, but because of the 50% of Etch Passivation thickness, therefore only consumes about 0.4 μm~0.5
The photoresist of μ m thick retains the photoresist above color blocking layer thicker, and dry etching damage will not be generated to planarization layer, thus
The vapor deposition of subsequent organic function layer is not influenced.Second of dry etching uses CF4(content is 65%~85%)+O2(content is
15%~35%) it carries out, and is carried out using high source power and high bias power, etch the passivation layer of remaining 50% thickness,
Due to CF4Content is higher, passivation layer is etched it is very fast, to the angle of passivation layer dry etching can relatively steep (60 °~70 °), but because of first
The etched passivation layer of half when secondary etching, so the dry etching angle of later half passivation layer is to the deposition of subsequent anode without shadow
It rings, and due to CF4Content is higher, O2Content it is less, can avoid dry etching process to O2It is further consumption so that dry etching process
Dry etching will not be caused to damage planarization layer.
Further, in the specific implementation, in the production method of above-mentioned array substrate provided in an embodiment of the present invention, also
Dry etching processing, during the treatment, O can be carried out to passivation layer only with a dry etching2Ratio gradually drop
It is low.
Based on the same inventive concept, the embodiment of the invention also provides a kind of array substrates, as shown in Fig. 2, using this hair
The above-mentioned production method that bright embodiment provides is made.Specifically, which includes: underlay substrate 1, is located at underlay substrate 1
On the thin film transistor (TFT) 2, passivation layer 3, color blocking layer 4 and the planarization layer 5 that are cascading, and pass through the second of passivation layer 3
The anode 6 that through-hole P2 is electrically connected with the drain electrode 21 of thin film transistor (TFT) 2.Thin film transistor (TFT) 2 specifically includes: active layer 21, grid are exhausted
Edge layer 22, grid 23, source electrode 24 and drain electrode 25, array substrate further include slow between thin film transistor (TFT) 2 and underlay substrate 1
Layer 8 is rushed, the shading metal layer 7 between buffer layer 8 and underlay substrate 1, shading metal layer 7 is used to block active layer 4, and
Interlayer insulating film 9 between source-drain electrode (24 and 25) and grid 23.
Further, in the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in Fig. 2, the
Having at least two angles of gradient between the section and underlay substrate 1 of two through-hole P2, (embodiment of the present invention using dry method twice to be carved
For losing passivation layer, there are two θ 1 and θ 2) for angle of gradient tool, are directed toward the direction far from underlay substrate 1, the angle of gradient along underlay substrate 1
Degree gradually decrease, the angle of gradient refers to that the angle between the dry etching inclined-plane of passivation layer 3 and underlay substrate 1, the i.e. degree of θ 1 are big
In the degree of θ 2.Although the angle of θ 1 is larger, the dry etching angle of passivation layer 3 is steeper, etched when etching because of first time
The passivation layer 3 of half, so the dry etching angle, θ 1 of later half passivation layer 3 is on the deposition of subsequent anode without influence.
It should be noted that array substrate provided in an embodiment of the present invention can be applied to organic electroluminescent LED
(Organic Light Emitting Diode, OLED) display panel.The array substrate can also include cathode and be located at
Organic function layer between anode and cathode.
It is described in detail below by production method of the specific embodiment to array substrate provided in an embodiment of the present invention.
(1) it can use chemical vapour deposition technique and deposit one layer of shading metallic film, shading metal foil on underlay substrate 1
Film can be the metals such as molybdenum or molybdenum niobium alloy, and thickness can be 0.10 μm~0.15 μm, followed by exposure, development and wet process
Shading metal layer 7 is formed after etching, specifically, wet etching shading metallic film can be used nitration mixture and perform etching；It then can be with
One layer is deposited on the underlay substrate 1 for being formed with shading metal layer 2 using the method for chemical vapour deposition technique or magnetron sputtering
Buffer layer 8, specifically, the material of the buffer layer 8 can be silica, and thickness can be 0.3 μm~0.5 μm；It then can benefit
With chemical vapour deposition technique on buffer layer 8 depositing metal oxide semiconductive thin film, it is then thin to metal-oxide semiconductor (MOS)
Film carries out a patterning processes and forms active layer 21, i.e., after photoresist coating, is exposed with common mask plate to photoresist
Light, development, etching form active layer 21, and specifically, the material of active layer 4 can be tin indium oxide (IGZO), and thickness can be
0.05 μm~0.1 μm；Then the method that can use chemical vapour deposition technique or magnetron sputtering is being formed with active layer 21
One layer of grid insulating film is deposited on underlay substrate 1, specifically, the material of the grid insulating film can be silica, thickness
It is 0.1 μm~0.2 μm；Then it is thin that the method that can use magnetron sputtering deposits one layer of gate metal on grid insulating film
Film, specifically, gate metal film can be copper metal, and specifically, the thickness of gate metal film can be 0.4 μm~0.5 μ
m；Then grid 23 is formed by patterning processes and specifically coat photoresist on gate metal film, then utilize mask plate
Photoresist is exposed, and forms grid 23 after development, etching, this etching technics can be copper wet-etching technique, can adopt
Wet etching is carried out with hydrogenperoxide steam generator；After the completion of 23 wet etching of grid, retain gate mask (the i.e. photoresist figure of 23 top of grid
Case) dry etching processing is carried out to grid insulating film, gate insulating layer 22 is formed, specifically, flow, which can be used, is
The CF of 2000sccm~2500sccm4The O for being 1000sccm~1500sccm with flow2Mixed gas protects unglazed photoresist
Grid insulating film carries out dry etching；After forming gate insulating layer 22, continue the gate mask for retaining 23 top of grid
(i.e. photoetching agent pattern) carries out at conductor to the active layer 21 exposed after dry etching processing is carried out in gate insulating layer
Reason.Since active layer 21 includes by channel region that gate insulating layer 22 covers and the source contact for being located at channel region two sides
Therefore region drain contact region by carrying out conductor processing to source contact area and drain contact region, can reduce shape i.e.
At source electrode 24, drain electrode 25 and active layer 21 contact resistance, improve electric conductivity.Specifically, ammonia (NH can be used3) or
Helium (He) carries out conductor processing；Then, wet process removing is carried out to photoresist；Then insulating layer 9 between depositing from level to level, interlayer
The material of insulating layer 9 can be silica, and thickness can be 0.45 μm~0.6 μm, a layer photoresist is subsequently coated with, then using covering
Diaphragm plate is exposed photoresist, and forms contact hole corresponding with the source electrode and drain electrode that will be formed after development, etching, with
Just it is electrically connected source-drain electrode and 21 layers active, dry etching carries out wet process removing after going out contact hole；Then one layer of drain metallic film is deposited,
Drain metallic film can be the metals such as copper and aluminium, with a thickness of 0.5 μm~0.7 μm, form source electrode 24 and drain electrode by photoetching wet etching
25；Then one layer of passivation layer 3 is deposited on the underlay substrate 1 for forming source 24 and drain electrode 25, the material of passivation layer 3 can be oxygen
SiClx-top/nitridation silicon/oxidative silicon-bottom composite layer, it is contemplated that characteristic is influenced, silica-top thickness can be 0.1 μ
M~0.2 μm, silicon nitride thickness can be 0.03 μm~0.05 μm, and silica-bottom thickness can be 0.1 μm~0.2 μm, such as
Shown in Fig. 3 A.
(2) color blocking layer 4 is formed on passivation layer 3 specifically can successively carry out Blue, Green and Red color blocking process；
Then planarization layer 5 is formed on the underlay substrate 1 for be formed with color blocking layer 4, by patterning processes in the top of thin film transistor (TFT) 2
First through hole P1 is formed in corresponding planarization layer 5 and specifically coats photoresist on planarization layer 5, then utilizes mask plate
Photoresist is exposed, and forms first through hole P1 after development, etching, the removing of photoresist wet process is then carried out, such as Fig. 3 B
It is shown.
(3) photoresist layer is formed on the planarization layer with first through hole P1, then using intermediate tone mask plate to light
Photoresist layer is exposed, develops and etches, and forms photoetching agent pattern, as shown in Figure 3 C；Specifically, photoetching agent pattern includes complete
Removal region 01, first part retain region 02, second part retains region 03 and region 04 is fully retained；Wherein, it goes completely
Except region 01 within the scope of first through hole P1 and above drain electrode 25, first part retains region 02 and is covered by first through hole P1
Lid is fully retained region 04 and covers 4 region of color blocking layer.Specifically, photoresist layer is positive photoresist, and thickness can be
2.1 μm, due to the mobility of photoresist, the photoresist in the first through hole P1 of planarization layer 5 can be made with a thickness of 3 μm -3.6 μm,
Therefore the photoetching agent pattern in region 04 is fully retained with a thickness of 1.5 μm -1.8 μm in the photoresist that first part retains region 02
With a thickness of 2.1 μm, second part retain the photoetching agent pattern in region 03 with a thickness of 1.7 μm -1.9 μm.It uses through the invention
Intermediate tone mask plate the photoresist in the first through hole P1 of planarization layer 5 meet etching to require, and thickness will not be because
The mobility of photoresist and it is thicker, and the corresponding photoresist thickness in the top of color blocking layer 4 is thicker, and being resistant to subsequent passivation layer 3 etches, no
Dry etching damage can be generated to planarization layer 5, improve the reliability of panel；And second part is retained to the photoresist in region 03
The thickness of pattern is reduced to the 10%~20% of former photoresist, is easily peeled off in this way in subsequent stripping photoresist.
(4) using photoetching agent pattern (02,03 and 04) as blocking, dry etching processing, tool are carried out to the passivation layer 3 of exposing
Body, dry etching processing is carried out to passivation layer 3 using dry etching twice, first time dry etching uses CF4(content is
35%~45%)+O2(content is 55%~65%) carries out, and is carried out using high source power and high bias power, and etching is about
The passivation layer of 50% thickness, due to O2Content is higher and the first through hole of planarization layer 4 in P1 photoresist thickness it is not thick, meet
Etching requires, and makes passivation layer 3 that can etch preferable dry etching angle；Second of dry etching uses CF4(content be 65%~
85%)+O2(content is 15%~35%) carries out, and is carried out using high source power and high bias power, etches remaining
The passivation layer 3 of 50% thickness, due to CF4Content is higher, etches comparatively fast to passivation layer 3, can be relatively steep to the angle of 3 dry etching of passivation layer
(60 °~70 °), after twice etching, passivation layer 3 is completely removing the second through-hole P2 of the corresponding position in region 01 formation, with
Stripping photoresist pattern afterwards, as shown in Figure 3D.
(5) anode 6 is formed on planarization layer 5, anode 6 is electrically connected by the second through-hole P2 with drain electrode 25, such as Fig. 3 E institute
Show.
Array substrate provided in an embodiment of the present invention can be produced after (1) to step (5) through the above steps.
Based on the same inventive concept, the embodiment of the invention also provides a kind of display panels, including the embodiment of the present invention to mention
The above-mentioned array substrate supplied.The implementation of the display panel may refer to the embodiment of above-mentioned array substrate, and it is no longer superfluous to repeat place
It states.
Based on the same inventive concept, the embodiment of the invention also provides a kind of display devices, including the embodiment of the present invention to mention
The above-mentioned display panel supplied.The display device can be with are as follows: mobile phone, tablet computer, television set, display, laptop, number
Any products or components having a display function such as photo frame, navigator.The implementation of the display device may refer to above-mentioned array base
The embodiment of plate, overlaps will not be repeated.
Production method, display panel and the display device of array substrate provided in an embodiment of the present invention, by being formed in
Photoresist layer on planarization layer carries out patterned process, makes not having in the part first through hole above the drain electrode of thin film transistor (TFT)
Photoresist layer, first through hole other parts reserve part divide that photoresist layer, corresponding photoresist layer is fully retained above color blocking layer；
In this way it is subsequent to passivation layer carry out dry etching processing when, due to first through hole other parts only reserve part be divided photoresist
Layer, the photoresist layer that the other parts of middle first through hole are fully retained compared with the prior art is relatively thin, and the present invention is conducive in dry etching
Preferable dry etching Profile is formed when passivation layer；In addition the relatively existing skill of photoresist layer thickness in the present invention above color blocking layer
Photoresist layer thickness in art above color blocking layer is thicker, and when carrying out dry etching to passivation layer, the present invention can be prevented in color blocking
The planarization layer of side generates dry etching damage, avoids so that subsequent organic luminous layer vapor deposition exception and organic film transmitance reduced
It may.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (13)
1. a kind of production method of array substrate characterized by comprising
Thin film transistor (TFT), passivation layer, color blocking layer and planarization layer are sequentially formed on underlay substrate；Wherein, the film crystal
Pipe and orthographic projection of the color blocking layer on the underlay substrate are not overlapped, and the planarization layer is upper the thin film transistor (TFT)
Side has first through hole；
Photoresist layer is formed on the planarization layer with the first through hole；
Patterned process is carried out to the photoresist layer, forms photoetching agent pattern；The photoetching agent pattern includes completely removing area
Domain, first part retain region and region are fully retained；Wherein, it is described completely remove region within the scope of the first through hole and
Above the drain electrode, the first part retains region and is covered by the first through hole, and area is fully retained in the photoresist
Domain covers the color blocking layer region；
Using the photoetching agent pattern as blocking, dry etching processing is carried out to the passivation layer of exposing, the passivation layer exists
The corresponding position in region that completely removes forms the second through-hole；
Remove the photoetching agent pattern；
Anode is formed on the planarization layer, the anode is electrically connected by second through-hole with the drain electrode.
2. the production method of array substrate as described in claim 1, which is characterized in that the photoetching agent pattern further includes second
Part retains region, and the second part retains region and the thin film transistor (TFT) and the color blocking layer in the underlay substrate
On orthographic projection be not overlapped, and the second part retain region photoresist thickness be greater than the first part retain region
Photoresist thickness.
3. the production method of array substrate as claimed in claim 2, which is characterized in that patterned to the photoresist layer
Processing, specifically includes: carrying out patterned process to the photoresist layer using intermediate tone mask plate；The intermediate tone mask plate packet
It includes: completely removing the corresponding complete transmission region in region with described, retain the corresponding first part in region with the first part
Transmission region retains the corresponding second part transmission region in region with the second part, and described that region is fully retained is corresponding
Light tight region；The light transmission capacity of first part's transmission region is the 50% of the light transmission capacity of the complete transmission region, institute
State second part transmission region light transmission capacity be the complete transmission region light transmission capacity 10%~20%.
4. the production method of array substrate as claimed in claim 3, which is characterized in that the first part retains the light in region
Photoresist pattern with a thickness of 1.5 μm -1.8 μm, the photoetching agent pattern that region is fully retained with a thickness of 2.1 μm, described
Two parts retain region photoetching agent pattern with a thickness of 1.7 μm -1.9 μm.
5. the production method of array substrate according to any one of claims 1-4, which is characterized in that the passivation to exposing
Layer carries out dry etching processing, specifically includes:
Using O2And CF4Combination gas to the passivation layer carry out dry etching processing, the O2With the CF4Ratio be become
Change.
6. the production method of array substrate as claimed in claim 5, which is characterized in that using dry etching at least twice to institute
It states passivation layer and carries out dry etching processing, wherein the O in dry etching each time2And CF4Ratio fix, adjacent dry method twice
O in etching2And CF4Ratio be variation.
7. the production method of array substrate as claimed in claim 6, which is characterized in that using dry etching twice to described blunt
Change layer and carry out dry etching processing, wherein O in first time dry etching2Ratio be greater than O in second dry etching2Ratio.
8. the production method of array substrate as claimed in claim 7, which is characterized in that O in the first time dry etching2's
The content that content is 55%~65%, CF4 is 35%~45%；O in second of dry etching2Content be 15%~
The content of 35%, CF4 are 65%~85%.
9. the production method of array substrate as claimed in claim 5, which is characterized in that using a dry etching to described blunt
Change layer and carries out dry etching processing, during the treatment, the O2Ratio gradually decrease.
10. a kind of array substrate, which is characterized in that be made using such as the described in any item production methods of claim 1-9.
11. array substrate as claimed in claim 10, which is characterized in that the section of second through-hole and the underlay substrate
Between have at least two angles of gradient, along the underlay substrate be directed toward far from the underlay substrate direction, the angle of gradient
Degree gradually decreases.
12. a kind of display panel, which is characterized in that including the array substrate as described in right wants 11.
13. a kind of display device, which is characterized in that including the display panel as described in right wants 12.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910464234.4A CN110164873B (en) | 2019-05-30 | 2019-05-30 | Manufacturing method of array substrate, display panel and display device |
| PCT/CN2020/081886 WO2020238384A1 (en) | 2019-05-30 | 2020-03-27 | Array substrate manufacturing method, array substrate, display panel, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910464234.4A CN110164873B (en) | 2019-05-30 | 2019-05-30 | Manufacturing method of array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110164873A true CN110164873A (en) | 2019-08-23 |
| CN110164873B CN110164873B (en) | 2021-03-23 |
Family
ID=67630497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910464234.4A Active CN110164873B (en) | 2019-05-30 | 2019-05-30 | Manufacturing method of array substrate, display panel and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110164873B (en) |
| WO (1) | WO2020238384A1 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769037A (en) * | 2020-05-29 | 2020-10-13 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
| WO2020238384A1 (en) * | 2019-05-30 | 2020-12-03 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate, display panel, and display device |
| CN113054149A (en) * | 2021-03-17 | 2021-06-29 | 昆山国显光电有限公司 | Display panel manufacturing method and display panel |
| CN113097409A (en) * | 2021-03-17 | 2021-07-09 | 深圳市华星光电半导体显示技术有限公司 | Display panel, display device and manufacturing method of display panel |
| CN113113353A (en) * | 2021-04-12 | 2021-07-13 | 合肥鑫晟光电科技有限公司 | Preparation process of array substrate, array substrate and display device |
| CN113540127A (en) * | 2021-07-19 | 2021-10-22 | 合肥鑫晟光电科技有限公司 | Back plate, display panel, display device and preparation method of display device |
| CN113571587A (en) * | 2021-07-14 | 2021-10-29 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and manufacturing method of array substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112859510A (en) * | 2021-01-28 | 2021-05-28 | 江苏高光半导体材料有限公司 | Mask plate and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100270538A1 (en) * | 2009-04-23 | 2010-10-28 | Samsung Mobile Display Co., Ltd | Organic light emitting display device and method of manufacturing the same |
| CN104538357A (en) * | 2015-01-13 | 2015-04-22 | 合肥京东方光电科技有限公司 | Method for manufacturing array substrate and array substrate |
| CN106783883A (en) * | 2016-12-27 | 2017-05-31 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof |
| CN107068725A (en) * | 2017-04-26 | 2017-08-18 | 京东方科技集团股份有限公司 | Active matrix organic light-emitting diode backboard and its manufacture method |
| CN108565357A (en) * | 2018-01-09 | 2018-09-21 | 深圳市华星光电半导体显示技术有限公司 | A kind of OLED display panel of inkjet printing and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151369B (en) * | 2013-02-06 | 2016-01-06 | 京东方科技集团股份有限公司 | A kind of dot structure and preparation method thereof |
| CN103943649B (en) * | 2013-02-15 | 2017-10-03 | 上海天马微电子有限公司 | OLED display panel and its driving method |
| CN103219336B (en) * | 2013-03-29 | 2016-06-29 | 京东方科技集团股份有限公司 | A kind of preparation method of array base palte, display device and array base palte |
| CN110164873B (en) * | 2019-05-30 | 2021-03-23 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, display panel and display device |
-
2019
- 2019-05-30 CN CN201910464234.4A patent/CN110164873B/en active Active
-
2020
- 2020-03-27 WO PCT/CN2020/081886 patent/WO2020238384A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100270538A1 (en) * | 2009-04-23 | 2010-10-28 | Samsung Mobile Display Co., Ltd | Organic light emitting display device and method of manufacturing the same |
| CN104538357A (en) * | 2015-01-13 | 2015-04-22 | 合肥京东方光电科技有限公司 | Method for manufacturing array substrate and array substrate |
| CN106783883A (en) * | 2016-12-27 | 2017-05-31 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof |
| CN107068725A (en) * | 2017-04-26 | 2017-08-18 | 京东方科技集团股份有限公司 | Active matrix organic light-emitting diode backboard and its manufacture method |
| CN108565357A (en) * | 2018-01-09 | 2018-09-21 | 深圳市华星光电半导体显示技术有限公司 | A kind of OLED display panel of inkjet printing and preparation method thereof |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020238384A1 (en) * | 2019-05-30 | 2020-12-03 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate, display panel, and display device |
| CN111769037A (en) * | 2020-05-29 | 2020-10-13 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
| CN113054149A (en) * | 2021-03-17 | 2021-06-29 | 昆山国显光电有限公司 | Display panel manufacturing method and display panel |
| CN113097409A (en) * | 2021-03-17 | 2021-07-09 | 深圳市华星光电半导体显示技术有限公司 | Display panel, display device and manufacturing method of display panel |
| CN113054149B (en) * | 2021-03-17 | 2022-08-09 | 昆山国显光电有限公司 | Display panel manufacturing method and display panel |
| CN113113353A (en) * | 2021-04-12 | 2021-07-13 | 合肥鑫晟光电科技有限公司 | Preparation process of array substrate, array substrate and display device |
| CN113113353B (en) * | 2021-04-12 | 2023-09-19 | 合肥鑫晟光电科技有限公司 | Preparation process of array substrate, array substrate and display device |
| CN113571587A (en) * | 2021-07-14 | 2021-10-29 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN113571587B (en) * | 2021-07-14 | 2023-12-01 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN113540127A (en) * | 2021-07-19 | 2021-10-22 | 合肥鑫晟光电科技有限公司 | Back plate, display panel, display device and preparation method of display device |
| CN113540127B (en) * | 2021-07-19 | 2023-09-19 | 合肥鑫晟光电科技有限公司 | Backboard, display panel, display device and preparation method of display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110164873B (en) | 2021-03-23 |
| WO2020238384A1 (en) | 2020-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110164873A (en) | Production method, array substrate, display panel and the display device of array substrate | |
| CN108538890A (en) | A kind of organic light-emitting display device | |
| CN105914183B (en) | The manufacturing method of TFT substrate | |
| CN104867942B (en) | The preparation method and its structure of TFT substrate | |
| CN104867959B (en) | The preparation method and its structure of dual gate oxide semiconductor TFT substrate | |
| CN107863451B (en) | A kind of preparation method of OLED anode and the preparation method of OLED display | |
| CN104867870B (en) | The preparation method and its structure of dual gate oxide semiconductor TFT substrate | |
| KR20130094161A (en) | Thin film transistor, thin film transistor array substrate, and method of fabricating the same | |
| CN102709234B (en) | Thin-film transistor array base-plate and manufacture method thereof and electronic device | |
| EP3703112A1 (en) | Method for manufacturing oled backplane | |
| WO2018223731A1 (en) | Organic electroluminescent display panel and preparation method therefor | |
| CN102842601B (en) | Array substrate and manufacture method thereof | |
| CN109411522A (en) | A kind of transparent display panel and preparation method thereof, display device | |
| CN104538428A (en) | Structure and manufacturing method of COA type WOLED | |
| CN109300840A (en) | Display base plate and its manufacturing method, display device | |
| US10784287B2 (en) | TFT substrate and manufacturing method thereof | |
| CN109920845A (en) | Array substrate and its manufacturing method, display panel, display device | |
| CN110148601A (en) | A kind of array substrate, its production method and display device | |
| CN106784014A (en) | Thin film transistor (TFT) and preparation method thereof, display base plate, display device | |
| CN108766989A (en) | A kind of optical sensor device and preparation method thereof, display device, display equipment | |
| US10431743B2 (en) | Manufacturing method of an OLED anode and an OLED display device thereof | |
| CN110098201A (en) | Transistor device and its manufacturing method, display base plate, display device | |
| CN109728001A (en) | A kind of array substrate and preparation method thereof, display panel | |
| US9716117B2 (en) | Method for producing a via, a method for producing an array substrate, an array substrate, and a display device | |
| WO2016123979A1 (en) | Thin-film transistor and manufacturing method therefor, array substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |