CN113113353A - Preparation process of array substrate, array substrate and display device - Google Patents
Preparation process of array substrate, array substrate and display device Download PDFInfo
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- CN113113353A CN113113353A CN202110391099.2A CN202110391099A CN113113353A CN 113113353 A CN113113353 A CN 113113353A CN 202110391099 A CN202110391099 A CN 202110391099A CN 113113353 A CN113113353 A CN 113113353A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The application relates to the technical field of display, in particular to a preparation process of an array substrate, the array substrate and a display device. The preparation process of the array substrate comprises the following steps: performing wet etching on the first film layer to form a first blind hole; forming a second film layer on one side of the first film layer subjected to etching, wherein the second film layer covers the first blind hole; wet etching is carried out on the second film layer at the position aligned with the first blind hole, and a second blind hole is formed; and carrying out dry etching on the second blind hole to form a via hole penetrating through the first film layer and the second film layer. This application is through wet etching step by step, and first step carries out wet etching to first rete and forms the first blind hole that does not run through first rete, and wet etching of second step only is to the second rete, and the second rete covers first blind hole completely, and the second rete after through the wet etching for the second time can seal the interface between second rete and the first rete, prevents that etching solution from transversely getting into the interface and boring the carving to avoid appearing the sculpture crack.
Description
Technical Field
The present disclosure generally relates to the field of display technologies, and in particular, to a manufacturing process of an array substrate, an array substrate and a display device.
Background
In the related art, a top gate TFT (Thin Film Transistor) is widely used and receives more and more attention. The main preparation process of the top gate type TFT is as follows: a light shielding layer, a buffer layer, an active layer, a grid insulating layer and a grid are sequentially deposited and formed on a substrate, and in the preparation process, a dry etching process is needed to prepare a through hole penetrating through an interlayer dielectric layer and the buffer layer.
The size of the display panel is larger and higher, and the resolution is higher and higher, which requires that the metal traces be made narrow enough to reduce the propagation Delay (RC Delay) and increase the aperture ratio. However, since the gate layer and the source drain layer of the top gate TFT are both thick, the interlayer dielectric layer and the like which need to be covered thereon are also thick, and further, the through hole which needs to be etched through is deep, the required dry etching time is long, the damage rate of the dry etching process to the photoresist is high, the current process reaches the limit of equipment, and the conventional dry etching process cannot be adopted for punching along with the further increase of the hole depth of the interlayer dielectric layer to be etched.
Based on the above process problems, the prior art considers that wet etching is performed by using an etching solution, but in the wet etching process, because the compactness of the buffer layer is high and the interlayer dielectric layer is mounted on the active layer, the compactness is low, so that the difference between the film qualities of the buffer layer and the interlayer dielectric layer is large, the etching solution is etched at the junction of the buffer layer and the interlayer dielectric layer, and transverse drilling and etching are easy to occur, and etching cracks are generated.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the technical problem that etching cracks can appear in wet etching in the prior art, the application provides a preparation process of an array substrate, the array substrate and a display device, wherein the preparation process of the array substrate, the array substrate and the display device are used for avoiding the occurrence of the etching cracks at film layer junctions.
In order to achieve the purpose of the invention, the following technical scheme is adopted in the application:
according to a first aspect of embodiments of the present application, there is provided a manufacturing process of an array substrate, including the following steps:
performing wet etching on the first film layer to form a first blind hole;
forming a second film layer on one side of the first film layer subjected to etching, wherein the second film layer covers the first blind hole;
wet etching is carried out on the second film layer at the position aligned with the first blind hole, and a second blind hole is formed;
and carrying out dry etching on the bottom of the second blind hole to form a via hole penetrating through the first film layer and the second film layer.
In one embodiment, the step of wet etching the second film layer in alignment with the first blind hole further includes: and carrying out wet etching on the second film layer at the position aligned with the first blind hole to form the second blind hole which penetrates through or does not penetrate through the second film layer.
In one embodiment, in the step of dry etching the bottom of the second blind via, the method further includes: and carrying out dry etching on the first film layer positioned at the bottom of the first blind hole, or simultaneously carrying out dry etching on the first film layer positioned at the bottom of the first blind hole and the second film layer positioned at the bottom of the second blind hole.
In one embodiment, before the step of wet etching the first film layer, the method further includes the following steps:
forming a light-shielding layer on a base substrate;
forming the first film layer on one side of the light shielding layer, which is far away from the substrate;
in one embodiment, in the step of performing wet etching on the first film layer, the method further includes: and performing wet etching on one side of the first film layer, which is far away from the light shielding layer, to form the first blind hole.
In one embodiment, before the step of forming the second film layer on the side where the first film layer is etched, the method further comprises the following steps:
forming an active layer isolated from the first blind hole on one side of the first film layer subjected to etching;
the second film layer is formed on the active layer, the first blind hole and the first film layer together.
In one embodiment, in the step of performing wet etching on the first film layer, the method further includes: and coating photoresist on the first film layer, forming a mask with a first etching hole on the photoresist, and performing wet etching at the first etching hole.
In one embodiment, in the step of forming the second film layer on the side where the first film layer is etched, the method further includes: and filling inorganic matters into one side of the first film layer subjected to etching to form the second film layer.
In one embodiment, the step of wet etching the second film layer in alignment with the first blind hole further includes: and coating photoresist on the second film layer aligned with the first blind hole, forming a mask with a second etching hole on the photoresist, and performing wet etching at the second etching hole.
According to a second aspect of the embodiments of the present application, there is provided an array substrate prepared by the process for preparing an array substrate according to any one of the embodiments, the array substrate including:
the first film layer is provided with a first blind hole;
and the second film layer is positioned on one side of the first film layer, where the first blind hole is formed, covers the first blind hole, is aligned with the first blind hole, and is provided with a second blind hole, and the bottom of the second blind hole is provided with a through hole penetrating through the first film layer and the second film layer.
According to an embodiment of the present application, the first and second layers are both formed by depositing silicon oxide.
According to an embodiment of the present disclosure, the first film layer is a buffer layer, and the second film layer is an interlayer dielectric layer.
According to an embodiment of the present application, the depth of the first blind hole is d1The thickness of the first film layer at the wet etching position is D1(ii) a Wherein d is1＜D1。
According to an embodiment of the present application, the second blind hole has a depth d2The thickness of the second film layer at the wet etching position is D2(ii) a Wherein d is2≤D2。
According to an embodiment of the present application, the via hole has a depth d3The sum of the thicknesses of the first film layer and the second film layer at the wet etching position is D3(ii) a Wherein d is3＝D3。
According to a third aspect of the embodiments of the present application, a display device includes the array substrate according to any one of the embodiments.
According to the technical scheme, the preparation process of the array substrate, the array substrate and the display device have the advantages and positive effects that:
according to the embodiment of the application, the wet etching is performed step by step, namely, the first wet etching is only performed on the first film layer, the formed first blind hole does not penetrate through the first film layer, so that the etching liquid is only etched in the first film layer and cannot appear at the film layer boundary, the second wet etching is only performed on the second film layer, the second film layer completely covers the first blind hole, the second blind hole formed after the second film layer is etched can cover the first blind hole, namely, the second film layer after the second wet etching can seal the interface between the second film layer and the first film layer, the etching liquid is prevented from transversely entering the interface to be etched, etching cracks are prevented from appearing at the film layer boundary, and finally, through holes are formed through the residual part of the dry etching, the yield of a product is improved, and the performance of the product is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIGS. 1(a) -1(d) are schematic diagrams of intermediate structures produced during a fabrication process of a prior art array substrate;
FIG. 2 is a scanning electron microscope image of a crack generated by a manufacturing process of an array substrate in the prior art;
FIG. 3 is a process flow diagram illustrating a fabrication process of an array substrate according to an exemplary embodiment;
fig. 4(a) -4(e) are schematic views illustrating intermediate structures generated during a fabrication process of an array substrate according to an exemplary embodiment.
Wherein the reference numerals are as follows:
1. a light-shielding layer; 2. a first film layer; 21. a first blind hole; 3. a second film layer; 31. a second blind hole; 4. an active layer; 5. a via hole; 6. a base substrate.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
In the related art, the size of the display panel is larger and higher, and the resolution is higher and higher, which requires that the metal traces be made narrow enough to reduce the propagation delay and increase the aperture ratio. However, since the gate layer and the source drain layer of the top gate TFT are thick, the interlayer dielectric layer and the like which need to be covered thereon are also thick, and further, the through hole which needs to be etched through is deep, the required dry etching time is long, the damage rate of the dry etching process to the photoresist is high, the current process reaches the limit of equipment, and the conventional dry etching process cannot be adopted for punching along with the further increase of the hole depth of the interlayer dielectric layer to be etched.
Based on the above process problems, the prior art considers that wet etching is performed by using an etching solution, but an active layer needs to be formed on a buffer layer, and an interlayer dielectric layer is formed on the active layer, so that the compactness of the buffer layer is high, the compactness of the interlayer dielectric layer is low, the difference between the film qualities of the buffer layer and the interlayer dielectric layer is large, and the existing etching solution etches the junction of the buffer layer and the interlayer dielectric layer, so that transverse drilling and etching are easy to occur, and etching cracks are generated.
Fig. 1(a) -1(d) are schematic diagrams of intermediate structures generated during a process of manufacturing an array substrate in the prior art, fig. 2 is a scanning electron microscope diagram of cracks generated during the process of manufacturing the array substrate in the prior art, and as can be seen from fig. 1(a) -1(d) and fig. 2, the array substrate includes a substrate 6, a Light shield 1, a Buffer layer 2, an active layer 4 and an interlayer dielectric layer 3, which are sequentially disposed, a first blind hole 21 that does not penetrate through the interlayer dielectric layer 3 is first formed on the interlayer dielectric layer 3 by an etching solution, then the interlayer dielectric layer 3 and the Buffer layer 2 are simultaneously etched by the etching solution to form a second blind hole 31 that penetrates through the interlayer dielectric layer 3 but does not penetrate through the Buffer layer 2, and finally a via hole 5 that penetrates through the interlayer dielectric layer 3 and the Buffer layer 2 is formed by dry etching the bottom of the second blind hole 31, in the process of the second wet etching step, the etching liquid can transversely enter two sides of the film layer junction of the interlayer dielectric layer 3 and the buffer layer 2 to be etched, and cracks are formed.
Based on the consideration of the above problems, an embodiment of the present application provides a preparation process of an array substrate, including the following steps:
performing wet etching on the first film layer to form a first blind hole;
forming a second film layer on one side of the first film layer subjected to etching, wherein the second film layer covers the first blind hole;
wet etching is carried out on the second film layer at the position aligned with the first blind hole, and a second blind hole is formed;
and carrying out dry etching on the bottom of the second blind hole to form a via hole penetrating through the first film layer and the second film layer.
The second blind hole is formed in two forms, the first blind hole penetrates through the second film layer, the second blind hole does not penetrate through the second film layer but cannot be etched into the first film layer, and the two forms can both ensure that etching liquid cannot enter the junction of the first film layer and the second film layer. In the first mode, after penetrating through the second film layer, the bottom of the first blind hole is exposed, the thickness of the bottom of the hole, namely the thickness of the first film layer at the bottom of the hole, is about 1000 angstroms, but the second film layer still surrounds the junction of the second film layer and the first film layer, so that the second film layer is prevented from being transversely etched; most preferably, in the second mode, a mode that the second film layer does not penetrate through is adopted, so that the second film layer with the thickness of 500 angstroms and the first film layer with the thickness of 500 angstroms can be left (the numerical values are exemplified, only the first film layer and the second film layer with the thickness of about 1000 angstroms are needed to be left finally, so that the dry etching time is short), so that the etching liquid can not enter the first film layer in the second step of wet etching, and the effect of preventing cracks is achieved better.
For a more particular understanding of the technical idea of the present application, exemplary embodiments are described below with reference to the accompanying drawings:
fig. 3 is a process flow diagram illustrating a manufacturing process of an array substrate according to an exemplary embodiment, and fig. 4(a) -4(e) are schematic diagrams illustrating intermediate structures generated during the manufacturing process of the array substrate according to an exemplary embodiment, and it can be seen in fig. 3 and fig. 4(a) -4(e) that the embodiment of the present application provides a manufacturing process of an array substrate, including the following steps:
s001, as shown in FIGS. 4(a) -4(b), performing wet etching on the first film layer 2 to form a first blind hole 21;
s002, as shown in FIG. 4(c), forming a second film layer 3 on the side where the first film layer 2 is etched, wherein the second film layer 3 covers the first blind hole 21;
s003, as shown in FIG. 4(d), wet etching is carried out on the second film layer 3 at the position aligned with the first blind hole 21 to form a second blind hole 31;
and S004, as shown in FIG. 4(e), performing dry etching on the bottom of the second blind hole 31 to form a via hole 5 penetrating through the first film layer 2 and the second film layer 3.
In the embodiment of the application, the wet etching is performed step by step, that is, the first step wet etching is only performed on the first film layer 2, as shown in fig. 4(a) -4(b), the formed first blind hole 21 does not penetrate through the first film layer 2, and no other layer is formed in this step, so that the etching liquid is only etched in the first film layer 2, and does not appear at the film layer boundary, the second step wet etching is only performed on the second film layer 3, as shown in fig. 4(c) -4(d), the second film layer 3 completely covers the first blind hole 21, because the direction of the wet etching is the direction perpendicular to each layer, the second blind hole 31 formed after etching only on the second film layer 3 can also cover the first blind hole 21, that is, the second film layer 3 after the second etching can completely seal the interface between the second film layer 3 and the first film layer 2, so that the etching liquid is prevented from entering the interface along the transverse direction to be etched, and the etching crack at the film layer boundary is avoided, and finally, the residual part is etched by a dry method to form a via hole 5, so that the yield of the product is improved, and the performance of the product is improved.
Before the step of S001, the method also comprises the following steps: first, a light shielding layer 1 is formed on a substrate 6, specifically, the light shielding layer 1 is formed by depositing an insulating material or a conductive material on the substrate 6 and patterning the insulating material or the conductive material, and further, the first film layer 2 is formed on a side of the light shielding layer 1 away from the substrate 6.
In step S001, specifically, wet etching is performed on a side of the first film layer 2 away from the light shielding layer 1, so as to form a first blind hole 21 that does not penetrate through the first film layer 2. In addition, the wet etching in the step is to specifically coat a photoresist on the first film layer 2, form a mask with a first etching hole on the photoresist, and set a light source, when the light source irradiates, the first film layer 2 covered with the mask is not etched by the etching liquid, and the wet etching is performed only at the first etching hole through the etching liquid, so that the accuracy of the wet etching is improved.
In the S002 step, the method further includes the steps of: an active layer 4 isolated from the first blind hole 21 is formed on one side of the first film layer 2 subjected to etching, a grid electrode insulating layer and a grid electrode are sequentially formed on one side of the active layer 4 departing from the first film layer 2, and a second film layer 3 is formed on the active layer 4, the grid electrode insulating layer, the grid electrode, the first blind hole 21 and the first film layer 2 together through filling of inorganic matters.
Specifically, a semiconductor material is deposited on the first film layer 2 and patterned to form an active layer 4, and a gate insulating layer and a gate electrode are sequentially formed on the active layer 4, specifically, an entire gate insulating layer and an entire metal layer for preparing the gate electrode may be sequentially formed on the active layer 4, and then the entire gate insulating layer and the entire metal layer are patterned to obtain the gate insulating layer and the gate electrode.
In addition, a self-aligned process may be further used to conduct a conductive process (i.e., depositing a conductive material and patterning the conductive material) on the active layer 4, so as to divide the active layer 4 into an active region, a first conductive region and a second conductive region, where the first conductive region and the second conductive region are located on two sides of the active region and isolated from the first blind via 21, the first conductive region may be a source region, the second conductive region may be a drain region, and the active region is located in a projection of the gate insulating layer on the active layer 4.
Wherein the active layer 4 is isolated from the first blind via 21, as will be appreciated by those skilled in the art, the second blind via 31 and the via 5 are also isolated from the active layer 4, since the wet etching and the dry etching are performed in a direction perpendicular to the layers.
In the S003 step, the method further includes: the second film layer 3 is subjected to wet etching at the position aligned with the first blind hole 21 to form a second blind hole 31 penetrating or not penetrating the second film layer 3, and no matter whether the second blind hole 31 penetrates the second film layer 3 or not, the etching liquid is only positioned in the second film layer 3 and cannot enter the first film layer 2. Preferably, the second blind hole 31 may not completely penetrate the second membrane layer 3, so as to better prevent the etching solution from entering the membrane layer interface between the second membrane layer 3 and the first membrane layer 2, prevent the generation of etching cracks, and improve the yield of the product. Specifically, the wet etching in this step is to coat a photoresist on the second film layer 3 aligned with the first blind hole 21, form a mask having a second etching hole on the photoresist, and set a light source, so that when the light source irradiates, the second film layer 3 covered with the mask is not etched by the etching liquid, and the wet etching is performed only at the second etching hole, thereby improving the accuracy of the wet etching.
In the step S004, two methods are further included: one is the condition that corresponds second blind hole 31 and runs through second rete 3, only need carry out dry etching to first rete 2 that is located first blind hole 21 bottom, it is the condition that corresponds second blind hole 31 and does not run through second rete 3, then need carry out dry etching to first rete 2 that is located first blind hole 21 bottom and second rete 3 that is located second blind hole 31 bottom, the surplus thickness that needs to carry out dry etching is about 1000 angstroms meters, because the 5 degree of depth of via hole that need the sculpture to be worn through is shallow, so the dry etching time that needs is shorter, damage rate to the photoresist is slower, thereby product quality and product yield can be improved.
Wherein, the etching liquid mainly comprises Hydrogen Fluoride (HF) and ammonium fluoride (NH)4F) And a surfactant, wherein the mass fraction (wt) of hydrogen fluoride is 2-5%, and ammonium fluorideThe mass fraction of the surfactant is 20-40%, and the mass fraction of the surfactant is 1-5%. For example, the mass fraction (wt) of hydrogen fluoride is 2%, 3.5% or 5%, the mass fraction of ammonium fluoride is 20%, 30% or 40%, and the mass fraction of surfactant is 1%, 3% or 5%.
According to a second aspect of the embodiments of the present application, there is provided an array substrate, including a substrate 6, a light shielding layer 1, a first film layer 2, an active layer 4, and a second film layer 3; the light shielding layer 1 is formed on one side of the substrate base plate 6 and does not completely cover the substrate base plate 6, the active layer 4 is arranged on one side of the first film layer 2, which is far away from the substrate base plate 6, and does not completely cover the first film layer 2, and the second film layer 3 completely covers the active layer 4 and one side of the first film layer 2, which is far away from the substrate base plate 6; wherein, first rete 2 forms the first blind hole 21 that does not run through first rete 2 through wet etching, and second rete 3 covers first blind hole 21, and second rete 3 part is located first blind hole 21 promptly, and then forms second blind hole 31 through wet etching to the second rete 3 that aligns first blind hole 21, and second blind hole 31 can run through or does not run through second rete 3, and the bottom of second blind hole 31 forms through hole 5 that runs through first rete 2 and second rete 3 through dry etching.
As will be understood by those skilled in the art, the first film layer 2 is a buffer layer, and the second film layer 3 is an interlayer dielectric layer.
As for the depth of the first blind via 21, since the first blind via 21 does not penetrate through the first film layer 2, the depth of the first blind via 21 should be smaller than the thickness of the first film layer 2 corresponding to the wet etching, i.e. the depth of the first blind via 21 is d1The thickness of the first film layer 2 at the wet etching position is D1(ii) a Wherein d is1＜D1。
For the depth of the second blind hole 31, the second blind hole 31 has two forms, one is penetrating the second film 3 but not entering the first film 2, and the other is not penetrating the second film 3, so the hole depth should be less than or equal to the thickness of the second film 3 at the position corresponding to the wet etching, that is, the depth of the second blind hole 31 is d2The thickness of the second film layer 3 at the wet etching position is D2(ii) a Wherein d is2≤D2。
For the depth of the via hole 5, since the via hole 5 needs to penetrate through the second film layer 3 and the first film layer 2 at the same time, and the etching does not involve the light shielding layer 1, the hole depth of the via hole 5 should be the same as the sum of the thicknesses of the second film layer 3 and the first film layer 2 at the corresponding wet etching position, that is, the depth of the via hole 5 is d3The sum of the thicknesses of the first film layer 2 and the second film layer 3 at the wet etching position is D3(ii) a Wherein d is3＝D3。
For the first blind hole 21, the second blind hole 31 and the via hole 5, the first blind hole 21 includes a first sidewall, the second blind hole 31 includes a second sidewall, and the via hole 5 includes a third sidewall, wherein the projection of the second sidewall on the first film layer 2 falls into the projection of the first sidewall on the first film layer 2, and the projection of the third sidewall on the first film layer 2 falls into the projection of the second sidewall on the first film layer 2. The included angle between the first side wall and the first film layer 2 is alpha, the included angle between the second side wall and the first film layer 2 is beta, the included angle between the third side wall and the first film layer is gamma, alpha is not less than beta and not more than gamma, and the first blind hole 21, the second blind hole 31 and the via hole 5 are all structures which are gradually reduced from top to bottom, namely, the first blind hole 21, the second blind hole 31 and the via hole 5 are gradually steeper and steeper.
For each layer of the array substrate, the light-shielding layer 1 may be made of an insulating material or a conductive material, the insulating material may be opaque black resin, and the conductive material may be a metal or an alloy material, such as aluminum, silver, magnesium-silver alloy, and the like; the first film layer 2 and the second film layer 3 are both made of silicon oxide materials, have good compactness and can play a good role in blocking water and oxygen; the material of the active layer 4 may be a semiconductor material, such as low temperature polysilicon, IGZO (indium gallium zinc oxide), etc., and when the array substrate is used for a large-sized display panel, the material of the active layer 4 is typically IGZO, thereby ensuring better uniformity of the active layer 4.
According to a third aspect of an embodiment of the present application, a display device includes the array substrate of any one of the above embodiments, and further includes a display module.
It should be understood that the display device in this embodiment may be: any product or component with a display function, such as electronic paper, an electronic book, a mobile phone, a tablet computer, a television, a notebook computer, a desktop computer, a digital camera, a digital photo frame, a navigator and the like.
The forming process adopted in the above process may include, for example: deposition, sputtering and other film forming processes and etching and other patterning processes.
It is noted that in the description and claims of the present application and in the above-mentioned drawings, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
Also, the terms "comprises," "comprising," and "having," as well as any variations thereof or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications and changes to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (15)
1. The preparation process of the array substrate is characterized by comprising the following steps of:
carrying out wet etching on the first film layer (2) to form a first blind hole (21);
forming a second film layer (3) on one side of the first film layer (2) subjected to etching, wherein the second film layer (3) covers the first blind hole (21);
wet etching is carried out on the second film layer (3) at the position aligned with the first blind hole (21) to form a second blind hole (31);
and carrying out dry etching on the bottom of the second blind hole (31) to form a via hole (5) penetrating through the first film layer (2) and the second film layer (3).
2. The preparation process of the array substrate according to claim 1, wherein the step of wet etching the second membrane layer (3) at the position aligned with the first blind hole (21) further comprises:
and carrying out wet etching on the second film layer (3) at the position aligned with the first blind hole (21) to form the second blind hole (31) which penetrates or does not penetrate through the second film layer (3).
3. The preparation process of the array substrate according to claim 2, wherein in the step of dry etching the bottom of the second blind via (31), the preparation process further comprises:
and carrying out dry etching on the first film layer (2) positioned at the bottom of the first blind hole (21), or simultaneously carrying out dry etching on the first film layer (2) positioned at the bottom of the first blind hole (21) and the second film layer (3) positioned at the bottom of the second blind hole (31).
4. The preparation process of the array substrate according to claim 1, further comprising the following steps before the step of wet etching the first film layer (2):
forming a light-shielding layer (1) on a base substrate (6);
and forming the first film layer (2) on one side of the light shielding layer (1) departing from the substrate base plate (6).
5. The manufacturing process of the array substrate according to claim 4, wherein in the step of performing the wet etching on the first film layer (2), the method further comprises:
and carrying out wet etching on one side of the first film layer (2) departing from the shading layer (1) to form the first blind hole (21).
6. The preparation process of the array substrate according to claim 1, further comprising the following steps before the step of forming the second film layer (3) on the side where the first film layer (2) is etched:
forming an active layer (4) isolated from the first blind hole (21) on the side of the first film layer (2) subjected to etching;
-collectively forming the second membrane layer (3) on the active layer (4), the first blind hole (21) and the first membrane layer (2).
7. The manufacturing process of the array substrate according to claim 1, wherein in the step of performing the wet etching on the first film layer (2), the method further comprises:
and coating photoresist on the first film layer (2), forming a mask with a first etching hole on the photoresist, and carrying out wet etching at the first etching hole.
8. The manufacturing process of the array substrate according to claim 1, wherein the step of forming the second film layer (3) on the side where the first film layer (2) is etched further comprises:
and filling inorganic matters into the etched side of the first film layer (2) to form the second film layer (3).
9. The preparation process of the array substrate according to claim 1, wherein the step of wet etching the second membrane layer (3) at the position aligned with the first blind hole (21) further comprises:
and coating photoresist on the second film layer (3) aligned with the first blind hole (21), forming a mask with a second etching hole on the photoresist, and performing wet etching at the second etching hole.
10. An array substrate prepared by the process for preparing an array substrate according to any one of claims 1 to 9, the array substrate comprising:
the first film layer (2) is provided with the first blind hole (21);
the second film layer (3) is located on one side, provided with the first blind hole (21), of the first film layer (2), the second film layer (3) covers the first blind hole (21), the second film layer (3) aligned with the first blind hole (21) is provided with the second blind hole (31), and the bottom of the second blind hole (31) is provided with a through hole (5) penetrating through the first film layer (2) and the second film layer (3).
11. The array substrate of claim 10, wherein the first film layer (2) is a buffer layer and the second film layer (2) is an interlayer dielectric layer.
12. The array substrate of claim 10, wherein the first blind hole (21) has a depth d1The thickness of the first film layer (2) at the wet etching position is D1(ii) a Wherein d is1＜D1。
13. The array substrate of claim 10, wherein the second blind hole (31) has a depth d2The thickness of the second film layer (3) at the wet etching position is D2(ii) a Wherein d is2≤D2。
14. The array substrate of claim 10, wherein the via (5) has a depth d3The sum of the thicknesses of the first film layer (2) and the second film layer (3) at the position of wet etching is D3(ii) a Wherein d is3＝D3。
15. A display device comprising the array substrate according to any one of claims 10 to 14.
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